Category Archives: Process Materials

Engineers at MIT have devised a new technique for trapping hard-to-detect molecules, using forests of carbon nanotubes.

The team modified a simple microfluidic channel with an array of vertically aligned carbon nanotubes — rolled lattices of carbon atoms that resemble tiny tubes of chicken wire. The researchers had previously devised a method for standing carbon nanotubes on their ends, like trees in a forest. With this method, they created a three-dimensional array of permeable carbon nanotubes within a microfluidic device, through which fluid can flow.

Now, in a study published this week in the Journal of Microengineering and Nanotechnology, the researchers have given the nanotube array the ability to trap certain particles. To do this, the team coated the array, layer by layer, with polymers of alternating electric charge.

“You can think of each nanotube in the forest as being concentrically coated with different layers of polymer,” says Brian Wardle, professor of aeronautics and astronautics at MIT. “If you drew it in cross-section, it would be like rings on a tree.”

Depending on the number of layers deposited, the researchers can create thicker or thinner nanotubes and thereby tailor the porosity of the forest to capture larger or smaller particles of interest.

The nanotubes’ polymer coating may also be chemically manipulated to bind specific bioparticles flowing through the forest. To test this idea, the researchers applied an established technique to treat the surface of the nanotubes with antibodies that bind to prostate specific antigen (PSA), a common experimental target. The polymer-coated arrays captured 40 percent more antigens, compared with arrays lacking the polymer coating.

Wardle says the combination of carbon nanotubes and multilayer coatings may help finely tune microfluidic devices to capture extremely small and rare particles, such as certain viruses and proteins.

“There are smaller bioparticles that contain very rich amounts of information that we don’t currently have the ability to access in point-of-care [medical testing] devices like microfluidic chips,” says Wardle, who is a co-author on the paper. “Carbon nanotube arrays could actually be a platform that could target that size of bioparticle.”

The paper’s lead author is Allison Yost, a former graduate student who is currently an engineer at Accion Systems. Others on the paper include graduate student Setareh Shahsavari; postdoc Roberta Polak; School of Engineering Professor of Teaching Innovation Gareth McKinley; professor of materials science and engineering Michael Rubner, and Raymond A. And Helen E. St. Laurent Professor of Chemical Engineering Robert Cohen.

A porous forest

Carbon nanotubes have been a subject of intense scientific study, as they possess exceptional electrical, mechanical, and optical properties. While their use in microfluidics has not been well explored, Wardle says carbon nanotubes are an ideal platform because their properties may be manipulated to attract certain nanometer-sized molecules. Additionally, carbon nanotubes are 99 percent porous, meaning a nanotube is about 1 percent carbon and 99 percent air.

“Which is what you need,” Wardle says. “You need to flow quantities of fluid through this material to shed all the millions of particles you don’t want to find and grab the one you do want to find.”

What’s more, Wardle says, a three-dimensional forest of carbon nanotubes would provide much more surface area on which target molecules may interact, compared with the two-dimensional surfaces in conventional microfluidics.

“The capture efficiency would scale with surface area,” Wardle notes.

A versatile array

The team integrated a three-dimensional array of carbon nanotubes into a microfluidic device by using chemical vapor deposition and photolithography to grow and pattern carbon nanotubes onto silicon wafers. They then grouped the nanotubes into a cylinder-shaped forest, measuring about 50 micrometers tall and 1 millimeter wide, and centered the array within a 3 millimeter-wide, 7-millimeter long microfluidic channel.

The researchers coated the nanotubes in successive layers of alternately charged polymer solutions in order to create distinct, binding layers around each nanotube. To do so, they flowed each solution through the channel and found they were able to create a more uniform coating with a gap between the top of the nanotube forest and the roof of the channel. Such a gap allowed solutions to flow over, then down into the forest, coating each individual nanotube. In the absence of a gap, solutions simply flowed around the forest, coating only the outer nanotubes.

After coating the nanotube array in layers of polymer solution, the researchers demonstrated that the array could be primed to detect a given molecule, by treating it with antibodies that typically bind to prostate specific antigen (PSA). They pumped in a solution containing small amounts of PSA and found that the array captured the antigen effectively, throughout the forest, rather than just on the outer surface of a typical microfluidic element.

Wardle says that the nanotube array is extremely versatile, as the carbon nanotubes may be manipulated mechanically, electrically, and optically, while the polymer coatings may be chemically altered to capture a wide range of particles. He says an immediate target may be biomarkers called exosomes, which are less than 100 nanometers wide and can be important signals of a disease’s progression.

“Science is really picking up on how much information these particles contain, and they’re sort of everywhere, but really hard to find, even with large-scale equipment,” Wardle says. “This type of device actually has all the characteristics and functionality that would allow you to go after bioparticles like exosomes and things that really truly are nanometer scale.”

A team of engineers from Cornell University, the University of Notre Dame and the semiconductor company IQE has created gallium nitride (GaN) power diodes capable of serving as the building blocks for future GaN power switches — with applications spanning nearly all electronics products and electricity distribution infrastructures.

Power semiconductor devices are a critical part of the energy infrastructure — all electronics rely on them to control or convert electrical energy. Silicon-based semiconductors are rapidly approaching their performance limits within electronics, so materials such as GaN are being explored as potential replacements that may render silicon switches obsolete.

But along with having many desirable features as a material, GaN is notorious for its defects and reliability issues. So the team zeroed in on devices based on GaN with record-low defect concentrations to probe GaN’s ultimate performance limits for power electronics. They describe their results in a paper in the journal Applied Physics Letters, from AIP Publishing.

“Our engineering goal is to develop inexpensive, reliable, high-efficiency switches to condition electricity — from where it’s generated to where it’s consumed within electric power systems — to replace generations-old, bulky, and inefficient technologies,” said Zongyang Hu, a postdoc working in Professor Grace Huili Xing’s research group within the School of Electrical and Computer Engineering at Cornell University. “GaN-based power devices are enabling technologies to achieve this goal.”

The team examined semiconductor p-n junctions, made by joining p-type (free holes) and n-type (free electrons) semiconductor materials, which have direct applications in solar cells, light-emitting diodes (LEDs), rectifiers in circuits, and numerous variations in more complex devices such as power transistors. “For our work, high-voltage p-n junction diodes are used to probe the material properties of GaN,” Hu explained.

To describe how much the device’s current-voltage characteristics deviate from the ideal case in a defect-free semiconductor system, the team uses a “diode ideality factor.” This is “an extremely sensitive indicator of the bulk defects, interface and surface defects, and resistance of the device,” he added.

Defects exist within all materials, but at varying levels. “So one parameter we used to effectively describe the defect level in a material is the Shockley-Read-Hall (SRH) recombination lifetime,” Hu said.

SRH lifetime is the averaged time it takes injected electrons and holes in the junction to move around before recombining at defects. “The lower the defect level, the longer the SRH lifetime,” Hu explained. “It’s also interesting to note that for GaN, a longer SRH lifetime results in a brighter light emission produced by the diode.”

The work is significant because many researchers around the globe are working to find ways to make GaN materials reliable for use within future electronics. Due to the presence of defects with high concentrations in typical GaN materials today, GaN-based devices often operate at a fraction of what GaN is truly capable of.

It’s worth noting that, in 2014, a Nobel Prize in physics was awarded to three scientists for making seminal and breakthrough contributions to the field of GaN-based LEDs. Though operating at compromised conditions, GaN LEDs are helping to shift the global lighting industry to a much more energy-efficient, solid-state lighting era.

The work led by Xing at Cornell University is the first report of GaN p-n diodes with near-ideal performance in all aspects simultaneously: a unity ideality factor, avalanche breakdown voltage, and about a two-fold improvement in device figure-of-merits over previous records.

“Our results are an important step toward understanding the intrinsic properties and the true potential of GaN,” Hu noted. “And these achievements are only possible in high-quality GaN device structures (an effort led by IQE engineers) prepared on high-quality GaN bulk substrates and with precisely tuned fabrication technologies (an effort led by Dr. Kazuki Nomoto, a research associate at Cornell University).”

One big surprise for the team came in the form of unexpectedly low differential-on-resistance of the GaN diode. “It’s as if the body of the entire p-n diode is transparent to the current flow without resistance,” he said. “We believe this is due to high-level injection of minority carriers and their long lifetime, and are exploring it further.”

The team’s work is part of the U.S. Department of Energy’s (DOE) Advanced Research Projects Agency-Energy (ARPA-E) “SWITCHES” program, monitored by Dr. Timothy Heidel. “Leading one of these projects, we at Cornell, in collaboration with our industrial partners IQE, Qorvo, and UTRC, have established an integrated plan to develop three terminal GaN power transistors, package them, and insert them into circuits and products,” Xing said.

Beyond the DOE ARPA-E project, the team is open to collaboration with any researchers or companies interested in helping drive GaN power electronics to its fruition.

At last week’s IEEE International Electron Devices Meeting 2015, nano-electronics research center imec presented three novel aluminum gallium nitride (AlGaN)/ gallium nitride (GaN) stacks featuring optimized low dispersion buffer designs. Moreover, imec optimized the epitaxial p-GaN growth process on 200mm silicon wafers, achieving e-mode devices featuring beyond state-of-the-art high threshold voltage (Vt) and high drive current (Id).

To achieve a good, current-collapse-free device operation in AlGaN/GaN-on-Silicon (Si) devices, dispersion must be kept to a minimum. Trapped charges in the buffer between the GaN-based channel and the silicon substrate are known to be a critical factor in causing dispersion. Imec compared the impact of different types of buffers on dispersion and optimized three types: a classic step-graded buffer, a buffer with low-temperature AlN interlayers, and a super lattice buffer. These three types of buffers were optimized for low dispersion, leakage and breakdown voltage over a wide temperature range and bias conditions.

Imec also optimized the epitaxial p-GaN growth process demonstrating improved electrical performance of p-GaN HEMTs, achieving a beyond state-of-the-art combination of high threshold voltage, low on-resistance and high drive current (Vt >2V, RON = 7 Ω.mm and Id >0.4A/mm at 10V). The P-GaN HEMT results outperformed their MISHEMT counterparts.

Imec’s GaN-on-Si R&D program aims at bringing this technology towards industrialization. Imec’s offering includes a complete 200mm CMOS-compatible 200V GaN process line that features excellent specs on e-mode devices. Imec’s program allows partners early access to next-generation devices and power electronics processes, equipment and technologies, and speed up innovation at shared costs. Current R&D focuses on improving the performance and reliability of imec’s e-mode devices, while in parallel pushing the boundaries of the technology through innovation in substrate technology, higher levels of integration and exploration of novel device architectures.

“Imec’s presentations at the renowned IEDM meeting last week are a testament to the capabilities, sophistication, and maturity of our 200mm GaN-on-Silicon platform,” stated Rudi Cartuyvels, executive vice president of smart systems and energy technology at imec. “Building upon this success, we are now working with our GaN partners to implement and transfer specific device customizations. in parallel, we are exploring alternative substrate technologies to further push the boundaries of the GaN technology.”

At this week’s IEEE IEDM conference, nano-electronics research center imec demonstrates record enhancement of novel InGaAs Gate-All-Around (GAA) channel devices integrated on 300mm Silicon and explores emerging tunnel devices based on optimization of the same III-V compound semiconductor.

III-V-on-Si GAA devices with a record peak transconductance at 0.5V has been achieved by optimizing both the channel epitaxy quality and the gate-channel passivation. In search of device technologies beyond FinFETs and GAA-nanowires for sub-0.5V operations, imec investigates InGaAs Tunnel-FET (TFETs). Homo-junction III-V TFETs achieving a record ON-state current (ION) and superior subthreshold swing have been demonstrated. These results increase the knowledge on the impact of defectivity and channel optimization on device operations, and pave the way to advanced logic devices based on III-V-On-Si for high performance or ultra-low power applications.

Imec’s R&D program on advanced logic scaling is targeting the new and mounting challenges for performance, power, cost, and density scaling for future process technologies. One of the directions that imec is following, looks into beyond-Si solutions, such as integrating high-mobility materials into the channels of CMOS devices to increase their performance, and the integration challenges of these materials with silicon. Gate-All-Around Nanowire (GAA NW) FETs have been proven to offer significantly better short-channel electrostatics, and quantum-well FinFETs (with SiGe, Ge, or III-V channels) achieving high carrier mobility, are interesting concepts to increase device performance. Tunnel FETs, on the other hand, offering a steeper than 60mV/dec subthreshold swing, are a promising option for ultra-low power applications.

At IEDM, imec presented gate-all-around InGaAs Nanowire FETs (Lg=50nm) that performed at an average peak transconductance (gm) of 2200µS/µm with a SSSAT of 110mV/dec. Imec succeeded in increasing the performance by gate stack engineering using a novel gate stack ALD inter-layer (IL) material developed by ASM, and high pressure annealing. The novel IL/HfO2 stack achieved a 2.2 times higher gm for a device with a gate length (Lg) of 50nm, compared to the reference Al2O3/HfO2 stack.

Imec also presented a planar InGaAs homo-junction TFET with 70 percent Indium (In) content. The increase of In content from 53 to 70 percent in a 8nm channel, was found to significantly boost the performance of the device. A record ON-state current (ION) of 4µA/µm (IOFF = 100pA/µm, Vdd = 0.5V and Vd = 0.3V) with a minimum subthreshold swing (SSmin) of 60mV/dec at 300k was obtained for a planar homo-junction TFET device. It was also shown that subthreshold swing and transconductance in TFET devices were more immune to positive bias temperature instability (PBTI) compared to MOSFET devices.

“Imec’s R&D enables Moore’s Law beyond the 5nm technology node through 3 approaches. First, we are tackling the technology challenges to extend silicon CMOS devices towards smaller nodes. At the same time, we research into disruptive heterogeneous solutions for beyond-silicon CMOS devices to increase performance and introduce new functionalities. Lastly, imec pursues emerging beyond-CMOS devices and systems such as spintronics to investigate further functional scaling beyond device-density-driven scaling,” stated Aaron Thean, vice president and director of imec’s advanced logic R&D program. “Boosting the performance of advanced compound semiconductor logic devices is extremely important, and these results support the quest of the semiconductor industry to find solutions that enable 5nm technology nodes and beyond.”

“ASM and imec have a long history of R&D collaboration using many of ASM’s products and advanced deposition and thermal processes,” says Ivo Raaijmakers, ASM CTO and Director of R&D. “As a leader in ALD, we are glad to see this breakthrough new ALD material now demonstrated in imec’s high mobility devices and presented at IEDM 2015.”

Imec’s research into advanced logic scaling is performed in cooperation with imec’s key partners in its core CMOS programs including GlobalFoundries, Intel, Micron, Panasonic, Qualcomm, Samsung, SK Hynix, Sony and TSMC.

TEM of complete gate-all-around InGaAs Nanowire FET and HRTEM of the gatestack

TEM of complete gate-all-around InGaAs Nanowire FET and HRTEM of the gatestack

Researchers from North Carolina State University have discovered a new phase of solid carbon, called Q-carbon, which is distinct from the known phases of graphite and diamond. They have also developed a technique for using Q-carbon to make diamond-related structures at room temperature and at ambient atmospheric pressure in air.

Phases are distinct forms of the same material. Graphite is one of the solid phases of carbon; diamond is another.

“We’ve now created a third solid phase of carbon,” says Jay Narayan, the John C. Fan Distinguished Chair Professor of Materials Science and Engineering at NC State and lead author of three papers describing the work. “The only place it may be found in the natural world would be possibly in the core of some planets.”

Q-carbon has some unusual characteristics. For one thing, it is ferromagnetic — which other solid forms of carbon are not.

“We didn’t even think that was possible,” Narayan says.

In addition, Q-carbon is harder than diamond, and glows when exposed to even low levels of energy.

“Q-carbon’s strength and low work-function — its willingness to release electrons — make it very promising for developing new electronic display technologies,” Narayan says.

But Q-carbon can also be used to create a variety of single-crystal diamond objects. To understand that, you have to understand the process for creating Q-carbon.

Researchers start with a substrate, such as such as sapphire, glass or a plastic polymer. The substrate is then coated with amorphous carbon — elemental carbon that, unlike graphite or diamond, does not have a regular, well-defined crystalline structure. The carbon is then hit with a single laser pulse lasting approximately 200 nanoseconds. During this pulse, the temperature of the carbon is raised to 4,000 Kelvin (or around 3,727 degrees Celsius) and then rapidly cooled. This operation takes place at one atmosphere — the same pressure as the surrounding air.

The end result is a film of Q-carbon, and researchers can control the process to make films between 20 nanometers and 500 nanometers thick.

By using different substrates and changing the duration of the laser pulse, the researchers can also control how quickly the carbon cools. By changing the rate of cooling, they are able to create diamond structures within the Q-carbon.

“We can create diamond nanoneedles or microneedles, nanodots, or large-area diamond films, with applications for drug delivery, industrial processes and for creating high-temperature switches and power electronics,” Narayan says. “These diamond objects have a single-crystalline structure, making them stronger than polycrystalline materials. And it is all done at room temperature and at ambient atmosphere – we’re basically using a laser like the ones used for laser eye surgery. So, not only does this allow us to develop new applications, but the process itself is relatively inexpensive.”

And, if researchers want to convert more of the Q-carbon to diamond, they can simply repeat the laser-pulse/cooling process.

If Q-carbon is harder than diamond, why would someone want to make diamond nanodots instead of Q-carbon ones? Because we still have a lot to learn about this new material.

“We can make Q-carbon films, and we’re learning its properties, but we are still in the early stages of understanding how to manipulate it,” Narayan says. “We know a lot about diamond, so we can make diamond nanodots. We don’t yet know how to make Q-carbon nanodots or microneedles. That’s something we’re working on.”

NC State has filed two provisional patents on the Q-carbon and diamond creation techniques.

Worldwide silicon wafer area shipments decreased during the third quarter 2015 when compared to second quarter area shipments according to the SEMI Silicon Manufacturers Group (SMG) in its quarterly analysis of the silicon wafer industry.

Total silicon wafer area shipments were 2,591 million square inches during the most recent quarter, a 4.1 percent decrease from the record amount of 2,702 million square inches shipped during the previous quarter. New quarterly total area shipments were flat when compared to third quarter 2014 shipments.

“After two consecutive record breaking quarters, quarterly silicon shipment growth slightly declined,” said Ginji Yada, chairman of SEMI SMG and general manager, International Sales & Marketing Department of SUMCO Corporation. “Quarterly shipments for the most recent quarter are on par with the same quarter as last year, with total silicon shipment volumes for 2015 through the end of the third quarter higher relative to the same period last year.”

Quarterly Silicon* Area Shipment Trends

Million Square Inches

Q3-2014

Q2-2015

Q3-2015

9M-2014

9M-2015
Total

2,597

2,702

2,591

7,548

7,930

* Shipments are for semiconductor applications only and do not include solar applications

Silicon wafers are the fundamental building material for semiconductors, which in turn, are vital components of virtually all electronics goods, including computers, telecommunications products, and consumer electronics. The highly engineered thin round disks are produced in various diameters (from one inch to 12 inches) and serve as the substrate material on which most semiconductor devices or “chips” are fabricated.

All data cited in this release is inclusive of polished silicon wafers, including virgin test wafers and epitaxial silicon wafers, as well as non-polished silicon wafers shipped by the wafer manufacturers to the end-users.

The Silicon Manufacturers Group acts as an independent special interest group within the SEMI structure and is open to SEMI members involved in manufacturing polycrystalline silicon, monocrystalline silicon or silicon wafers (e.g., as cut, polished, epi, etc.). The purpose of the group is to facilitate collective efforts on issues related to the silicon industry including the development of market information and statistics about the silicon industry and the semiconductor market.

SEMI recently completed its annual silicon shipment forecast for the semiconductor industry. This forecast provides an outlook for the demand in silicon units for the period 2015–2017. The results show polished and epitaxial silicon shipments totaling 10,042 million square inches in 2015; 10,179 million square inches in 2016; and 10,459 million square inches in 2017 (refer to table below). Total wafer shipments this year are expected to exceed the market high set in 2014 and are forecast to continue shipping at record levels in 2016 and 2017.

“2015 has been a record-breaking year for silicon shipments, attributed primarily to larger diameter wafers,” said Denny McGuirk, president and CEO of SEMI. “The outlook for the next two years is measured, but continues on a modest growth path.”

2015 Silicon Shipment Forecast
Total Electronic Grade Silicon Slices* – Does not Include Non-Polished
(Millions of Square Inches, MSI)

Actual Forecast
2013 2014 2015 2016 2017
MSI 8,834 9,826 10,042 10,179 10,459
Annual Growth 0% 11% 2% 1% 3%

Source: SEMI, October 2015; * Shipments are for semiconductor applications only and do not include solar applications

Silicon wafers are the fundamental building material for semiconductors, which in turn, are vital components of virtually all electronics goods, including computers, telecommunications products, and consumer electronics. The highly engineered thin round disks are produced in various diameters (from one inch to 12 inches) and serve as the substrate material on which most semiconductor devices or “chips” are fabricated.

All data cited in this release is inclusive of polished silicon wafers, including virgin test wafers and epitaxial silicon wafers shipped by the wafer manufacturers to the end-users. Data do not include non-polished or reclaimed wafers.

For more information on the SEMI Worldwide Silicon Wafer Shipment Statistics, visit www.semi.org/en/MarketInfo/SiliconShipmentStatistics.

By Jeff Dorsch, Contributing Editor

The short answer to that headline’s question is “no.” Longer term, in going beyond the 5-nanometer process node, silicon may finally reach the end of its usefulness to the semiconductor industry.

SEMI estimates the worldwide semiconductor materials market grew 3 percent in 2014 to $44.3 billion, compared with 2013’s $43.05 billion. The 2014 total was composed of $24.0 billion in wafer fabrication materials and $20.4 billion in packaging materials. Taiwan last year remained the world’s largest consumer of semiconductor materials, accounting for $9.58 billion in sales, an 8 percent increase from the prior year’s $8.91 billion.

SEMI’s Silicon Manufacturers Group reports silicon wafer area shipments increased 11 percent in 2014 to 10,098 million square inches, as against 9,067 MSI in 2013. Revenues, however, grew only 1 percent year-to-year, to $7.6 billion from $7.5 billion, still far below the 2007 peak of $12.1 billion.

Researchers around the world are constantly investigating materials that could be the successor to silicon. Molybdenum disulfide shows promise. Graphene, the “wonder material” with many exciting attributes, is difficult to employ as a semiconductor material due to its lack of a bandgap, although bandgaps can be found in bilayer graphene or graphene nanoribbons.

Closer at hand are silicon carbide and the III-V materials, such as gallium arsenide and gallium nitride.

Scott Balaguer, Edwards’ president of the U.S. & Europe Semiconductor Business Unit, observes, “Chemistries, gas flows and materials are constantly changing across numerous applications and design nodes. We see these innovations in both silicon and compound semiconductor technologies. A great example is the new prototype SiC line at SUNY Polytechnic Institute that General Electric is driving in Albany, New York.

“The rate and pace of 10nm development is picking up and 14nm HVM fabs continue to improve and efficiencies and achieve higher yields.

“Clearly the rate of EUV adoption has gained momentum as source performance and throughput has improved. It is not a question of if, it is just when,” Balaguer says.

Thomas Piliszczuk, senior vice president of marketing, business development, and global sales for Soitec, says radio-frequency silicon-on-insulator technology is becoming mainstream and has seen “huge growth over the past several years.” He adds, “SOI is today in 99 percent of smartphones.”

On the fully-depleted silicon-on-insulator front, the industry today is at a tipping point with strong industry support and a growing ecosystem. The low-power, significant performance, and cost benefit attributes of FD-SOI are making the technology attractive for mobile, wearable devices, and the Internet of Things, as well as automotive and networking applications, according to Piliszczuk. “FD-SOI is a cheaper solution, overall,” he says. The executive looks for it to soon become “a very high-volume market.”

“The ecosystem now sees SOI not as a niche any more, but as a robust technology for many consumer applications,” Piliszczuk concludes. Shin-Etsu Handotai and SunEdison Semiconductor have joined Soitec as SOI wafer suppliers.

EUV and immersion lithography are expected to usher in the 7nm and 5nm process nodes. What happens past N7 and N5?

An Steegen, senior vice president of process technology for imec, looks ahead to nanowires and high-mobility channels in semiconductors of the future. Those nanowires will be made of silicon or silicon germanium, she says, with germanium in the channel.

That technology will have its drawbacks, she acknowledges. “One nanowire will never beat the performance of one FinFET,” Steegen says.

IBM Research has touted the future use of carbon nanotubes in transistors.

So, don’t write off silicon for now. The old reliable material may have years of usefulness ahead, whether in compound semiconductors or on its own.

The exceptional properties of tiny molecular cylinders known as carbon nanotubes have tantalized researchers for years because of the possibility they could serve as a successors to silicon in laying the logic for smaller, faster and cheaper electronic devices.

First of all they are tiny — on the atomic scale and perhaps near the physical limit of how small you can shrink a single electronic switch. Like silicon, they can be semiconducting in nature, a fact that is essential for circuit boards, and they can undergo fast and highly controllable electrical switching.

But a big barrier to building useful electronics with carbon nanotubes has always been the fact that when they’re arrayed into films, a certain portion of them will act more like metals than semiconductors — an unforgiving flaw that fouls the film, shorts the circuit and throws a wrench into the gears of any potential electronic device.

In fact, according to University of Illinois-Urbana Champaign professor John Rogers, the purity needs to exceed 99.999 percent — meaning even one bad tube in 100,000 is enough to kill an electronic device. “If you have lower purity than that,” he said, “that class of materials will not work for semiconducting circuits.”

Now Rogers and a team of researchers have shown how to strip out the metallic carbon nanotubes from arrays using a relatively simple, scalable procedure that does not require expensive equipment. Their work is described this week in the Journal of Applied Physics, from AIP Publishing.

The Road to Purification

Though it has been a persistent problem for the last 10-15 years, the challenge of making uniform, aligned arrays of carbon nanotubes packed with good densities on thin films has largely been solved by several different groups of scientists in recent years, Rogers said.

That just left the second problem, which was to find a way to purify the material to make sure that none of the tubes were metallic in character — a thorny problem that had remained unsolved. There were some methods of purification that were easy to do but fell far short of the level of purification necessary to make useful electronic components. Very recent approaches offer the right level of purification but rely on expensive equipment, putting the process out of reach of most researchers.

As the team reports this week, they were able to deposit a thin coating of organic material directly on top of a sheet of arrayed nanotubes in contact with a sheet of metal. They then applied current across the sheet, which allowed the current to flow through the nanotubes that were metal conductors — but not the bulk of the tubes, which were semiconducting.

The current heated up the metal nanotubes a tiny amount — just enough to create a “thermal capillary flow” that opened up a trench in the organic topcoat above them. Unprotected, the metallic tubes could then be etched away using a standard benchtop instrument, and then the organic topcoat could be washed away. This left an electronic wafer coated with semiconducting nanotubes free of metallic contaminants, Rogers said. They tested it by building arrays of transistors, he said.

“You end up with a device that can switch on and off as expected, based on purely semiconducting character,” Rogers said.

By combining the powers of two single-atom-thick carbon structures, researchers at the George Washington University’s Micro-propulsion and Nanotechnology Laboratory have created a new ultracapacitor that is both high performance and low cost.

The device, described in the Journal of Applied Physics, capitalizes on the synergy brought by mixing graphene flakes with single-walled carbon nanotubes, two carbon nanostructures with complementary properties.

Ultracapacitors are souped-up energy storage devices that hold high amounts of energy and can also quickly release that energy in a surge of power. By combining the high energy-density properties of batteries with the high power-density properties of conventional capacitors, ultracapacitors can boost the performance of electric vehicles, handheld electronics, audio systems and more.

Single-walled carbon nanotubes and graphene both have unique and excellent electronic, thermal, and mechanical properties that make them attractive materials for designing new ultracapacitors, said Jian Li, first author on the paper. Many groups had explored the use of the two materials separately, but few had looked at combining them, he said.

“In our lab we developed an approach by which we can obtain both single-walled carbon nanotubes and graphene, so we came up with the idea to take advantage of the two promising carbon nanomaterials together,” added Michael Keidar, a professor in the Department of Mechanical and Aerospace Engineering in the School of Engineering and Applied Science at GW, and director of the Micro-propulsion and Nanotechnology Laboratory.

A scanning electron microscope image shows the ultracapacitor’s composite film containing graphene flakes and single-walled carbon nanotubes. Credit: Journal of Applied Physics

A scanning electron microscope image shows the ultracapacitor’s composite film containing graphene flakes and single-walled carbon nanotubes.
Credit: Journal of Applied Physics

The researchers synthesized the graphene flakes and nanotubes by vaporizing a hollow graphite rod filled with metallic catalyst powder with an electric arc. They then mixed the two nanostructures together to form an ink that they rolled onto paper, a common separator for current commercial capacitors.

The combination device’s specific capacitance, a measurement of the performance of a capacitor per unit of weight, was three times higher than the specific capacitance of a device made from carbon nanotubes alone.

The advantage of the hybrid structure, Li explained, is that the graphene flakes provide high surface area and good in-plane conductivity, while the carbon nanotubes connect all of the structures to form a uniform network.

While other types of ultracapacitors have also achieved the high specific capacitance of the graphene/nanotube hybrid, the researchers say, the main advantage of the combination approach is its low costs, since the team has developed a simple way to manufacture large amounts of the desirable mix of carbon nanostructures.

The hybrid ultracapacitor is also small and light, an advantage as electronic devices get ever smaller.