Category Archives: MEMS

Sankalp Semiconductor, a chip design service company, announced that it has signed an agreement with STMicroelectronics to serve as an FD-SOI services and IP partner.

“The FD-SOI ecosystem is growing quickly with multiple and diverse partners throughout the Supply Chain because, at 28nm, FD-SOI technology is proven as the most cost-effective and energy-efficient option. FD-SOI provides a wide range of operating voltages, including from 0.6V to 1.1V, and a unique body-bias capability,” said Giorgio Cesana, Director of Technology Marketing, STMicroelectronics. “Having worked with Sankalp Semiconductor on previous designs, we recognize and appreciate their skill and value to the FD-SOI supply-chain.”

“Sankalp has been involved in the development of many FD-SOI analog IP and high-speed PHYs for ST, have mastered the technology’s appropriate use and the integration of these IP in SoC, and has seen first-hand its’ faster, simpler, and cooler benefits,” said Atul Arora, IP Business Unit Head, Sankalp Semiconductor. “The addition of FD-SOI to our toolkit enables Sankalp to best serve our customers in the IoT / Wearable, Consumer, Multimedia & Automotive markets with complete IP and SoC solutions.”

The agreement with ST gives Sankalp Semiconductor access to a broad range of IP in FD-SOI at the 28nm node. Sankalp has also developed a porting engine and a methodology to port designs to other nodes in a shorter turn-around time.

A new, low pH, BTA free, noble-bond chemistry produced equivalent yield at substantially lower costs.

BY CHRISTOPHER ERIC BRANNON, Texas Instruments, Dallas, TX

The 2010 economic downturn affected many industries, semiconductor manufacturing notwithstanding. Many fabrication facilities had to layoff employees and curtail spending, all the while managing lower wafer output. This effect caused many semiconductor companies to rethink how they spend on resources. Everything was considered, from the cost of the wafers to the cost of the tool consumables and chemistries.

Texas Instruments (TI) copper chemical-mechanical planarization (Cu CMP) was no different. All spending had to be reduced and copper hillock defect had to
be eliminated. The CMP Team proposed developing a process based on the new third generation clean chemistry on the market for a number of economic and logistical reasons. The first rationale for this strategy was cost and second was time – most of the clean chemis- tries on the market were considerably cheaper than the current process of record (POR). CMP had also seen many defects due to via-to-via shorts caused by Cu hillocking (localized Cu protrusion into the above interlayer dielectric; see FIGURE 1).

FIGURE 1. TEM of copper hillocks [1].

FIGURE 1. TEM of copper hillocks [1].

A successful Cu cleaning CMP process

There were two key reasons that TI succeeded in developing a Cu cleaning process: detailed engineering work and strong vendor support. Process development went through four generations of refinement before it was ready for high volume manufacturing. The first version focused on new clean chemistry improvements such as third generation low pH, high acid clean chemistry and an array of design of experiments (DOE) continuous improvement through optimization of the process controls and equipment modification followed in the second. The third generation attempted to adapt an existing Mirra-Desica process using a previous qualified process. A final successful attempt was made during the fourth cycle to develop a lower cost, higher throughput multi-copper platen cleaning process using a commercial chemistry from Air Products, COPPEREADY®CP72B. This paper will discuss the work that went into building TI’s successful Cu cleaning CMP process.

TI Cu CMP

Neutral pH clean chemistries using Benzotriazole (BTA) were the first generation application on most Cu CMP dual damascene back end of the line process at TI. This was dependent on using dry-in wet-out Cu CMP AMAT tools with spray acid Vertec hoods for cleaning and drying. It was also very high in cost and low in consumable life compared to most conventional CMP clean process (e.g. Tungsten, STI, Oxide). The TI POR was no different, a first generation Cu clean using three different chemistries, BTA, Electra Clean and ESC774TM. These chemistries were very expensive to use and were not very efficient at cleaning or passivating the polished copper surface. They were able to passivate the copper surface but were prone to leave many types of incompatible carbon residue defects on the wafers. Cu hillocking was very prevalent with this type of cleaning solution and via-to-via shorts in the back end of the line (BEOL) were the top defect pareto for TI.

Clean chemistry identification

To reduce the time to develop a new Cu CMP clean process, most of the development cycle focused on Cu cleans leveraging a Mirra-Desica DIDO Cu polishing process using existing pads, conditioning pucks, and heads. Early on, it was decided that to achieve maximum throughput, the wafers would need to be processed through the tool’s onboard scrubber and dry station as quickly as possible. With time running out, the Cu CMP team had contacted the major players in Cu clean chemistry to obtain their specific information and prepare a white paper screening to determine the correct path. The four candidates were evaluated on chemistry type, makeup, pH, passivation (BTA), cost, and compatibility to our current Cu and barrier slurry. Two of the chemistries fit the bill for the criteria and were selected for further testing. Chemistry 1 was a novel approach for Cu CMP and was from our current clean chemistry vendor, Chemistry 2 was similar to the current TI process of record.

The initial criteria used to judge the chemistries were blanket test wafer performance (Cu, Teos, Ta, and Nitride): etch rate, passivation, cleaning tunability via recipe parameter windowing, and defectivity. Experimental designs were run on the basic process controls with these chemistry’s with respect to the polish process: carrier speed, table speed, down-force, carrier position, carrier oscillation, and chemical flow. Both cleans performed well on the blanket experiments and were advanced to short loop, patterned wafer tests. These patterned wafer tests were used to study product behavior in the polisher and brush cleaner. A significant amount of time was spent adjusting recipe parameters to eliminate defects. The team contacted both vendors to do lifetime experiments with consumables at their facilities. The data that was collected revealed many issues with each candidate, one more so than the other (FIGURE 2).

FIGURE 2. Charts of Cu CMP defects showing effects of new clean chemistry.

FIGURE 2. Charts of Cu CMP defects showing effects of new clean chemistry.

Chemistry A was a second generation Cu clean that had high pH but had chemical additives that would aid in cleaning, still a very basic approach to wafer cleaning. The overall defectivity was sufficient on the product test wafers but would degrade after a short time window after polish. It also had to be paired with another chemistry to achieve the same Cu passivation as the POR. This chemistry was disqualified due to this reason.

Chemistry B is a third generation Cu clean that had low pH (about ~2.1) and it is BTA-free, unlike any other Cu cleans on the market at that time. This chemistry is an organic acid blend, which helps ionize Cu2O and CuO to form water and soluble Cu complex, used for passivation. This forms a strong bond with the Cu to make the surface nobel. The low pH helps to dissolve the surface defects resulting in a step function decrease in defectivity compared to baseline (see Figure 2). The chemistry was also scalable, depending on concentration making cost of ownership low. This chemistry was selected for qualification at TI Cu CMP.

Vendor support

TI’s internal polishing engineering staff was augmented with exceptional support from several consumable vendors during development. Together TI engineers developed proprietary and patent-pending technologies to enhance the Mirra Desica cleaner performance on Cu BEOL CMP. TI also benefited from strong relationships with its contact clean brush suppliers. Rippy was instrumental in brush evaluations and consul- tation on process developments. To improve the tool’s performance, DOW was pivotal in adding additional functionality to the process through end of life evaluations. Perhaps most important of all relationships that developed was with Air Products, who provided an invaluable education into Cu cleaning process development.

Solving defect issues

During process development, TI engineers encountered several defect related issues. Some issues like photo-induced corrosion were resolved quickly after some technical research. There were two others that took more troubleshooting: carbon residue defects and Cu hillock formation.

The presence of gross surface defects, like carbon residue is an obvious yield killer. The Cu CMP Engineers come to the conclusion through EDX (Energy-dispersive X-ray spectroscopy) and much lab analysis that the current Cu slurry still had traces of BTA in it and were causing this residue defect to form on the wafers after polish. Many DOE later determined that extending the clean chemistry buff polish would eliminate this defect.

With residue defects effectively eliminated, the next major technical challenge was Cu hillock formation. TI had been experiencing higher defectivity due to back end of the line via to via shorts on the previous Cu CMP clean chemistry process. It was understood that the formation of Cu hillocks were the cause for this signature. To solve this problem, a completely different wafer cleaning chemistry was needed to passivate the copper surface. TI Cu CMP Engineers looked for one that did not use BTA or other high pH chemistries, but, would coat the wafer surface and not allow native oxides to grow on the Cu. The new chemistry (CoppeReady®CP72B) proved to form a nobel bond with the Cu (CuO2) and eliminated hillock growth formation, thereby reducing via-to-via shorts (see FIGURE 3).

FIGURE 3. Metal 1 via etch contact pitting chart (dark vias induced by copper hillock).

FIGURE 3. Metal 1 via etch contact pitting chart (dark vias induced by copper hillock).

Further process development

One of the last stages of development on the new process was a project to develop a faster through-put process. Although this work was successful, it highlights some of the challenges in pursuing this type of strategy. The motivation for this work was to dramatically boost the throughput and to further cut process expense. The POR process was limited by the cleaner and was much slower causing higher cost and higher wafer-per-hour rates. To maximize throughput, the new process would have two components: speed up the on board cleaner, brush box 1&2 throughput, as well decrease the platen 2&3 process times but include a clean chemistry buff. Because of the high down forces employed to achieve a flat removal profile, the Cu polishing component of this work, platen 1, was surprisingly fast but was the intended bottle neck. These changes allowed for a 10 percent increase in overall wafer through put compared to the baseline process. This had an alternate effect on the Cu polish process. TI’s current Cu slurry is thermally driven, with making platen 1 the bottle neck it kept that platen at one constant temperature throughout the lot, causing the overall end point times (EPD) to be reduced and streamlined. This further increased the tools throughput by 2 percent and reduced wafer to wafer EPD variation down to 2 to 3 seconds; previous was 10 to 12 sec between wafers (see FIGURE 4).

FIGURE 4. Cu CMP end point charts, variation reduction, clean chemistry and throughput enhancements.

FIGURE 4. Cu CMP end point charts, variation reduction, clean chemistry and throughput enhancements.

Benchmarking performance

For initial qualification and benchmarking, TI installed and setup the best known method (BKM) Cu polishing process on an Applied Materials Mirra-Desica. To
bring the new clean process into production, Cu Polish engineers needed to demonstrate equivalent or better yield between the two competing process. The new clean chemistry needed to be tested for EM (electro migration), which is a stress test of Cu interconnects between two metal lines. This test had to be outsourced to a third party company that specializes in oven-baking stress tests (FIGURE 5). After extensive electrical and yield testing, the new clean process was fully released. Sample yield comparisons consistently demonstrated that the performance is equivalent to slightly better and the new process has higher through-put (~12 percent). The chemical costs (dilute 60 to 1 CP72B®) are 68 percent less per wafer pass than the competing process. The pad/ conditioner life had increased by 13 percent from the previous process due to thermal driven Cu slurry through put modification (FIGURES 6 AND 7).

FIGURE 5. Electromigration (EM) stress test, new clean vs baseline.

FIGURE 5. Electromigration (EM) stress test, new clean vs baseline.

FIGURE 6. Sample availability with the new clean chemistry improvements.

FIGURE 6. Sample availability with the new clean chemistry improvements.

FIGURE 7. Clean chemistry cost over time in Cu CMP in terms of lots processed.

FIGURE 7. Clean chemistry cost over time in Cu CMP in terms of lots processed.

Conclusion

TI engineers developed a Cu CMP cleaning process using new third generation low pH Cu chemistry. Despite the tool’s many limitations, the engineering staff successfully delivered an integrated process capable of producing equivalent yield at substantially lower costs over the best alternative method. There were undoubtedly challenges along the way, only a fraction of which have been described in this paper. By leveraging an existing deep reservoir of engineering, maintenance, and operational talent, an existing and efficient supply chain, and the outstanding support of numerous vendors, TI Polish module was able to realize its goal of making efficient use of its assets to achieve a competitive advantage.

References

1. Tsung-Kuei Kanga, and Wei-Yang Choub Author. ‘Avoiding Cu Hillocks during the Plasma Process’

Journal of The Electrochemical Society, 151

CHRISTOPHER ERIC BRANNON is a TI Cu CMP Manufacturing Engineering, Texas Instruments, Dallas, TX.

SEMI today announced the update of its World Fab Forecast report for 2015 and 2016. The report projects that semiconductor fab equipment spending (new, used, for Front End facilities) is expected to increase 11 percent (US$38.7 billion) in 2015 and another 5 percent ($40.7 billion) in 2016. Since February 2015, SEMI has made 282 updates to its detailed World Fab Forecast report, which tracks fab spending for construction and equipment, as well as capacity changes, and technology nodes transitions and product type changes by fab.   

Capital expenditure (capex without fabless and backend) by device manufacturers is forecast to increase almost 6 percent in 2015 and over 2 percent in 2016. Fab equipment spending is forecast to depart from the typical historic trend over the past 15 years of two years of spending growth followed by one of decline.  For the first time, equipment spending could grow every year for three years in a row: 2014, 2015, and 2016.

The SEMI World Fab Forecast Report, a “bottoms up” company-by-company and fab-by-fab approach, lists over 48 facilities making DRAM products and 32 facilities making NAND products. The report also monitors 36 construction projects with investments totaling over $5.6 billion in 2015 and 20 construction projects with investments of over $7.5 billion in 2016.  

According to the SEMI report, fab equipment spending in 2015 will be driven by Memory and Foundry ─ with Taiwan and Korea projected to become the largest markets for fab equipment at $10.6 billion and $9.3 billion, respectively. The market in the Americas is forecast to reach $6.1 billion, with Japan and China following at $4.5 and $4.4 billion, respectively. Europe/Mideast is predicted to invest $2.6 billion. The fab equipment market in South East Asia is expected to total $1.2 billion in 2015.

Learn more about the SEMI World Fab Forecast and plan to attend the SEMI/Gartner Market Symposium at SEMICON West 2015 on Monday, July 13 for an update on the semiconductor supply chain market outlook. In addition to presentations from Gartner analysts, Christian Dieseldorff of SEMI will present on “Trends and Outlook for Fabs and Fab Capacity” and Lara Chamness will present on “Semiconductor Wafer Fab Materials Market and Year-to-Date Front-End Equipment Trends.”   

Fab Equipment Spending
(for Front-End Facilities, includes new, used, in-house)

 

2014

(US$B)

2015

(US$B)

Year-over-Year
Americas

7.8

6.1

-22%
China

4.1

4.4

10%
Europe and Mideast

2.2

2.6

18%
Japan

3.8

4.5

17%
Korea

7.4

9.3

27%
SE Asia

1.1

1.2

2%
Taiwan

8.5

10.6

25%
Total

34.9

38.7

11%
Source: SEMI World Fab Forecast Reports (May 2015)Totals may not add due to rounding

CEA-Leti today announced that it has demonstrated a path to fabricating high-density micro-LED arrays for the next generation of wearable and nomadic systems in a process that is scalable to the IC manufacturing process.

The high-brightness, enhanced-vision systems such as head-up and head-mounted displays can improve safety and performance in fields such as aeronautics and automotive, where the displays allow pilots and drivers to receive key navigation data and information in their line of sight. For consumers, smart glasses or nomadic projection devices with augmented reality provide directions, safety updates, advertisements and other information across the viewing field. LED microdisplays are ideally suited for such wearable systems because of their low footprint, low power consumption, high-contrast ratio and ultra-high brightness.

Leti researchers have developed gallium-nitride (GaN) and indium gallium-nitride (InGaN) LED technology for producing high-brightness, emissive microdisplays for these uses, which are expected to grow dramatically in the next three to five years. For example, the global research firm MarketsandMarkets forecasts the market for head-up displays alone to grow from $1.37 billion in 2012 to $8.36 billion in 2020.

“Currently available microdisplays for both head-mounted and compact head-up applications suffer from fundamental technology limitations that prevent the design of very low-weight, compact and low-energy-use products,” said Ludovic Poupinet, head of Leti’s Optics and Photonics Department. “Leti’s technology breakthrough is the first demonstration of a high-brightness, high-density micro-LED array that overcomes these limitations and is scalable to a standard microelectronic large-scale process. This technology provides a low-cost, leading-edge solution to companies that want to target the fast-growth markets for wearable vision systems.”

Announced during Display Week 2015 in San Jose, Calif., Leti’s technology innovation is based on micro-LED arrays that are hybridized on a silicon backplane. Key innovations include epitaxial growth of LED layers on sapphire or other substrates, micro-structuration of LED arrays (10μm pitches or smaller), and 3D heterogeneous integration of such LED arrays on CMOS active-matrices.

These innovations make it possible to produce a brightness of 1 million cd/m² for monochrome devices and 100 kcd/m² for full-color devices with a device size below one inch and 2.5 million pixels. This is a 100- to 1,000-times improvement compared to existing self-emissive microdisplays, with very good power efficiency. The technology also will allow fabrication of very compact products that significantly reduce system-integration constraints.

The high-density micro-LED array process was developed in collaboration with III-V Lab.

CEA-Leti plays a role in the development of the Internet of Things as a provider of key underlying technologies that help its partners take advantage of the opportunities the IoT will offer. These technologies include new sensors, energy-harvesting systems, ultra-low-power communication technologies and ultra-low-power digital processors.

Building on this foundation, the 17th annual LetiDays Grenoble on June 24-25 will expand the conversation with presentations about Internet of Things-augmented mobility, which is revolutionizing the way we interact with appliances, infrastructure and countless common objects that are part of our daily lives.

Another conference theme that includes the IoT and broader markets is Leti’s breakthroughs in silicon technologies, sensors, telecommunications, power management in wearable systems, health applications, transportation and cities of the future. We will focus on how to bring increases in performance, efficiency and security to these fields and markets.

The two-day event will feature more than 40 conferences, many networking opportunities, plus showroom and exhibition halls.

Speakers include:

  • Leti CEO Marie-Noëlle Semeria
  • Suresh Venkatesan, SVP technology development, GLOBALFOUNDRIES
  • Jean-Pierre Cojan, Director, Strategy and Transformation, Safran and
  • Christophe Fourtet, Chief Science Officer and co-founder, SIGFOX. 

In addition, Prof. Alim Louis Benabid will give a keynote address on June 24 at 6 pm. Benabid is a neurosurgeon and board chairman of the Edmond J. Safra Biomedical Research Center Clinatec on the Minatec campus in Grenoble. He has won multiple awards for his pioneering work in the treatment for Parkinson’s disease, including the Albert-Lasker Prize in 2014 and the Breakthrough Prize in Life Sciences in 2015.

Leti also will host technology workshops during the week of June 22:

IC Insights will release its Update to the 2015 IC Market Drivers report in June. The Update includes revisions to IC market conditions and forecasts for the 2015 2018 automotive, smartphone, personal computer and tablet markets, as well as an update to the market for the Internet of Things. This bulletin reviews IC Insights’ 2015 unit shipment forecast for total personal computing unit shipments.

Five years ago, touchscreen tablets began pouring into the personal computing marketplace, stealing growth from standard personal computers and signaling the start of what has been widely described as the “post-PC” era. Led by Apple’s iPad systems, tablet shipments overtook notebook PCs in 2013, and it appeared as if they would surpass total personal computer units (counting both desktop and portable systems) by 2016. However, that scenario no longer seems possible after tablet growth lost significant momentum in 2014 and then nearly stalled out in the first half of 2015 due to the rise in popularity of large-screen smartphones and the lack of interest in new tablets that do not add enough features or capabilities to convince existing users to buy replacements. Consequently, IC Insights has downgraded its forecast for the overall personal computing market, including much lower growth in tablets and continued weakness in standard PCs (Figure 1).

The updated forecast shows total personal computing unit shipments (desktop PCs, notebook PCs, tablets, and Internet/cloud-computing “thin-client” systems) dropping 1 percent in 2015 to 545 million. In the original forecast of the 2015 IC Market Drivers report (MD15), total personal computing system shipments were projected to rise 8 percent in 2015 to 609 million units, followed by a 10 percent increase in 2016 to 670 million. The revised outlook cuts the compound annual growth rate (CAGR) of personal computing unit shipments to 2.1 percent between 2013 and 2018. Total personal computing system shipments are now projected to reach 578 million in 2018.

Worldwide shipments of keyboard-equipped standard PCs (desktops and notebooks) peaked in 2012 at 345 million, but they are expected to decline by a CAGR of -0.5 percent in the 2013-2018 timeperiod. In the updated outlook, tablets are projected to account for 45 percent of total systems sold in 2018 (259 million units) versus the MD15’s original forecast of 57 percent (423 million) that year. Further into the future, tablets are now expected to account for about half of personal computing system shipments with the remaining units being divided between standard PCs and Internet/cloud-centric platforms.

IC Insights June Report

Figure 1

 

Additional details on the IC market for medical and wearable electronic is included in the 2015 edition of IC Insights’ IC Market Drivers—A Study of Emerging and Major End-Use Applications Fueling Demand for Integrated Circuits.  This report examines the largest, existing system opportunities for ICs and evaluates the potential for new applications that are expected to help fuel the market for ICs.

Xcerra Corporation today announced that Nordic Semiconductor, a company that specializes in ultra-low power (ULP) 2.4GHz transceivers, notably for the Bluetooth Smart and wearables segments, has selected the Diamondx from Xcerra’s semiconductor tester group, LTX-Credence, for high volume production test of their Internet of Things (IoT) products. Nordic will use the Diamondx in combination with NighthawkCT, an industry leading instrument for low cost RF test of connectivity devices.

“We are delighted to once again see LTX-Credence come out of this type of benchmarking exercise with the best overall fit for our testing needs,” notes Ole-Fredrik Morken, Supply Chain Director at Nordic Semiconductor, and adds, “While our strategy in this arena is mainly driven by a requirement for highest possible throughput per test cell, we also value a long-term relationship with LTX-Credence and their consistent focus on providing best-in-class test solutions for our product segment. We are currently running high volume production on Diamondx systems at multiple OSATs in Asia.”

Frank Berntsen, Chief Scientist at Nordic, commented, “After analyzing the data we determined that the Diamondx and NighthawkCT configuration features a superior combination of instrument performance, infrastructure speed and allows for a significant increase in parallel test. This is critically important for us as the application of Bluetooth Smart and emerging technologies for all types of IoT and wearables will further fuel Nordic’s growth, driving the need for high volume, low cost test solutions.”

Steve Wigley, vice president of the semiconductor tester group at Xcerra Corporation commented, “The growth in IoT applications is expected to be a major contributor to semiconductor unit volumes over the next several years. The combination of Diamondx and NighthawkCT was specifically designed to offer a new level of test capability for these types of applications. This new level of capability provides RF connectivity performance testing, as well as, a significantly reduced cost of testing RF enabled devices used in IoT applications. This is one of the drivers of the large installed base of Diamondx systems at the major OSATs. The selection of Diamondx and NighthawkCT for high volume production test by a key IoT player such as Nordic validates that our test solutions are well aligned to the needs of these fast growing applications.”

By Paula Doe, SEMI

Ever growing volumes of data to be stored and accessed, and advancing process technologies for sophisticated control of deposition and etch in complex stacks of new materials, are creating a window of opportunity for an emerging variety of next-generation non-volatile memory technologies.  While flash memory goes vertical for  higher densities, resistive RAM and spin-transfer magnetic RAM  technologies are moving towards commercial manufacture for  initial applications in niches that demand a different mix of speed,  power and endurance than  flash or SRAM. This article delves into some of the topics that will be addressed at SEMICON West 2015.

Micron: Memory Needs to go Vertical

“Memory is going through a transformation, making it an exciting time to be in the sector, with both emerging opportunities and new challenges,” notes Naga Chandrasekaran, Micron Technology VP of process R&D, who will keynote the next-generation memory program at SEMICON West 2015.  As new applications in the connected world drive demand for increased storage, bandwidth, and smart memory, and as conventional planar memory scaling faces more challenges, memory suppliers across the industry face a transformation, requiring new emerging memory types and a transition from planar to vertical technology.

“Memory needs to go vertical to meet growing demands placed on performance, and that means a new set of process and equipment requirements,” says Chandrasekaran.  Scaling the vertical 3DNAND structures is no longer limited by the lithography, but instead is driven by the capability of the etch, film and characterization processes.  “Metrology and structure/defect characterization is a holdup for the entire sector, which is slowing down the cycle time for development,” he notes. “In addition, there are challenges in materials, structural scaling, equipment technology, and manufacturability on the new roadmap that need to be resolved.”

Everspin Targets ST-RAM on GLOBALFOUNDRIES’ 40nm 300mm Process in a Year

Everspin Technologies’ recently introduced 64Mb spin transfer torque MRAM makes a big jump in density over the company’s earlier 16Mb device, as switching the magnetization by a current of electrons of aligned spin allows much better selectivity than applying a magnetic field.  Manufacturing these spin-transfer devices has traditionally been a challenge, but the company claims it sees a clear roadmap to continue to increase the density. “We’re squeezing a 64Mb device on 90nm silicon out of the quarter-micron process equipment in our fab,” says VP of manufacturing Sanjeev Aggarwal, who will give an update on the technology at SEMICON West.  The company is in the process of transferring the technology to a 40nm process on 300mm wafers at partner GLOBALFOUNDRIES in the next year, to significantly reduce the cell size and spacing.

Aggarwal notes that the layers in the magnetic stack of the spin-transfer torque device (ST RAM) are similar in thickness to those of the earlier magnetic-field switched MRAM devices, which have already shipped some  50 million units. In the 28nm version of the ST-RAM, targeted for a couple of years out, the company plans to switch from an in-plane to a perpendicular structure, which will significantly improve efficiency to cut power consumption by an order of magnitude, though the material stack and processing will remain very similar.

Current deposition tools can provide the layer uniformity required for the many ultrathin layers of these magnetic stacks, and etching technology being developed with a vendor for cleanly removing these non-volatile magnetic material looks promising for 40nm, says Aggarwal. Key is the company’s IP for depositing the tunnel barrier MgO and for stopping the etch uniformly on the tunnel barrier when etching the magnetic stack. “These deposition and etch technologies should extend to 1Gb without much change, though at 16Gb we may need something new,” he adds. “In the next several years we will need help from vendors on better ways to clean up the etch residue, such as by ion milling after RIE, or encapsulating the stack to protect it before the next round of etching.”

Demand for the 64Mb ST-RAM is coming from buffer storage applications, such as high-end enterprise-class solid state drives, where an array of the fast-writing, non-volatile chips holds the data until it can be more permanently filed and stored, and where the high volumes of data require better endurance than flash,  reports Terry Hulett,  Evergreen VP Systems Engineering and GM Storage Solutions.  “As our products increase in density, we expect to serve the same function for bigger storage systems, like a whole rack of solid state drives,” he projects. The company also targets applications for potential power savings for the instant-on persistent memory, such as powering off the display buffer between every refresh cycles for mobile devices, or shutting down the server between operations.

Both Sanjeev Aggarwal (Everspin) and Naga Chandrasekaran (Micron Technology) will update SEMICON West attendees on the state of these emerging memory technologies in a TechXPOT.   In addition, Wei D. Lu (Crossbar), Robert Patti (Tezzaron), and Jim Handy (Objective Analysis) will provide analysis and updates at the July 14 event in San Francisco:

Crossbar Aims for Embedded ReRAM IP Blocks from Foundry by End of Year

ReRAM suppliers, meanwhile, argue that their technology potentially offers better prospects for scaling and lower costs than either flash or spin-based MRAM, although it is still a ways from a commercial volume process.   Crossbar Co-founder and chief scientist Wei Lu, who will also speak at SEMICON West, says the company plans to deliver its ReRAM technology to strategic partners as an IP block for embedded non-volatile memory on logic chips from a leading-edge manufacturing foundry by the end of the year.  The company’s approach stores data by changing the resistance by forming a conductive metallic bridge through a resistive layer of amorphous silicon sandwiched between two electrode layers.

Lu says the devices are being made with two-mask steps on top of the CMOS transistors in a leading foundry.  Key to improving performance to commercial levels and achieving very dense crossbar arrays, he notes, is the addition of a high speed selector device on top of the memory layer.  This layer blocks unwanted sneak currents at low voltages and turns on at the threshold level to enable formation of the conduction bridge. “It’s like a volatile RAM stacked on top of the ReRAM, with nanosecond recovery time,” he explains. “This brings the on/off selectivity up to 108.”

Initial target market is chip makers who want to embed nonvolatile memory directly in the logic fab, for low-power applications like the IoT, with faster speed and higher endurance than flash.  But ultimately the company targets the bigger market of stand-alone enterprise data storage with lower read and write latencies.  “We expect to offer Gigabit-level density at faster speed than NAND flash by around 2017,” claims Lu.  He figures ReRAM and STT RAM will both find their place in the more diverse memory market of the future, with SST RAM offering better endurance, and ReRAM offering higher density and lower cost.

Tezzaron Reports High ReRAM Yields from Repair and Remapping through Multilayer Stack

Tezzaron Semiconductor takes a different approach to ReRAM, storing data by moving oxygen vacancies instead of metal ions across the thin layers to change resistance.  CTO Robert Patti, another SEMICON West speaker, credits the Tezzaron fab’s ALD technology for the tight control of layer uniformity required to build its 16-tiers of ReRAM cells on top of a CMOS transistor tier from another foundry.  Controlling the chemistry of the layering and the reaction is a challenge, but the tiers allow dynamic repair and remapping of defective cells, which Patti claims can enable yields of up to 98%.  “The possibility to repair across the vertical structure makes defect density less of an issue, and lets us deal with materials and processes that are less mature,” he notes.

Patti says his company’s aerospace/military customers, who need a non-volatile option with better endurance than flash memory, will likely move to ReRAM within a couple of years.  Server makers are also starting to look at the potential for adding a new intermediate level of memory, between the solid state disk and the DRAM, which could potentially significantly improve server performance in analyzing big data by holding big chunks of data for faster access at lower power. It might also reduce system-level costs, although it will require changes in operating system architecture to use it effectively, and sophisticated programming algorithms to manage the memory to limit wear.  Demands on the intermediate storage memory should be limited enough that the ReRAM target endurance of 109 cycles should be sufficient, though it remains lower than DRAM’s 1015.  If ReRAM endurance reaches 1012 cycles, the nonvolatile, instant-on memory could become a viable replacement for mobile memory, Patti suggests.

“Vertical NAND is appealing because it’s more familiar, which has probably delayed interest in ReRAM.  But ReRAM has a smaller cell size so may ultimately be easier to scale and more cost effective,” argues Patti.

Costs Remain the Challenge

“The only thing that ultimately matters in memory is cost,” argues Objective Analysis analyst Jim Handy, another speaker, pointing out that the target aerospace and enterprise storage applications remain small markets, and volumes are not high enough yet to build up deep understanding of the new materials used, so there will be bumps in the road to come.  But as costs come down as MRAM and ReRAM scale to higher densities, he expects them to gradually take over more mainstream applications, starting with the highest cost memories, so first SRAM (especially SRAM with battery backup), then NOR flash, DRAM and finally NAND flash — perhaps by ~2023.  “We have been predicting that 2017 is the earliest we’ll see significant penetration of 3D NAND into the planar NAND market,” he notes. “And now that some suppliers are saying it will be 2017, it makes me think it may be longer.”

On July 14, all of these industry leaders will present at SEMICON West at the emerging memory technologies TechXPOT (www.semiconwest.org/node/13781). Register now and save $100 off registration.

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today announced that its NILPhotonics Competence Center—established to assist customers in enabling new and enhanced products and applications in the field of photonics—has generated strong interest from customers and resulted in multiple system orders since its launch in December 2014. New system orders have included the company’s EVG700/7000 Series UV-NIL (UV nanoimprint lithography) systems with SmartNIL technology to support high-volume manufacturing applications, including displays, light emitting diodes (LEDs) and wafer-level optics.

EV Group wafer

Since its initial launch, the NILPhotonics Competence Center has also expanded the products and applications it is supporting. These include photonic and microfluidic devices for bio-medical applications that pave the way for faster and more accurate diagnosis of diseases, as well as plasmonic structures that simultaneously carry optical and electrical signals and can be scaled to the smallest dimensions to enable new chip designs as well as better-performing devices, such as waveguides and sensors.

“The prevailing perception has been that despite the potential benefits of NIL technology, the barrier to entry for integrating it into high-volume manufacturing (HVM) is high. That simply isn’t the case. EV Group has invested significant resources over many years in developing NIL technology as an HVM-capable solution for a number of applications,” stated Markus Wimplinger, corporate technology development and IP director at EV Group. “Today, we have the world’s largest installed base ofmore than 200 systems at customer facilities around the globe supporting volume-manufacturing of LEDs, MEMS, optics, photovoltaics and other devices. Our NILPhotonics Competence Center allows us to more easily bring all of our process and product capabilities and expertise to bear in helping our customers enable new photonic products and applications.”

EVG’s NILPhotonics Competence Center leverages EVG’s process and equipment know-how in NIL and other process areas such as wafer bonding to support emerging photonic applications and significantly shorten time to market through fast process implementation and optimization, as well as through customized equipment design. In addition, EVG has a global partner network to draw from to support its customers’ process integration and optimization efforts across the NIL infrastructure, including template manufacturing, resist materials and supporting equipment. As a result, EVG is able to provide consultation and support across all phases of the product lifecycle—from design for manufacturing and prototyping through process development, qualification runs, pilot manufacturing and process transfer.

“More than a decade ago, EV Group launched the NILCom Consortium with support from companies representing key aspects of the NIL supply chain in order to speed commercialization of NIL technology. Through the dedicated efforts of all of our members, we are pleased to announce that the NILCom Consortium has successfully completed its charter and will end formal operations. That said, we will continue to collaborate with companies across the NIL supply chain including our former members as needed to ensure that NIL technology continues to address future customer roadmap requirements,” added Wimplinger.

In 2014, the MEMS sector represented an $11.1B business for Si-based devices. According to Yole Développement (Yole) latest MEMS report “Status of the MEMS Industry”, the MEMS industry is preparing to exceed $20B by 2020.

“We have seen different market leaders in the past and the competition is still very open,” said Jean-Christophe Eloy, President & CEO, Yole. “But 2014 will be remembered for the emergence of what could be a future “MEMS Titan”: Robert Bosch (Bosch),” he added.

Under this new analysis entitled, “Status of the MEMS Industry” report Yole proposes a deep understanding of the MEMS markets trends and players dynamics. The More than Moore market research and strategy consulting company announces its 2014 MEMS manufacturers and foundries ranking and proposes an overview of the future game-changers including new devices, disruptive technologies, 300mm wafers, sensor fusion and new markets.

mems market forecast

Bosch’s MEMS revenues have increased by 20 percent to top $1.2B, driven by consumer sales. STMicroelectronics’ revenue is thus now lagging $400M behind. Compared to 2013, the top five companies remain unchanged and together they earn $3.8B, around a third of the total MEMS business. However, Bosch’s dominance is clear, as its revenues now account for around one-third of that figure. Among the 10 or so MEMS titans that are currently sharing most of the MEMS market, Yole distinguishes the “Titans with Momentum” from the “Struggling Titans”

Titans with Momentum group includes Bosch, InvenSense and others.

“Bosch’s case is particularly noteworthy as it is today the only MEMS company in dual markets – namely automotive and consumer – that has the right R&D/production infrastructure,” said Dr Eric Mounier, Senior Technology & Market Analyst, MEMS devices & Technology at Yole.

STMicroelectronics, Texas Instruments, Knowles, Denso and Panasonic are part of the second group, “Struggling Titans.” These companies are currently struggling to have an efficient value growth engine.

A third family is the upcoming “Baby Titans” like Qorvo and Infineon that have grown significantly in the past couple of years and could become serious MEMS players.

Yole has analyzed the three “Brick Walls” players have to overcome to develop a significant MEMS business. The first is to launch a first MEMS product on the market. The second is moving from one to multiple MEMS product lines to diversify a company’s portfolio. The last is the move from being a device maker to a system maker with a successful MEMS business. So far, only Bosch has achieved a very successful transition.

Yole also announces: “New MEMS devices are emerging.” Under its analysis, the consulting company considers gas and chemical sensors. Such devices are based on semiconductor technologies. But MEMS is a further improvement that can reduce size by half or more and also cut costs, thus opening up new opportunities. According to Yole’s analysis, MEMS-based gas sensors will be increasingly used in applications with formfactor/cost issues, particularly in wearables and then consumer applications such as smartphones.

Another example is MEMS micro mirrors. Yole explains: “They are attracting new interest from the market for optical datacom, with Calient achieving impressive growth, or human-machine interfaces, as demonstrated by Intel’s acquisition of Lemoptix.”

Under its analysis on the MEMS & Sensors industry, Yole and its team took the opportunity to exchange with Jeanne Forget, Global Marketing Director, Bosch Sensortec and Dr Frank Schafer, Senior Manager of product management for automotive micro-electro-mechanical sensors (MEMS) at Robert Bosch on the evolution of the MEMS markets and the ability of Bosch, in the last 20 years and for the next decade, to build and maintain its unique leadership on MEMS industry. Full discussion is available on i-micronews.com, MEMS & Sensors news.