Category Archives: MEMS

By Jay Chittooran, SEMI Public Policy

Following through on his 2016 campaign promise, President Trump is implementing trade policies that buck conventional wisdom in Washington, D.C. and among U.S. businesses. Stiff tariffs and the dismantling of longstanding trade agreements – cornerstones of these new actions – will ripple through the semiconductor industry with particularly damaging effect. China, a chief target of criticism from President Trump, has again found itself in the crosshairs of the administration, with trade tensions rising to a fever pitch.

The Trump Administration has long criticized China for what it considers unfair trade practices, often zeroing in on intellectual property. In August 2017, the Office of the U.S. Trade Representative (USTR), charged with developing and recommending U.S trade policy to the president, launched a Section 301 investigation into whether China’s practice of forced technology transfer has discriminated against U.S. firms. As the probe continues, it is becoming increasingly clear that the United States will impose tariffs on China based on its current findings. Reports suggest that the tariffs could come soon, hitting a range of products from consumer electronics to toys. Other measures could include tightening restrictions on the trade of dual-use goods – those with both commercial and military applications – curbing Chinese investment in the United States, and imposing strict limits on the number of visas issued to Chinese citizens.

With China a major and intensifying force in the semiconductor supply chain, raising tariffs hangs like the Sword of Damocles over the U.S. and global economies. A tariff-ignited trade war with China could stifle innovation, undermine the long-term health of the semiconductor industry, and lead to unintended consequences such as higher consumer prices, lower productivity, job losses and, on a global scale, a brake on economic growth.

Other recently announced U.S. trade actions could also cloud the future for semiconductor companies. The Trump administration, based on two separate Section 232 investigations claiming that overproduction of both steel and aluminum are a threat to U.S. national security, recently levied a series of tariffs and quotas on every country except Canada and Mexico. While these tariffs have yet to take effect, the mere prospect has angered U.S. trading partners – most notably Korea, the European Union and China. Several countries have threatened retaliatory action and others have taken their case to the World Trade Organization.

Trade is oxygen to the semiconductor industry, which grew by nearly 30 percent last year and is expected to be valued at an estimated $1 trillion by 2030. Make no mistake: SEMI fully supports efforts to buttress intellectual property protections. However, the Trump administration’s unfolding trade policy could antagonize U.S. trade partners.

For its part, SEMI is weighing in with USTR on these issues, underscoring the critical importance of trade to the semiconductor industry as we educate policymakers on trade barriers to industry growth and encourage unobstructed cross-border commerce to advance semiconductors and the emerging technologies they enable. On behalf of our members, we continue our work to increase global market access and lessen the regulatory burden on global trade. If you are interested in more information on trade, or how to be involved in SEMI’s public policy program, please contact Jay Chittooran, Public Policy Manager, at [email protected].

Originally published on the SEMI blog.

SEMICON West, the flagship U.S. event for connecting the electronics manufacturing supply chain, has opened registration for the July 10-12, 2018, exposition at the Moscone Center in San Francisco, California. Building on a year of record-breaking industry growth, SEMICON West 2018 will highlight the engines of future industry expansion including smart transportation, smart manufacturing, smart medtech, smart data, big data, artificial intelligence, blockchain and the Internet of Things (IoT). Click here to register.

Themed BEYOND SMART, SEMICON West 2018 sets it sights on the growing impact of cognitive learning technologies and other industry disruptors with programs and new Smart Pavilions including Smart Manufacturing and Smart Transportation to showcase interactive technologies for immersive, virtual experiences. Each Pavilion will feature a Meet the Experts Theater with an intimate setting for attendees to engage informally with industry thought leaders.

Smart Workforce Pavilion: Connecting Next-Generation Talent with the Microelectronics Industry

The SEMI Smart Workforce Pavilion at SEMICON West 2018 leverages the largest microelectronic manufacturing event in North America to draw the next generation of innovators. Reliant on a highly skilled workforce, the industry today is saddled with thousands of job openings and fierce competition for workers, bringing renewed focus to strengthening its talent pipeline. Educational and engaging, the Pavilion connects the microelectronics industry with college students and entry-level professionals interested in career opportunities.

In the Workforce Pavilion “Meet the Experts” Theater, industry engineers will share insights and inspiration about their personal working experiences and career advisors will offer best practices. Recruiters from top companies will be available for on-the-spot interviews, while career coaches offer mentoring, tips on cover letter and resume writing, job-search guidance, and more. Visitors will learn more about the industry’s vital role in technological innovation in today’s connected world.

This year, SEMI will also host High Tech U (HTU) in conjunction with the SEMICON West Smart Workforce Pavilion. The highly-interactive program supported by Advantest, Edwards, KLA-Tencor and TEL exposes high school students to STEM education pathways and stimulates excitement about careers in the industry.

Free registration with three-day access and shuttle service to SEMICON West are available to all college students. Students are encouraged to register for the mentor program, attend keynotes and tour the exposition hall to see everything the industry has to offer.  To learn more, visit Smart Workforce Pavilion and College Track to preview how students can enter to win a $500 hiring bonus!

Three Ways to Experience the Expo

Attendees can tailor their SEMICON West experience to meet their specific interests. The All-In pass covers every program and event, while the Thought-Leadership and Expo-Only packages offer scaled pricing and program options. Attendees can also purchase select events and programs à la carte, including exclusive IEEE-sponsored sessions, the SEMI Market Symposium, and the STEM Rocks After-hours Party, a fundraising event to support the SEMI Foundation.

CEA-Leti, a French technology research institute of the CEA and Inac, a joint fundamental research institute between the CEA and the University Grenoble Alpes, today announced a breakthrough towards large-scale fabrication of quantum bits, or qubits, the elementary bricks of future quantum processors. They demonstrated on a 300 mm pre-industrial platform a new level of isotopic purification in a film deposited by chemical vapor deposition (CVD). This enables creating qubits in thin layers of silicon using a very high purity silicon isotope, 28Si, which produces a crystalline quality comparable to thin films usually made of natural silicon.

“Using the isotope 28Si instead of natural silicon is crucial for the optimization of the fidelity of the silicon spin qubit,” said Marc Sanquer, a research director at Inac. “The fidelity of the spin qubit is limited to small values by the presence of nuclear spins in natural silicon. But spin qubit fidelity is greatly enhanced by using 28Si, which has zero nuclear spin. We expect to confirm this with qubits fabricated in a pre-industrial CMOS platform at CEA-Leti.” 

Qubits are the building blocks of quantum information. They can be made in a broad variety of material systems, but when it comes to the crucial issue of large-scale integration, the range of possible choices narrows significantly. Silicon spin qubits have a small size and are compatible with CMOS technology. They therefore present advantages for large-scale integration compared to other types of qubits.

Since 2012, when the first qubits that relied on electron spins were reported, the introduction of isotopically purified 28Si has led to significant enhancement of the spin coherence time. The longer spin coherence lasts, the better the fidelity of the quantum operations.

Quantum effects are essential to understanding how basic silicon micro-components work, but the most interesting quantum effects, such as superposition and entanglement, are not used in circuits. The CEA-Leti and Inac results showed that these effects can be implemented in CMOS transistors operated at low temperature.

CEA-Leti and Inac previously reported preliminary steps for demonstrating a qubit in a process utilizing a natural silicon-on-insulator (SOI) 300 mm CMOS platform1. The qubit is an electrically controlled spin carried by a single hole in a SOI transistor. In a paper published in npj Quantum Information2., CEA-Leti and Inac reported that an electron spin in a SOI transistor can also be manipulated by pure electrical signals, which enable fast and scalable spin qubits.

“To progress towards a practical and useful quantum processor, it is now essential to scale up the qubit,” said Louis Hutin, a research engineer in CEA-Leti’s Silicon Components Division. “This development will have to address variability, reproducibility and electrostatic control quality for elementary quantum bricks, as is done routinely for standard microprocessors.”

To help CEA-Leti and Inac leverage nuclear spin free silicon in the CMOS platform, a silicon precursor was supplied by Air Liquide, using an isotopically purified silane of very high isotopic purity with a 29Si isotope content of less than 0.00250 percent, prepared by the Institute of Chemistry of High-Purity Substances at the Russian Academy of Sciences. The 29Si isotope is present at 4.67 percent in natural silicon and is the only stable isotope of silicon that carries a nuclear spin limiting the qubit coherence time.

A secondary ion mass spectrometry (SIMS) analysis done on the CVD-grown layer using this purified silane precursor showed29Si concentration less than 0.006 percent, and 30Si less than 0.002 percent, while 28Si concentration was more than 99.992 percent. These unprecedented levels of isotopic purification for a CVD-grown epilayer on 300 mm substrates are associated with surfaces that are smooth at the atomic scale, as verified by atomic force microscopy (AFM), haze and X-ray reflectometry measurements.

Leveraging their scientific and technological expertise, and the specific opportunities associated with the 300 mm silicon platform on the Minatec campus, CEA-Leti and Inac will continue to contribute to the scientific, technological and industrial dynamic on quantum technologies, enhanced by the implementation of the EC’s FET Flagships initiative in this domain.

  1. “A CMOS silicon spin qubit”, arXiv:1605.07599 Nature Communications 7, Article number: 13575 (2016) doi:10.1038/ncomms13575
  1. “Electrically driven electron spin resonance mediated by spin-valley-orbit coupling in a silicon quantum dot”, Nature PJ Quantum Information (2018) 4:6; doi:10.1038/s41534-018-0059-1

GLOBALFOUNDRIES today announced a new ecosystem partner program, called RFWave, designed to simplify RF design and help customers reduce time-to-market for a new era of wireless devices and networks.

The last few years there has been an increasing demand for connected devices and systems that will require innovations in radio technologies to support the new modes of operation and higher capabilities. The RFWave Partner Program builds upon GF’s 5G vision and roadmap, with a focus on the company’s industry-leading radio frequency (RF) solutions, such as FD-SOI, RF CMOS (bulk and advanced CMOS nodes), RF SOI and silicon germanium (SiGe) technologies. The program provides a low-risk, cost-effective path for designers seeking to build highly optimized RF solutions for a range of wireless applications such as IoT across various wireless connectivity and cellular standards, standalone or transceiver integrated 5G front end modules, mmWave backhaul, automotive radar, small cell and fixed wireless and satellite broadband.

RFWave enables customers to build innovative RF solutions as well as packaging and test solutions. Initial partners have committed a set of key offerings to the program, including:

  • tools (EDA) that complement industry leading design flows by adding specific modules to easily leverage features of GF’s RF technology platforms,
  • a comprehensive library of design elements (IP), including foundation IP, interfaces and complex IP to enable foundry customers to start their designs using pre-validated IP elements,
  • resources (design consultation, services), trained and globally distributed, for Partners to gain easy access to support in developing solutions using GF’s RF technologies

“An explosion of digital information is expected to drive an enormous amount of growth in the coming years and our customers are already preparing for a future of seamless, reliable ultra high data rate wireless connectivity everywhere,” said Bami Bastani, senior vice president of GF’S RF Business Unit. “As a leader in RF, GF’s RFWave program takes industry collaboration to a new level, enabling our customers to build differentiated, highly integrated RF-tailored solutions that are designed to accelerate the next wave of technology.”

The RFWave Partner Program creates an open framework to allow selected partners to integrate their products or services into a validated, plug-and-play catalog of design solutions. This level of integration allows customers to create high-performance designs while minimizing development costs through access to a broad set of quality offerings, specific to RF technology. The partner ecosystem positions members and customers to take advantage of ubiquitous connectivity and the broad adoption of GF’s industry-leading RF technology platforms.

Initial members of the RFWave Partner Program are: asicNorth, Cadence, CoreHW, CWS, Keysight Technologies, Spectral Design, and WEASIC. These companies have already initiated work to deliver innovative, highly optimized RF solutions.

The ConFab — an executive invitation-only conference now in its 14th year — brings together influential decision-makers from all parts of the semiconductor supply chain for three days of thought-provoking talks and panel discussions, networking events and select, pre-arranged breakout business meetings.

In the 2018 program, we will take a close look at the new applications driving the semiconductor industry, the technology that will be required at the device and process level to meet new demands, and the kind of strategic collaboration that will be required. It is this combination of business, technology and social interactions that make the conference so unique and so valuable. Browse this slideshow for a look at this year’s speakers, keynotes, panel discussions, and special guests.

Visit The ConFab’s website for a look at the full, three-day agenda for this year’s event.

KEYNOTE: How AI is Driving the New Semiconductor Era

Rama Divakaruni_June_2014presented by Rama Divakaruni, Advanced Process Technology Research Lead, IBM

The exciting results of AI have been fueled by the exponential growth in data, the widespread availability of increased compute power, and advances in algorithms. Continued progress in AI – now in its infancy – will require major innovation across the computing stack, dramatically affecting logic, memory, storage, and communication. Already the influence of AI is apparent at the system-level by trends such as heterogeneous processing with GPUs and accelerators, and memories with very high bandwidth connectivity to the processor. The next stages will involve elements which exploit characteristics that benefit AI workloads, such as reduced precision and in-memory computation. Further in time, analog devices that can combine memory and computation, and thus minimize the latency and energy expenditure of data movement, offer the promise of orders of magnitude power-performance improvements for AI workloads. Thus, the future of AI will depend instrumentally on advances in devices and packaging, which in turn will rely fundamentally on materials innovations.

Imec, a research and innovation hub in nanoelectronics and digital technologies, today presented its annual Lifetime of Innovation Award to Dr. Irwin Jacobs, Founding Chairman and CEO Emeritus of Qualcomm. The annual industry honor is presented to the individual who has significantly advanced the field of semiconductor technology.  The formal presentation will be made at the global Imec Technology Forum (ITF) in May in Belgium.

In making the announcement, Luc Van den hove, president and CEO of imec, said: “Irwin Jacobs’ many technological contributions laid the groundwork for creating the mobile industry and markets that we know today. Under his leadership, Qualcomm developed two-way mobile satellite communications and tracking systems deemed the most advanced in the world. He pioneered spread-spectrum technology and systems using CDMA (code division multiple access), which became a digital standard for cellular phone communications. Together, these technologies opened mobile communications to the global consumer market.”

Irwin Jacobs began his career first as an assistant and then associate professor of electrical engineering at MIT and, later, as professor of computer science and engineering at the University of California in San Diego. While at MIT, he co-authored Principles of Communication Engineering, a textbook still in use. He began his corporate life as a cofounder of Linkabit, which developed satellite encryption devices.  In 1985, he co-founded Qualcomm, serving as CEO until 2005 and chairman through 2009.  His numerous awards include the National Medal of Technology, the Marconi Prize, and the Carnegie Medal of Philanthropy.  His honors include nine honorary degrees including doctor of engineering from the National Tsing Hua University, Taiwan.

Imec initiated the Lifetime of Innovation Award in 2015 at their annual global forum known as ITF (Imec Technology Forum).  The award marks milestones that have transformed the semiconductor industry.  The first recipient was Dr. Morris Chang, whose foundry model launched the fabless semiconductor industry, spurring creation of new innovative companies.  In 2016, Gordon Moore was honored, creator of the famous Moore’s law theory and co-founder of Intel.  Dr. Kinam Kim was honored in 2017 for his contributions in memory technologies and his visionary leadership at Samsung.

Luc Van den hove concluded, saying: “Our mission is to create innovation through collaboration. By gathering global technology leaders at the ITF, imec provides an open forum to share issues and trends challenging the semiconductor industry. In this international exchange, imec and participants outline ways to collaborate in bringing innovative solutions to market.”

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, and IBM (NYSE: IBM) today announced that the companies agreed to sign a license agreement on laser debonding technology. EVG plans to integrate IBM’s patented Hybrid Laser Release process into EVG’s advanced, field-proven temporary bonding and debonding equipment solutions, which can provide high-volume manufacturers with greater flexibility to implement optimized temporary bonding and debonding process flows. Thanks to the added process variants from IBM that will be supported by EVG’s equipment portfolio, customers can choose from a wide range of bonding, cleaning and metrology process options to help address their temporary bonding and debonding requirements and applications.

The result, which is an advanced laser debonding solution based on EVG’s combination of the technology licensed from IBM with EVG’s know-how, encompasses methods and designs for UV and IR laser debonding (designed to enable the use of glass or silicon carriers) as well as inspection of the bond interfaces. The technologies contributed by IBM help EVG implement designs that address the industry’s critical requirements for temporary bonding and debonding, including high throughput, low wafer stress for high yield, and low cost of ownership of the laser equipment, processing and consumables. The advanced EVG solution encompasses techniques to help protect chips from heat and laser damage, as well as chemical clean technologies for device and carrier wafers.

A scientific team led by the Department of Energy’s Oak Ridge National Laboratory has found a new way to take the local temperature of a material from an area about a billionth of a meter wide, or approximately 100,000 times thinner than a human hair.

This discovery, published in Physical Review Letters, promises to improve the understanding of useful yet unusual physical and chemical behaviors that arise in materials and structures at the nanoscale. The ability to take nanoscale temperatures could help advance microelectronic devices, semiconducting materials and other technologies, whose development depends on mapping the atomic-scale vibrations due to heat.

From left, Andrew Lupini and Juan Carlos Idrobo use ORNL's new monochromated, aberration-corrected scanning transmission electron microscope, a Nion HERMES to take the temperatures of materials at the nanoscale. Credit: Oak Ridge National Laboratory, US Dept. of Energy; photographer Jason Richards

From left, Andrew Lupini and Juan Carlos Idrobo use ORNL’s new monochromated, aberration-corrected scanning transmission electron microscope, a Nion HERMES to take the temperatures of materials at the nanoscale. Credit: Oak Ridge National Laboratory, US Dept. of Energy; photographer Jason Richards

The study used a technique called electron energy gain spectroscopy in a newly purchased, specialized instrument that produces images with both high spatial resolution and great spectral detail. The 13-foot-tall instrument, made by Nion Co., is named HERMES, short for High Energy Resolution Monochromated Electron energy-loss spectroscopy-Scanning transmission electron microscope.

Atoms are always shaking. The higher the temperature, the more the atoms shake. Here, the scientists used the new HERMES instrument to measure the temperature of semiconducting hexagonal boron nitride by directly observing the atomic vibrations that correspond to heat in the material. The team included partners from Nion (developer of HERMES) and Protochips (developer of a heating chip used for the experiment).

“What is most important about this ‘thermometer’ that we have developed is that temperature calibration is not needed,” said physicist Juan Carlos Idrobo of the Center for Nanophase Materials Sciences, a DOE Office of Science User Facility at ORNL.

Other thermometers require prior calibration. To make temperature graduation marks on a mercury thermometer, for example, the manufacturer needs to know how much mercury expands as the temperature rises.

“ORNL’s HERMES instead gives a direct measurement of temperature at the nanoscale,” said Andrew Lupini of ORNL’s Materials Science and Technology Division. The experimenter needs only to know the energy and intensity of an atomic vibration in a material–both of which are measured during the experiment.

These two features are depicted as peaks, which are used to calculate a ratio between energy gain and energy loss. “From this we get a temperature,” Lupini explained. “We don’t need to know anything about the material beforehand to measure temperature.”

In 1966, also in Physical Review Letters, H. Boersch, J. Geiger and W. Stickel published a demonstration of electron energy gain spectroscopy, at a larger length scale, and pointed out that the measurement should depend upon the temperature of the sample. Based on that suggestion, the ORNL team hypothesized that it should be possible to measure a nanomaterial’s temperature using an electron microscope with an electron beam that is “monochromated” or filtered to select energies within a narrow range.

To perform electron energy gain and loss spectroscopy experiments, scientists place a sample material in the electron microscope. The microscope’s electron beam goes through the sample, with the majority of electrons barely interacting with the sample. In electron energy loss spectroscopy, the beam loses energy as it passes through the sample, whereas in energy gain spectroscopy, the electrons gain energy from interacting with the sample.

“The new HERMES lets us look at very tiny energy losses and even very small amounts of energy gain by the sample, which are even harder to observe because they are less likely to happen,” Idrobo said. “The key to our experiment is that statistical physical principles tell us that it is more likely to observe energy gain when the sample is heated. That is precisely what allowed us to measure the temperature of the boron nitride. The monochromated electron microscope enables this from nanoscale volumes. The ability to probe such exquisite physical phenomena at these tiny scales is why ORNL purchased the HERMES.”

ORNL scientists are constantly pushing the capabilities of electron microscopes to allow new ways of conducting forefront research. When Nion electron microscope developer Ondrej Krivanek asked Idrobo and Lupini, “Wouldn’t it be fun to try electron energy gain spectroscopy?” they jumped at the chance to be the first to explore this capability of their HERMES instrument.

Nanoscale resolution makes it possible to characterize the local temperature during phase transitions in materials–an impossibility with techniques that do not have the spatial resolution of HERMES spectroscopy. For example, an infrared camera is limited by the wavelength of infrared light to much larger objects.

Whereas in this experiment the scientists tested nanoscale environments at room temperature to about 1300 degrees Celsius (2372 degrees Fahrenheit), the HERMES could be useful for studying devices working across a wide range of temperatures, for example, electronics that operate under ambient conditions to vehicle catalysts that perform over 300 C/600 F.

Micron Technology Inc. (Nasdaq:MU) announced today that the company has appointed Raj Talluri as senior vice president and general manager of the Mobile Business Unit.

In this role, Talluri will be responsible for leading and growing Micron’s mobile business. This includes building world-class mobile solutions to address the growing market opportunity driven by new usage models, from low-end devices to flagship smartphones. Talluri will report to Sumit Sadana, Micron’s executive vice president and chief business officer.

Talluri is a seasoned leader, with 25 years of experience in the semiconductor industry in executive roles spanning business, engineering management and strategic marketing. He joins Micron after nine years at Qualcomm, where he most recently served as senior vice president of product management, responsible for the company’s Internet of Things business and, before that, its mobile computing platform. Before joining Qualcomm, Talluri held executive positions at Texas Instruments, where he worked for sixteen years. His last role was general manager of the cellular media solution business in the wireless terminals business unit.

“Emerging usage models such as artificial intelligence, augmented reality and advanced imaging are increasing the complexity of devices, requiring new ways of processing, sharing and utilizing data, and making memory and storage increasingly critical to the mobile platform,” said Sadana. “Raj’s deep technical expertise and customer relationships in the mobile space, combined with his vision and business experience, make him the ideal choice to lead our mobile business unit.”

Talluri earned a Ph.D. in electrical engineering from the University of Texas in Austin. He also earned a Master of Engineering degree from Anna University in Chennai, India, and a Bachelor of Engineering from Andhra University in Waltair, India. He holds 13 U.S. patents relating to image processing, video compression and media processor architectures.

Scientists at Rice University and the Indian Institute of Science, Bangalore, have discovered a method to make atomically flat gallium that shows promise for nanoscale electronics.

The Rice lab of materials scientist Pulickel Ajayan and colleagues in India created two-dimensional gallenene, a thin film of conductive material that is to gallium what graphene is to carbon.

Extracted into a two-dimensional form, the novel material appears to have an affinity for binding with semiconductors like silicon and could make an efficient metal contact in two-dimensional electronic devices, the researchers said.

The new material was introduced in Science Advances.

Gallium is a metal with a low melting point; unlike graphene and many other 2-D structures, it cannot yet be grown with vapor phase deposition methods. Moreover, gallium also has a tendency to oxidize quickly. And while early samples of graphene were removed from graphite with adhesive tape, the bonds between gallium layers are too strong for such a simple approach.

So the Rice team led by co-authors Vidya Kochat, a former postdoctoral researcher at Rice, and Atanu Samanta, a student at the Indian Institute of Science, used heat instead of force.

Rather than a bottom-up approach, the researchers worked their way down from bulk gallium by heating it to 29.7 degrees Celsius (about 85 degrees Fahrenheit), just below the element’s melting point. That was enough to drip gallium onto a glass slide. As a drop cooled just a bit, the researchers pressed a flat piece of silicon dioxide on top to lift just a few flat layers of gallenene.

They successfully exfoliated gallenene onto other substrates, including gallium nitride, gallium arsenide, silicone and nickel. That allowed them to confirm that particular gallenene-substrate combinations have different electronic properties and to suggest that these properties can be tuned for applications.

“The current work utilizes the weak interfaces of solids and liquids to separate thin 2-D sheets of gallium,” said Chandra Sekhar Tiwary, principal investigator on the project he completed at Rice before becoming an assistant professor at the Indian Institute of Technology in Gandhinagar, India. “The same method can be explored for other metals and compounds with low melting points.”

Gallenene’s plasmonic and other properties are being investigated, according to Ajayan. “Near 2-D metals are difficult to extract, since these are mostly high-strength, nonlayered structures, so gallenene is an exception that could bridge the need for metals in the 2-D world,” he said.