Category Archives: MEMS

Energy loss due to scattering from material defects is known to set limits on the performance of nearly all technologies that we employ for communications, timing, and navigation. In micro-mechanical gyroscopes and accelerometers, such as those commonly found in cellphones today, microstructural disorder impacts measurement drift and overall accuracy of the sensor, analogous to how a dirty violin string might impact one’s enjoyment of beautiful music. In optical fiber communication systems, scattering from material defects can reduce data fidelity over long distances thereby reducing achievable bandwidth. Since defect-free materials cannot be obtained, how can we possibly improve on the fundamental technological limits imposed by disorder?

A research collaboration between the University of Illinois at Urbana-Champaign, the National Institute of Standards and Technology, and the University of Maryland has revealed a new technique by which scattering of sound waves from disorder in a material can be suppressed on demand. All of this, can be simply achieved by illuminating with the appropriate color of laser light. The result, which is published in Nature Communications, could have a wide-ranging impact on sensors and communication systems.

This is a microscope image of a silica glass resonator and optical fiber waveguide. Light and sound circulating in this type of resonator are shown to exhibit chiral effects in this study. (Credit: Gaurav Bahl, University of Illinois Department of Mechanical Science and Engineering)

This is a microscope image of a silica glass resonator and optical fiber waveguide. Light and sound circulating in this type of resonator are shown to exhibit chiral effects in this study. (Credit: Gaurav Bahl, University of Illinois Department of Mechanical Science and Engineering)

Gaurav Bahl, an assistant professor of mechanical science and engineering, and his research team have been studying the interaction of light with sound in solid state micro-resonators. This new result is the culmination of a series of experiments pursued by his team over the past several years, and a new scientific question posed in the right place.

“Resonators can be thought of as echo chambers for sound and light, and can be as simple as micro-spherical balls of glass like those we used in our study,” Bahl explained. “Our research community has long understood that light can be used to create and amplify sound waves in resonators through a variety of optical forces. The resonant echoes help to increase the interaction time between sound, light, and material disorder, making these subtle effects much easier to observe and control. Since interactions within resonators are fundamentally no different from those taking place in any other system, these can be a really compact platform for exploring the underlying physics.”

The key to suppressing scattering from disorder is to induce a mismatch in the propagation between the original and scattered directions. This idea is similar to how an electric current prefers to flow along the path of least resistance, or how water prefers to flow through a wider pipe rather than a constricted one. To suppress back-scattering of forward-moving sound waves, one must create a large acoustic impedance in the backward direction. This asymmetry for forward and backward propagating waves is termed as chirality of the medium. Most solid-state systems do not have chiral properties, but these properties can be induced through magnetic fields or through space-time variation of the medium.

“A few years ago, we discovered that chirality can be induced for light using an opto-mechanical phenomenon, in which light couples with propagating sound waves and renders the medium transparent. Our experiments at that time showed that the induced optical transparency only allows light to move unidirectionally, that is, it creates a preferentially low optical impedance in one direction,” Bahl said. “It is then that we met our collaborator Jacob Taylor, a physicist at NIST, who asked us a simple question. What happens to the sound waves in such a system?”

“Our theoretical modeling predicted that having a chiral system for sound propagation could suppress any back-scattering that may have been induced by disorder,” explained Taylor. “This concept arose from work we’ve been doing in the past few years investigating topological protection for light, where chiral propagation is a key feature for improving the performance of devices. Initially the plan with Bahl’s team was just to show a difference between the forward and backward propagating sound waves, using a cooling effect created by light. But the system surprised us with an even stronger practical effect than expected.”

That simple question launched a new multi-year research effort in a direction that has not been explored previously. Working in close collaboration, the team discovered that Brillouin light scattering, a specific kind of opto-mechanical interaction, could also induce chirality for sound waves. Between the experimental tools in Bahl’s lab, and the theoretical advancements in Taylor’s lab, the pieces of the puzzle were already in place.

“We experimentally prepared a chiral optomechanical system by circulating a laser field in the clockwise direction in a silica glass resonator. The laser wavelength, or color, was specially arranged to induce optical damping of only clockwise sound waves. This created a large acoustic impedance mismatch between clockwise and counter-clockwise directions of propagation,” explained Seunghwi Kim, first author of the study. “Sound waves that were propagating the clockwise direction experienced very high losses due to the opto-mechanical cooling effect. Sound waves moving in the counter-clockwise direction could move freely. Surprisingly, we saw a huge reduction of scattering loss for counter-clockwise sound waves, since those waves could no longer scatter into the clockwise direction! In other words, even though disorder was present in the resonator, its action was suppressed.”

Just as sound is the primary method of voice communication between humans, electromagnetic waves like radio and light are the primary technology used for global communications. What could this discovery mean for the communications industry? Disorder and material defects are unavoidable optical fiber systems, resulting in lower data fidelity, bit errors, and bandwidth limitations. The team believes that technologies based on this discovery could be leveraged to circumvent the impact of unavoidable material defects in such systems.

“We’ve seen already that many sensors, such as those found in your phone or in your car, can be limited by intrinsic defects in the materials,” added Taylor. “The approach introduced here provides a simple means of circumventing those challenges, and may even help us approach the limits set by quantum mechanics, rather than our own engineering challenges.”

Practical applications of this result may not be too many years off. Reduction of mechanical losses could also directly improve mechanics-based inertial navigation sensors that we use today. Examples that we encounter in daily life are accelerometers and gyroscopes, without which our mobile phones would be a lot less capable, and our cars and airplanes a lot less safe.

Worldwide semiconductor capital spending is projected to increase 10.2 percent in 2017, to $77.7 billion, according to Gartner, Inc. This growth rate is up from the previous quarter’s forecast of 1.4 percent, due to continued aggressive investment in memory and leading-edge logic which is driving spending in wafer-level equipment (see Table 1).

“Spending momentum is more concentrated in 2017 mainly due to strong manufacturing demand in memory and leading-edge logic. The NAND flash shortage was more pronounced in the first quarter of 2017 than the previous forecast, leading to over 20 percent growth of etch and chemical vapor deposition (CVD) segments in 2017 with a strong capacity ramp-up for 3D NAND,” said Takashi Ogawa, research vice president at Gartner.

According to Gartner’s latest view, the next cyclical down cycle will emerge in 2018 to 2019 in capital spending, compared with 2019 to 2020 in the previous quarter’s forecast. “Spending on wafer fab equipment will follow a similar cycle with a peak in 2018. While the most likely scenario will still keep positive growth in 2018, there is a concern that the growth will turn negative if the end-user demand in key electronics applications is weaker than expected,” said Mr. Ogawa.

Table 1: Worldwide Semiconductor Capital Spending and Equipment Spending Forecast, 2016-2020
(Millions of Dollars)

2016

2017

2018

2019

2020

Semiconductor Capital Spending

70,568.9

77,794.5

77,443.5

71,814.8

73,239.5

Growth (%)

9.1

10.2

-0.5

-7.3

2.0

Wafer Fab Equipment, Including Wafer-Level Packaging

37,033.1

43,661.0

43,690.4

40,515.8

41,342.7

Growth (%)

11.4

17.9

0.1

-7.3

2.0

Other Semiconductor Capital Spending

33,535.8

34,133.5

33,753.2

31,299.0

31,896.8

Growth (%)

6.8

1.8

-1.1

-7.2

1.9

Source: Gartner (July 2017)

This research is produced by Gartner’s Semiconductor Manufacturing program. This research program, which is part of the overall semiconductor research group, provides a comprehensive view of the entire semiconductor industry, from manufacturing to device and application market trends.

NXP Semiconductors N.V. (NASDAQ:NXPI) announced a $22 million dollar program that expands its operations in the United States, enabling the Company’s US facilities to manufacture security chips for government applications that can support critical US national and homeland security programs. Upon completion of the expansion project, NXP facilities in Austin and Chandler will be certified to manufacture finished products that exceed the highest domestic and international security and quality standards.

“This initiative advances NXP’s long-term commitment to developing secure ID solutions for federal, state and local government programs in the United States and demonstrates our deep dedication to serving the American market,” said Ruediger Stroh, Executive Vice President of Security and Connectivity at NXP. “The expansion program further positions NXP to deliver solutions for the IoT, connected devices and many other fast-growing applications in the United States as we continue to be a major contributor to the country’s global leadership in the semiconductor industry.”

As the market leader in secure identification solutions, NXP’s proven technology is included in core components that power secure government-issued ID documents in more than 120 countries, and is used by 95 countries worldwide to secure electronic passport programs.

Steve Adler, the Mayor of Austin, said, “We are excited to see NXP investing in Austin and in the cyber security of our country. We trust this initiative will also secure thousands of jobs and further foster the growth of Austin as a major technology hub.”

NXP R&D manufacturing facilities in San Jose, Austin and Chandler have also undergone a thorough security cite certification process to produce Common Criteria EAL6+ SmartMX microcontroller family products. Common Criteria is an international set of guidelines and specifications developed for evaluating information security products to ensure they meet a rigorous security standard for government deployments.

Knowles Corporation (NYSE: KN) today announced the appointment of Dr. Cheryl Shavers to the Board of Directors. Her appointment is effective August 1, 2017 and expands the Board to 9 directors, 8 of whom are independent.

Dr. Cheryl Shavers currently serves as Chief Executive Officer of Global Smarts, Inc. an advisory services and strategy firm which she founded in 2001. In this role, she consults small and established businesses as well as government agencies on managing growth opportunities and the innovative process. Between 1999 and 2001, Dr. Shavers served as the Undersecretary of Commerce for Technology at the U.S. Department of Commerce, where she oversaw the Office of Technology Policy and the Technology Administration, the focal point for partnerships between the US government and the private sector pertaining to commercial and industrial innovation, productivity and economic growth. She also oversaw the National Institute of Standards and Technology, the National Technical Information Service and the Office of Space Commercialization. Dr. Shavers was one of the highest-ranking technologists in the Clinton Administration at the time. Prior to joining the Clinton administration, she held a variety of roles at Intel Corporation and Hewlett-Packard, including director of Emerging Technologies and sector manager of the Microprocessor Products Group for Intel. Dr. Shavers also is a director of Rockwell Collins.

Dr. Shavers holds a doctorate in Solid State Chemistry and a bachelor’s degree in Chemistry from Arizona State University.

“I am excited to have Dr. Shavers as a member of the Board of Directors. She has a remarkable strategic mind and brings extensive experience with technology development, innovation and management of growth opportunities to the Board, which will be invaluable to the Company,” stated Jean-Pierre Ergas, Knowles’ Chairman.

Dr. Shavers has been appointed to serve on the Audit Committee and the Governance and Nominating Committee.

 

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, today announced worldwide sales of semiconductors reached $97.9 billion during the second quarter of 2017, an increase of 5.8 percent over the previous quarter and 23.7 percent more than the second quarter of 2016. Global sales for the month of June 2017 reached $32.6 billion, an uptick of 2.0 percent over last month’s total of $32.0 billion, and a surge of 23.7 percent compared to the June 2016 total of $26.4 billion. Cumulatively, year-to-date sales during the first half of 2017 were 20.8 percent higher than they were at the same point in 2016. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“The global semiconductor industry has enjoyed impressive sales growth midway through 2017, posting its highest-ever quarterly sales in Q2 and record monthly sales in June,” said John Neuffer, president and CEO, Semiconductor Industry Association. “Sales into the Americas market were particularly robust in June, and all regional markets saw growth of at least 18 percent year-over-year. Conditions are favorable for continued market growth in the months ahead.”

Regionally, sales increased compared to June 2016 in the Americas (33.4 percent), China (25.5 percent), Asia Pacific/All Other (19.5 percent), Europe (18.3 percent), and Japan (18.0 percent). Sales also were up across all regions compared to last month: the Americas (5.1 percent), Europe (1.9 percent), China (1.5 percent), Japan (1.0 percent), and Asia Pacific/All Other (0.8 percent).

June 2017

Billions

Month-to-Month Sales                              

Market

Last Month

Current Month

% Change

Americas

6.27

6.59

5.1%

Europe

3.11

3.16

1.9%

Japan

2.95

2.98

1.0%

China

10.25

10.41

1.5%

Asia Pacific/All Other

9.43

9.50

0.8%

Total

32.00

32.64

2.0%

Year-to-Year Sales                         

Market

Last Year

Current Month

% Change

Americas

4.94

6.59

33.4%

Europe

2.68

3.16

18.3%

Japan

2.52

2.98

18.0%

China

8.29

10.41

25.5%

Asia Pacific/All Other

7.95

9.50

19.5%

Total

26.38

32.64

23.7%

Three-Month-Moving Average Sales

Market

Jan/Feb/Mar

Apr/May/Jun

% Change

Americas

5.96

6.59

10.5%

Europe

2.96

3.16

7.1%

Japan

2.84

2.98

4.8%

China

10.06

10.41

3.4%

Asia Pacific/All Other

9.02

9.50

5.4%

Total

30.84

32.64

5.8%

Producers sometimes face challenges that go deep into the soil. They need answers to help the soil, on site. A portable field sensor can accurately measure minerals in soils more easily and efficiently than existing methods. And a research team, including a middle school student and her scientist father, can confirm it.

Calcium, like other minerals, is necessary for healthy plant growth. However, an excess of calcium — particularly in the form of calcium carbonate — can cause issues as it builds up in the soil.

“Calcium carbonate is basically a type of salt. It dissolves in water after a rainfall event and moves down through the soil,” explains David Weindorf. Weindorf is at the Department of Plant and Soil Science at Texas Tech University.

One main source of this calcium is limestone. At low levels, it makes thin threads or small white masses in the soil. However, in extreme cases it can actually take over the entire subsoil. Its hard surface can limit the ability of plant roots to grow. Getting this information on-the-fly is important for growers and soil scientists solving problems in the field.

Traditionally, soil scientists use their expertise to look at the soil and determine the stage of the calcium visually. There are also laboratory-based techniques that are very accurate, but they are not portable. The researchers wanted to see if a portable x-ray device — called PXRF, portable x-ray fluorescence spectrometry — would be better.

Based on their comparisons, the researchers found that, indeed, the device is a good method for measuring the calcium in the soil. The device can provide data on about 20 different elements, all in 60 seconds.

This can be a big advantage for soil scientists working in the field. It can also help scientists and farmers in developing countries who can’t afford expensive laboratory tests, or don’t have the expertise to visually appraise the soil.

“We are not advocating doing away with traditional assessment. We are simply providing a new data stream to help field soil scientists when evaluating carbonates in the field,” Weindorf explains. “Essentially, PXRF is another tool in the tool belt of the modern soil scientist, but it is by no means the only tool.”

Weindorf’s daughter was also part of the research. For Camille, this study was a way to branch out for her school’s science fair and do some original research. She scanned the soil samples and then helped her father perform the laboratory tests. She also helped calculate the summary statistics and write the paper.

“As a father, I just can’t overemphasize how proud I am of my daughter for taking on this science challenge with me,” he says. “I hope a project like this can inspire other students around her age to engage in original scientific inquiry. Truly, they are the future which will keep our country at the forefront of scientific innovation.”

SEMICON Southeast Asia will make its debut in Kuala Lumpur, Malaysia on May 8-10 at the new Malaysia International Trade & Exhibition Centre (MITEC). The move from Penang to Kuala Lumpur will attract new participation from key electronics clusters within Malaysia’s key Central and Southern regions ─ and will provide greater access to the entire electronics manufacturing downstream supply chain. Professionals in the electronics industry should check their calendars and note the new location and date, whether exhibiting or attending SEMICON Southeast Asia 2018.

Organised by SEMI, the global not-for-profit association advancing the global electronics manufacturing supply chain, SEMICON Southeast Asia has a recent legacy in Malaysia.  In 2016, the conference was the largest ever held at SPICE Arena in Penang, with approximately 6,700 visitors and over 200 exhibitors. This marked a 15 percent growth from 2016, making the conference the largest in three years. The move to Kuala Lumpur, with the larger venue, will accommodate the expanding scope of the conference as well as the growing numbers of visitors and exhibitors.

The growth of SEMICON Southeast Asia can be attributed to the rapid expansion of Malaysia’s Electrical & Electronics (E&E) market, which contributes 44 percent of the total manufacturing output and 26 percent of the total GDP of the region. Additionally, the E&E sector creates over 2.1 million jobs throughout Southeast Asia – and is forecasted to generate approximately U.S. $382 billion in exports in 2018.

Key highlights of SEMICON Southeast 2018:

  • Exhibition with 300+ booths and over 200 exhibitors
  • New Failure Analysis and Future Electronics Manufacturing pavilions
  • Opening Ceremony with the Malaysia Minister of International Trade & Industry
  • Technical and business forums on Advanced Packaging, Future Technology, IC Failure Analysis, Future Electronics Manufacturing, and Product & System Test, and Market Briefing
  • VIP Networking Reception
  • Futura-X at World of IoT, which showcases new applications
  • Vietnam Investment Seminar, featuring presentations from Ho Chi Minh City Semiconductor Industry Association (HSIA), ICDREC and Microlux

Sponsors for SEMICON Southeast Asia 2017 included 3M, Advantest, Air Products, AMEC, Applied Materials, ASE Group, Edwards, Evatec Process Systems, Global Foundaries, Hermes Epitek, Kulicke & Soffa, KLA Tencor, LAM Research, Merck, Mentor Graphics, NTT Data, Rudolph Technologies, SAS, Screen, SPTS, Tel, Thermo Fisher Scientific, Tibco, Toray, Xcerra, and Zeiss. Partners for the exposition include AEIS, INTI College Penang, investPenang, Malaysia Convention and Exhibition Bureau, MATRADE, Ministry of Tourism and Culture Malaysia, MIDA, Malaysia Truly Asia, Penang Tourism, Singapore Manufacturing Federation, Samenta, Touch Display Research, VLSI Consultancy, and YOLE Development.

For more information on SEMICON Southeast Asia, please visit www.semiconsea.org or contact [email protected]

 

Analog Devices, Inc. (ADI) today announced that it has become an affiliate member of Mcity at the University of Michigan. Mcity is a public-private partnership led by the University of Michigan to advance connected and automated vehicles. Among Mcity’s key initiatives is operating the Mcity Test Facility, which is the first purpose-built proving ground for testing connected and automated vehicles and technologies in simulated urban and suburban driving environments. Analog Devices will use the facility to test and refine future products in its Drive360 suite of technologies, including 28nm CMOS RADAR, solid state LIDAR, and high performance inertial measurement units for automated and autonomous driving applications.

By joining Mcity, ADI is committing to support the autonomous driving ecosystem as a premier semiconductor solutions provider and will use Mcity to understand market requirements through collaboration across the automotive design chain to bring connected and automated vehicle technologies to the commercial market.

ADI joins ranks with Mcity’s more than 65 industry members, which all play a role in creating a viable ecosystem to support connected and automated vehicles, including auto manufacturers and major parts suppliers, as well as vehicle communications, traffic infrastructure, and insurance companies, among others.

“Organizations like Mcity provide an important stage for testing products in real-world scenarios and for gathering real-time feedback from our customers and other key players in the autonomous driving ecosystem,” said Chris Jacobs, vice president, Autonomous Transportation and Safety, Analog Devices. “Working with the initiative will help shape our product and technology strategy by creating an open line of communication with customers and other industry leaders. This powerful connection will allow us to directly identify and address the toughest challenges to enable autonomous transportation.”

Three leading U.S. universities are the latest recipients of funding from the Nano-Bio Manufacturing Consortium (NBMC), operated by SEMI.  NBMC’s mission is to further the development of human performance monitoring (HPM), thereby broadening the use of advanced electronics in this highly anticipated application space. Among other applications, HPMs are expanding the fast growing wearable electronics markets. According to Research and Markets, “The global market for wearable electronic devices was valued at around USD $20 billion in 2016 and is expected to reach USD $97.8 billion, growing at a CAGR of around 24.1 percent from 2017 to 2023.”

The new awards announced today total more than $870,000 and include:

  • University of Arizona: To meet the needs of NBMC industry members, the University of Arizona will focus on determining which HPM sweat patch configuration is best suited to meeting performance requirements. The initial investigation will include a “lab-in-a-bandage” that collects and analyzes biomarkers within one minute from sweat secretion.  The follow-on project will determine the feasibility of using organic semiconductor sensor technology (compatible with flexible substrates and manufacturing techniques) for sweat biomarker detection sensitivity and selectivity with sweat sample volumes in the nano- and pico-liter range.
  • University of California at Los Angeles: UCLA will partner with i3 Electronics of Binghamton, NY to investigate the use of Fan-Out Wafer Level Packaging (FOWLP) methods as a new way to build versatile, biocompatible physically-flexible heterogeneous electronic systems. FOWLP is a relatively new packaging process that gaining widespread use in portable devices such as smart phones. It offers the advantages of true heterogeneous integration of different dies, including high performance electronics, tight pitch interconnects, and components (such as low profile passives) with a short turn-around, scalable, manufacturing process.
  • University of Massachusetts at Amherst: U Mass Amherst will conduct a detailed systematic assessment of microfluidic subsystem architecture and operational approaches for sweat-based biomarker detection.  The study will address issues associated with accurate, time-stamped sweat sample collection and delivery, effluent control and removal for continuous operation, and dynamic performance design aspects to address sample handling under conditions of high and low sweat rates.

“The NBMC program continues to push technology limits in ways that integrate leading edge microelectronics,” said Dr. Melissa Grupen-Shemansky, SEMI’s CTO for flexible electronics and advanced packaging.  “Consequently, SEMI is helping to identify new equipment, materials and process opportunities for our members and their customers.”

The NBMC program is funded through a cooperative agreement with the Air Force Research Laboratory in Dayton, Ohio.

For an increasing number of designs, companies are finding it beneficial to design their own ASICs with system-on-a- chip (SoC) complexity. For reasons of cost reduction, quality improvement, IP protection and security, a full turn-key ASIC can be achieved for $1-5 million, particularly if the design can be built using mature technology nodes.

To further explore this topic, we asked questions from three leading experts in the field. Participating in the Q&A are:

• Michel Villemain, CEO, Presto Engineering, Inc.
• Guillaume Etorre, VP Engineering, Devialet
• Venkata Simhadri, CEO, Gigacom Semiconductor

Q: What is the decision-making process for deter- mining which applications are best addressed with an ASIC vs standard, off-the-shelf components? How does one calculate non-recurring engineering (NRE) costs, for example, and how does the anticipated part volume impact the decision?

Etorre: In many cases, particularly for IoT or other space-constrained designs, going with multiple standard compo- nents is simply not an option. A single chip must embed the microcon- trollers, sensors, battery management system, radios, etc. required by the application, in the smallest possible form factor.

When space is available, a standard component approach can be more appropriate to meet tight deadlines or to address situations where demand for the product is unproven. It can also serve as a stop-gap to serve the market immediately while a lower-cost ASIC solution is being designed.

If demand for the product is proven, a net present value calculation over a range of scenarios (best, typ., worst case for volumes and schedule for instance) will provide guidance on the best approach. An ASIC typically carries higher NRE (design, tapeout, qualification, test) but yields lower unit cost than an off-the-shelf solution. Depending on anticipated volumes and cost of capital, the lower unit cost of an ASIC will outweigh the higher NRE.

Simhadri: Primarily two factors can impact a company’s decision to design its own ASIC.
1. Competitive advantage – If the company is building its system using off-the- shelf components, competition can quickly reproduce it and you are only left with software as the differentiating factor. In this situation, you must have your own ASIC to protect your IP.
2. Cost – When addressing large volume markets the unit cost becomes an important factor and the only way to cut down the cost is to integrate/optimize the off-the-shelf components.

The typical NRE cost includes the cost of design, proto- typing (shuttle) and qualifying the part. Companies typically use a few benchmarks to justify the upfront cost.

For example, NRE cost is primarily dependent on the infrastructure (staff and tools) the customer already has in place. If the company already has a design team, EDA tools, etc. then the incremental cost might not be too high. However, without a design infrastructure already in place, it’s going to be a lot more time- consuming and costly. In this case, it is much easier to work with an ASIC design house to have all the infra- structure and some of the building blocks put in place.

Villemain: NRE is somewhat challenging to calculate since the duration of the project is often underestimated and unpredicted issues (who really does anticipate them!) bring additional cost to such a project. One way of mitigating this is to use external sources provided on (primarily) fixed- cost engagements. Beside ROI on NRE (function of margins and volume, indeed), drivers for using ASICs include: form factor, reliability, IP, power consumption and security.

Q: What are the tools and supply chain partners needed to successfully design an ASIC solution, including EDA software, foundry, packaging and test house?

Simhadri: You need the standard EDA tools for both Analog/ Digital, if you are designing a mixed-signal chip. Typically, you will have to work with at least two EDA vendors, such as Synopsys, Cadence, or Mentor Graphics. Many of the foundries will also work with small companies, provided you show a path to volume. However, in terms of design support (pdks, libraries, etc) foundries with better design infrastructure can save significant time. If you are a start-up or doing it for the first time, it can be quite daunting to setup the relationships and you can lose quite a bit of time to get the process going. But there are ways to save time and cost by outsourcing some of the work to the right design companies and echo system partners.

Villemain: Success is a function of a combination of multiple competencies that need to work coher- ently throughout the life of the product, especially post-design: industrialization, supplier management, quality, planning, logistics and product sustaining. This typically represents more than ten different skillsets that need to be part of the extended product team.

Etorre:
• Availability of proven IP (CPU, peripherals, interconnects, digital & analog I/O,…) for the chosen technology node.
• Affordable EDA software, with specific packages for companies designing only one or two chips at any given time, for specific end-user products vs. fabless IC companies which can spread the EDA license cost over many different chip designs every year.
• Efficient turn-key supply chain partner that can abstract out the complexity of foundry, packaging, test, storage and logistics for companies that lack critical mass.

Q: With the rise of IoT, IIoT and wearables, there’s much interest in analog/mixed-signal ASICs. How are their requirements different from traditional digital designs?

Villemain: Analog/RF designs tend to be smaller in size and to require less aggressive wafer fab processes. From a design standpoint, they demand less expensive EDA tools and less costly verification. However, their characterization and test is typically more complex and requires more expertise than a purely digital equivalent. Finally, yield management can be more demanding as the equation design window vs. process window is left more to the engineers than digital products, which can use semi-automated tools.

Simhadri: The primary difference in the require- ments is power and connectivity. If the ASICs must be connected to the internet, determining which protocols you need to incorporate on to the chip makes a big difference. Power is going to be a huge differentiating factor for the wearables, and designers are looking at various power saving techniques in an effort to optimize the power. Also, the foundries are offering special process nodes like SOI to address these markets.

In addition to the standard low power techniques like voltage islands and power shut off modes, the ASIC can further optimize the power by custom- izing the IP blocks for the specific applications. For, example, serial interfaces that burn lot of power, can be optimized.

Etorre:
• Design cycle is longer for analog IP than for digital.
• It is therefore critical to choose a foundry and a node for which all or most of the required IP are available.
•Analog IP is typically not portable between foundries or between nodes without significant rework.• •Custom analog IP is therefore a significant investment that will be depreciated if a foundry change or node change is required.
• The best nodes for analog, MEMS, RF, high- voltage and digital are usually not the same.
• Selecting the most appropriate node for the applications is not a trivial task.
• Introducing new functionality in a subse- quent version of an ASIC can require a node change and therefore major redesign of analog / mixed signal circuits. Anticipating future requirements can help make better technology choices.

Q: How do mask set costs of more mature technologies (180-40nm node) compare with those of 28nm and below, and how do mask costs enter into the overall cost equation?

Simhadri: I strongly advise our customers to use shuttles to prototype the ASIC and completely qualify it before spending a huge amount on the full mask. As expected, the 180-40nm shuttle costs are signifi- cantly lower than 28/16nm.

Villemain: With verification being less of a factor for analog/RF designs, mask sets can become a significant part of NRE below 90nm. Process technology is obviously a leading factor, but in addition, process routes can be costly because of additional options or IP, implying the addition of a mask/process layer, and thus, decreasing ROI in smaller geometries. Also, cost plateaus do exist (depending on the foundries) due to equipment transition (wafer size, lithography technol- ogies, etc.)

Etorre: The mask cost ratio between older technol- ogies and more recent ones can reach 20:1. For a 180nm design, once design, qualification and test fixtures are factored in, mask cost is not a significant contributor to the overall NRE.

Q: Out of the various advantages of ASIC design — cost reduction, quality improvement, IP protection and security – how would you rank their importance. Are there other advantages to ASIC solutions?

Villemain: What we see in the industry is a combi- nation of those factors (cost reduction, quality to architect an ASIC that replaces the discrete compo- nents in the system, which can reduce the BOM improvement, IP protection and security) as a function of the market our customers are operating in. The most common drive is, of course, that of cost (ASICs usually bring a dramatic product cost reduction), although for infrastructure applications, reliability is a key criterion, while for battery-operated applica- tions, power consumption reduction is mandatory— and all are benefits of using an ASIC.

In addition, more and more IoT segments require security in order to be even just a contender in the market, and an ASIC-based solution offers both a certifiable source of design and a cost benefit as compared to standalone secured elements.

Finally, in very competitive markets, the IP differen- tiation that an ASIC provides is a huge benefit.

Simhadri: IP protection and security shall rank first, followed by cost reduction. In some cases, off-the-shelf chips may not meet the performance requirements.

Etorre:
1. Real estate savings – an ASIC-based design is much smaller than an off-the-shelf approach;
2. Cost reduction
3. IP protection
4. Quality improvement, if any – combining various
functions and technologies (analog, digital, RF, power, MEMS, etc.) on the same die can lead to lesser quality.

Q: How has your company benefitted from an ASIC approach?

Etorre: Devialet’s Analog-Digital Hybrid (ADH) audio amplification technology was first implemented with discrete components. This discrete design is used in our high-end Expert Pro amplifiers and it supports the widest range of operating conditions.

In our Phantom speakers, we had to fit the same technology is a much smaller area. We specialized the analog circuit for the specific speaker drivers used in the Phantom and we designed an ASIC to deal with the analog part of the ADH technology.

Simhadri: Gigacom has been working with a company in the industrial IoT space and building systems for sensing gases and air quality. We have worked together by 10x and reduce the area and power significantly at the same time.

Q: How has the supply chain evolved to meet this new kind of demand?

Villemain: The supply chain needs to evolve in order to focus more on the backend than the frontend. If SoC brought RFCMOS to mass adoption with connected product, IoT, relying on a sensor-specific package, must integrate a companion ASIC driver and a transceiver; System in Package back-end technologies are gaining tremendous momentum. More and more companies will design their own ASICs, on well-proven, stable fab processes. However, packaging, reliability, test and security will become prime drivers, defining not only product costs, but also the ability to ramp, yield and scale up in volume. Supply chains (and especially the management of supply chains) is evolving accordingly.

For example, until recently, building an ASIC for an IoT device required the assembly of a team of experts, each with expertise in a different part of the process. The design might be created in-house or through an outside firm, and large companies, like automotive manufacturers, might assemble whole organizations, often called “operations” departments, with the sole task of managing the production of the specialized devices they needed. For a small company, with a game-changing new product idea, the cost and delay of assembling such a team can be fatal. If a competitor beats you to market you might not get a second chance. This need for manufacturing expertise led to the creation of “outsourced operations” companies, like Presto Engineering, that can manage the entire semiconductor manufacturing process from the completion of the design to the delivery of the tested product. By reducing the risk, cost, and difficulty of the production process, companies, such as Presto, are playing a key role in accelerating the proliferation of application specific semiconductor solutions.

Etorre: By design, ASICs run in lower volumes that standard parts. The supply chain must adapt to deal with more customers running lower volumes. This creates an opportunity for companies providing turn-key supply chain services to bridge the gap between numerous mid-volume customers and tradi- tional foundries and packaging houses who only address the largest fabless IC vendors.

Simhadri: The supply chain needs some improve- ments in the following areas. The older process nodes from 180nm to 40nm have suddenly become popular for IoT applications. However, most of the PDKs and other collateral were developed for older EDA tool versions and they need to be updated. Also, most of the IP vendors are targeting their resources for developing the IP for the latest process nodes where they get the best returns on their investment. Some of this IP has to be ported back to enable the ASICs in older nodes.

Also, to bring up these ASICs, the industry needs good support for packaging and testing facilities and all the top vendors are focused on high volume and leading- edge ASICs. Companies like Presto can potentially fill the needs.