Category Archives: MEMS

By Michaël Tchagaspanian, Vice President of Sales and Marketing, Leti

Digital disruption begets innovation. Challenges equal opportunities. Those were clear messages during Leti Innovation Days recently in Grenoble, France. Over two days at the annual event, which this year coincided with Leti’s 50th anniversary, speakers and exhibitions highlighted challenges of the digital revolution and presented specific current-and-anticipated solutions for industry, healthcare and energy and the environment.

Coinciding with the launch of the administration of French President Emmanuel Macron, who has already talked of France becoming “a start-up nation”, Leti also noted the importance of creating and supporting startups that will help consumers, companies and countries address the challenges and opportunities of the digital revolution.

Citing challenges in the energy sector, Thierry Lepercq, executive vice president of research, technology and innovation at the international French energy company ENGIE, warned of potential energy blackouts and financial problems for traditional energy providers due to the growing penetration of alternative energy sources, the switch from fossil fuels – and energy sharing by households.

These developments, which ENGIE calls “Full 3D” – decarbonization, decentralization and digitalization – have destabilized traditional power systems and providers.

For example, a German residential battery-storage supplier allows residents to store energy at home and swap it on the grid, cutting out traditional electricity providers. Lepercq also noted that the rapid growth in the use of electric vehicles can load the grid with demand that was not anticipated even a few years ago. But the digital revolution also has prompted entrepreneurial responses. EV-Box, the Dutch company that has deployed more than 40,000 vehicle-charging stations in 20 countries, is gathering usage data, which will help officials understand the vehicles’ demands on the grid.

ENGIE acquired EV-Box this year as a strategic step towards operating in a completely new global energy paradigm.

Driving toward a new economy

Last month, Intel released a study that predicted autonomous vehicles will create a “Passenger Economy” – with mobility-as-a-service – that could grow to $800 billion in 2035 and to $7 trillion by 2050.

With autonomous vehicles, the car will no longer be a “stand-alone vehicle”, but “something that reacts with the environment”, said Mike Mayberry, corporate vice president and managing director of Intel Labs. Intel has opened advanced vehicle labs in the U.S. and Germany to explore the various requirements related to self-driving vehicles and the future of transportation. That includes sensing, in-vehicle computing, artificial intelligence, connectivity, and supporting cloud technologies and services.

When a panel discussion on driverless cars was asked when these vehicles will be in general use, Jean-François Tarabbia, CTO of Valeo, the automotive supplier to automakers worldwide, said “the better question is ‘why’”. And that depends in part on the industry’s ability to demonstrate vehicle safety. He said that traffic jams could be reduced by 30 percent with autonomous cars. Still, the cars will require a driver inside who will do something other than driving until he or she is needed to operate the vehicle.

Pierrick Cornet, brand incubator at Renault Nissan, said autonomous cars also will have to accommodate owners who occasionally want to drive their vehicles. For carmakers like Renault Nissan, the challenges are managing the cost and weight of the vehicles, which are loaded with batteries, as well as computing and sensing gear – and making them able to charge quickly.

Fabio Marchiò, automotive digital general manager at STMicroelectronics, noted that cars are the least-used appliance/machine in the household. He agreed with Tarabbia that safety and consumer resistance are primary roadblocks for the vehicles, but added that government regulations could slow down their widespread use.

Moore’s Law obtains

Outlining some of Intel’s R&D programs, Mayberry brushed aside frequent predictions that Moore’s Law has run its course. He said Intel expects Moore’s Law to be in effect at least through the next decade, because of the industry’s continued evolution to smaller technology nodes with new IC technologies.

In addition to focusing on enabling Moore’s Law going forward, Intel’s research on components and hardware includes developing novel integration techniques. But Intel Labs also is focused on enabling future product capabilities and “imagining what’s next”.

As part of that effort, Intel Labs has partnered with Princeton University to decode digital brain data, which is scanned using functional magnetic resonance imaging (fMRI). The goal is to reveal how neural activity gives rise to learning, memory and other cognitive functions such as human attention, control and decision-making.

Leti and Intel agreed last year to collaborate on strategic research programs, including the Internet of Things, high-speed wireless communication, security technologies and 3D displays.

Quantum computing

Also peering into the more-distant future, Leti CEO Marie Semeria noted development of Leti’s Si-CMOS quantum-technology platform.

“The quantum topic has recently become central, thanks to the huge advances made in solid-state implementation, both in superconducting systems and in silicon technologies,” she said. “Interest in silicon-based technologies is huge because of their reliability and their capability to reproduce industrial standards along with the low-noise characteristics and low variability of CMOS devices.”

Noting that the University of New South Wales recently demonstrated a promising two-qubit logic gate based on the silicon-28 isotope, Semeria said Leti had demonstrated the compatibility of such circuits with state-of-the-art CMOS processes.

“From an architectural point of view, it is clear that the future quantum computer will be hybrid. It will combine a quantum engine with a classical digital computer,” she explained. “The program that will run on such a machine will need to combine at least two computing models: a classical part, to prepare data and process results, and a quantum one. A tight connection between the two programming models will be necessary.”

With its history of pioneering in technology and its culture of spinning out new companies to further develop and commercialize innovative technologies, Leti is poised to help France achieve Macron’s goal: “I want France to be a ‘start-up nation’, meaning both a nation that works with and for the start-ups, but also a nation that thinks and moves like a start-up.”

Leti has launched 64 startups, including 13 in the past four years.

Digital innovations in healthcare

Jai Hakhu, president & CEO of HORIBA International Corporation (U.S.), explained how the digital revolution is creating in vitro diagnostics business potential by enabling delivery of preventive healthcare services in even remote regions of the world. In one of HORIBA and Leti’s joint projects, they are developing a hematology, microfluidics-based, lensfree, point-of-care and home-testing system that can be used in underdeveloped countries.

The collaboration is helping realize HORIBA’s vision of providing preventive self-testing anywhere in the world.

Leti’s start-up Avalun has developed a portable medical device for multiple-measurement capabilities using point-of-care testing. Other recent healthcare-related startups include Diabeloop, which is in the final stages of testing an artificial pancreas, and Aryballe Technologies, which is developing olfactory and gustatory sensors.

Routes to innovation

Those new companies were among the presenters at Leti’s immersive exhibition, “Routes to Innovation”, which was the focus of day two of the event. Entrepreneurs and Leti scientists offered more than 60 demonstrations of patented technologies, to show with concrete examples how Leti’s technological know-how and industrial transfer expertise can help French and international companies innovate and become more competitive.

The three “Digital Revolution” topics included “Micro-Nano Pathfinding”, showing how the diversity of Leti’s digital technologies are available to all economic sectors; “Cyber Physical Systems”, and “Business-Model Disruption”.

The “Environmental Transition” demos covered “Sustainable Activities”, “Monitoring Our World’ and “More with Less”. The “New Frontiers for Healthcare” demos covered “Prevention, Independence, Well Being”, “New Therapies” and “Analysis & Diagnosis”. 

Collaborating for technological sovereignty

During the event, Semeria and Fraunhofer Group for Microelectronics Chairman Hubert Lakner announced a wide-ranging collaboration to develop innovative, next-generation microelectronics technologies to spur innovation in their countries and strengthen European strategic and economic sovereignty.

The two institutes will initially focus on extending CMOS and More-than-Moore technologies to enable next-generation components for applications in the Internet of Things, augmented reality, automotive, health, aeronautics and other sectors, as well as systems to support French and German industries.

‘Smart everything everywhere’

Over the two days, a record number of guests, including CEOs, CTOs, journalists and special guests and speakers heard and saw examples of Leti’s advanced technology platforms, its commitment to research excellence and its vision for applying innovative technologies to challenges of the digital era.

Max Lemke, head of the Components and Systems Unit at the European Commission, noted that Leti’s contributions extend beyond microelectronics to cyber-physical systems, 5G, the Internet of Things, photonics and post-CMOS technologies. By supporting the digital transformation of industry, Leti plays a leading role in “smart everything everywhere”, Lemke said.

“Leti is excellently positioned to continue doing forward-looking research” on components and systems to build the foundation for Europe’s future competitiveness, and to play an instrumental role in supporting French and European industry in their digital transformation, he said.

By Dave Lammers

Keynote speakers Terry Higashi of Tokyo Electron Ltd. and Tom Caulfield of GlobalFoundries took the stage at the Yerba Buena Theater Tuesday morning to predict major changes in the goals and operations of the semiconductor industry.

higashi2013_11_600px_0 ThomasCaufieldSized

In many ways, 2017 has been marked by intense interest in the capabilities of neural networks and other forms of artificial intelligence (AI). Higashi, now a corporate director at TEL, predicted that AI and virtual reality are among the applications that will propel demand for semiconductors “almost without limit.” Neuromorphic processors, the veteran TEL executive said, “are one of the promising devices to enhance human creativity. They will be improved step by step, just as logic and memory devices were improved.”

Looking toward a future in which AI and human skills combine to resolve problems, Higashi predicted that today’s Von Neumann-based architectures and neuromorphic device will complement each other. “Artificial intelligence solutions will be proposed, and the challenges and problems will be solved by scientists and engineers. The combination of Von Neumann and neuromorphic computing gets us closer to true intelligence,” he said.

AI also will play a role in enhancing the immersive experiences promised by virtual reality, experiences which visionaries have predicted but which thus far mankind “has never fully experienced.”

Higashi said that by combining VR and AI, “we can attain a suspension of disbelief, and simply enjoy the experience. If we can provide the technologies, consumers will experience excitement and a form of happiness.”

Caulfield, the general manager of the Malta fab near Albany, agreed with Higashi’s assessment that that the semiconductor industry is seeing “new buds” that will bloom into large semiconductor markets.

However, Caulfield said that to achieve anything like the rate of technological progress seen over the first half century of the semiconductor industry, companies and customers will have to take collaboration to new levels. And he offered the collaboration between GlobalFoundries and AMD as an example.

“Collaboration, potentially, is the biggest thing we need to do. We need strategic partnerships, and not only among semiconductor manufacturers but also with equipment suppliers.”

At its Malta fab, GlobalFoundries builds all of AMD’s leading-edge discrete graphics engines and CPUs. “The AMD and GlobalFoundries engineering teams are so embedded with each other, one can hardly tell” which company an engineer works for, he said.

Noting the resurgence of AMD, Caulfield said “we are all proud to be part of that partnership.” And he pointed to another collaboration, between Samsung and GlobalFoundries, which allows customers to take the same 14nm design and choose whether to manufacture it at Samsung’s Austin fab or at Malta. “Customers can run photomasks in Austin or in Malta, New York and have the product look the same,” he said.

Government role

In such a collaboration-rich business environment, governments also have a role to play, Caulfield said.

“Public-private investments must imply a return to governments as well as to companies. Otherwise, they send the wrong message.” By investing several billion dollars in the Malta fab, GlobalFoundries and the state of New York put to work the well-educated young people who otherwise would have left the state in search of technology jobs. When Malta began operations, only 20 percent of the staff were educated in New York. Now, fully half of the workforce has benefited from a New York education.

“We were exporting talent. Now, the workforce has great opportunity within the state,” he said.

Both Higashi and Caulfield said major challenges face the industry. Higashi noted that innovation will be required to keep flash memory costs under control. “As data is captured by sensors and is transferred via the appropriate networks and stored in data centers, demand for NAND will be high. We must make huge efforts to reduce the overall cost, as the semiconductor industry is expected to provide enough volumes to support the Internet of Things.”

Caulfield said the performance of logic transistors has struggled to keep pace, even as density increases have continued. When the industry moved from 28nm to 14nm technologies, performance increased by fully 50 percent. But from 14nm to 10nm, speeds improved by about 18 percent, making shrinks primarily a cost improvement.

With the industry now focused on brining 7nm logic to the market, the question arises whether 5nm CMOS will provide enough performance to justify that node. While the jury on technology scaling is still out, Caulfield said the industry may have to move to gate all around (GAA) structures, or to non-silicon channel materials, in order to gain the kinds of performance improvements that customers expect from a new node.

Higashi said systems must get faster. “Real-time processing is crucial in the cyber world. And with robotic hands, there should be no delays in physical operations.”

“Memory, logic, and sensing make it possible for AI systems to solve problems much faster than a team of geniuses. We are now in a new era, one of super integration. In addition to improved specialty devices – based on logic, memory, and sensors – we must take these separate devices and put them together into fully integrated systems. It is time to make a pizza, with some of the best ingredients,” he said.

MEMS & Sensors Industry Group® (MSIG), the industry association advancing MEMS and sensors across global markets, is hosting a TechXPOT program today, titled “What’s Next for MEMS & Sensors: Big Growth of Disruptive Applications for Smart Sensing Changes the Business.” Speakers from industry and academia will explore the disruptive influence of MEMS and sensors on applications that span human-machine interfaces, disposable wireless electronics, and wireless sensor nodes for smart cities. They will also discuss advancements in piezoelectric materials for emerging applications as well as MEMS foundry process technologies that speed time to market.

“From smart autos and smart manufacturing to smart cities and smart health monitoring, emerging markets for MEMS and sensors are creating greater demand for integrated intelligence,” said Karen Lightman, vice president, MEMS & Sensors Industry Group, SEMI. “MSIG speakers at SEMICON West will help MEMS and sensors suppliers to more ably respond to this demand, as they learn how to add value through technological innovation and integration.”

Topics and presenters at the MEMS program at the TechXPOT include:

  • What’s Next for the MEMS Industry? ─ Jean-Christophe Eloy, CEO and founder, Yole Développement
  • New MEMS Opportunities from Piezoelectric Technology ─ David Horsley, professor, Mechanical & Aerospace Engineering, University of California Davis
  • Smart IT Systems and Development Protocols Enable Faster Time-to-Market in MEMS ─ Tomas Bauer, senior VP, sales/business development, Silex Microsystems
  • Waggle and the Future of Edge Computing and Smart Cities ─ Pete Beckman, co-director, Northwestern-Argonne Institute for Science and Engineering
  • Roll-up Implementation of Gesture Sensing and Voice Isolation Sensing Wall for Future Human-Machine Interface ─ James Sturm, professor, Electrical Engineering, Princeton University
  • Three Bit NFC Sensor Labels Based on a Flexible, Hybrid Printed CMOS TFT Process ─ Arvind Kamath, VP of Engineering, Thin Film Electronics

MSIG also invites members to attend the MEMS/NEMS Committee Meeting, including a Task Force on microfluidics, from 3:30-5:30 pm on July 13 at the San Francisco Marriott Marquis.

How low can we go?


July 11, 2017

By Ed Korczynski

In the advanced CMOS technology programs ongoing in the Belgium city of Leuven, imec works to extend the building-blocks of integrated circuits (IC). On the day before the opening of SEMICON West 2017, the invitation-only imec Technology Forum provided an update on the emerging opportunities in semiconductor technology and smart electronics systems. An Steegen, Executive VP Semiconductor Technology & Systems, provided the update on how small we can scale CMOS devices over the next 5-10 years. Taller finFETs will likely be used along with nano-wire FETs (NW-FET) by industry, and researchers see ways to cost-effectively combine both in future optimized System-on-Chips (SoC).

“Existing finFET technology can scale to the 5nm-node,” explained An Steegen at ITF 2017 in Antwerp, Belgium. “However, at the 3nm-node it looks like the nano-wire is comparable in performance to the finFET, but it has an additional advantage in that the nanowire is a better electro-statically controlled device so it enables gate-length scaling more than the finFET. So the contacted gate pitch (CGP) of a nano-wire can scale further than a finFET, because below ~40 nm CGP a finFET loses electro-static control which a nano-wire does not.”

While it is given that a nanowire has better electro-static control compared to a finFET, the basic trade-off is that of reduced drive current. The Figure shows that IMEC sees the possibility of System-Technology Co-Optimization (STCO) of future system-on-chip (SoC) designs using hybrid semiconductor technologies. imec’s basic process flow for NW-FETs starts with forming fins and so could be relatively easily integrated with finFETs for co-integrated hybrid CMOS.

System-Technology Co-Optimization (STCO) for future System-on-Chip (SoC) designs could integrate finFETs with Nano-Wire FETs (NW-FET) and Magnetic Random Access Memory (MRAM) for optimized performance. (Source: imec)

System-Technology Co-Optimization (STCO) for future System-on-Chip (SoC) designs could integrate finFETs with Nano-Wire FETs (NW-FET) and Magnetic Random Access Memory (MRAM) for optimized performance. (Source: imec)

“Today, this SoC is processed in one technology which means it’s sub-optimal for certain blocks on the SoC,” explained Steegen. “So imagine a future where you can choose the preferred technology for each block. I would choose finFETs for those blocks that need drive current, while I would choose nano-wire-FETs for those blocks that need more density and lower power. I would for example choose a magnetic RAM to replace my cache memory. I can optimize each sub-block for a preferred technology. Now I can do more, like sprinkle in low-energy devices like tunnel-FETs or spin-devices or 2D-materials as low-energy switches.”

Super-vias and Rutherails

Design-Technology Co-Optimization (DTCO) is imec’s term for new interconnect technologies to allow for simpler or more-compact designs. IDTCO process-scaling boosters are needed to stay with the pace of aggressive design rule targets. “We’re working on super-vias that connect more than one metal to the other and can jump a number of levels, and buried rails to support finFETs in standard-cell libraries,” explained Steegen during ITF2017.

Super-vias could be cobalt plugs that connect more than two metal levels within on-chip multi-level interconnects. The cobalt plugs would be nominally 20nm diameter and 105nm deep, and connected to a dual-damscene upper metal line. Low-k dielectric of k=2.55 uses thin silicon carbon nitride (SiCN) for definition between the damascene levels.

Ruthenium rails (Rutherails) would be buried in a front-end dielectric layer to provide electrical contacts below finFETs for 42nm CGP and 21nm MP needed for imec 3nm-Node (I3N) devices. Ruthenium rails 30nm deep and 10nm wide do not need complex barrier layers and should provide sufficient current flow for either finFETs or NW-FETs.

imec is also working on materials R&D to extend the performance of 3D-NAND. Steegen said,

“At imec we are working on improving the performance of that Flash device by introducing high-mobility channels, also by engineering the dielectric trapping layer with a barrier that can help improve the erase window and also the retention.”

Boston Semi Equipment (BSE), a global semiconductor test handler company, announced today it has received a follow on order for multiple Zeus gravity test handling systems for pressure MEMS. The order comes from a major manufacturer of tire pressure monitoring system sensors, which selected Zeus’ pressure MEMS solution for its high accuracy and throughput.

“The Zeus handler applies the pressure stimulus directly to the device while it is at the handler’s test site,” said Kevin Brennan, vice president of marketing for BSE. “This eliminates the need to hand off the package to a separate pressure unit for testing. The tool also reaches desired pressure set points faster, cycles through pressure levels in shorter times and offers a faster index time than other solutions. Combined, these advantages result in higher throughput for pressure MEMS devices, making Zeus an ideal solution.”

The Zeus is a tri-temperature handler that can be configured with up to eight test sites. Cold temperature testing is achieved using LN2 or a BSE-designed, two-stage chiller, the MR2. The Zeus offers the features and performance needed by today’s test cells at a more affordable price point.

At its annual Imec Technology Forum USA in San Francisco, imec today presented an electrically functional solution for the 5nm back-end-of-line (BEOL). The solution is a full dual-damascene module in combination with multi-patterning and multi-blocking. Scaling boosters and aggressive design rules pave the way to even smaller dimensions.

As R&D progresses towards the 5nm technology node, the tiny Cu wiring schemes in the chips’ BEOL are becoming more complex and compact. Shrinking the dimensions also reduces the wires cross-sectional area, driving up the resistance-capacitance product (RC) of the interconnect systems and thus increasing signal delay. To overcome the RC delay challenge and enable further improvements in interconnect performance, imec explores new materials, process modules and design solutions for future chip generations.

Dense-pitch blocks enabled by a dual damascene flow and multi-patterning. The pattern is etched into the low-k and metallized.

Dense-pitch blocks enabled by a dual damascene flow and multi-patterning. The pattern is etched into the low-k and metallized.

One viable option is to extend the Cu-based dual-damascene technology – the current workhorse process flow for interconnects – into the next technology nodes. Imec has demonstrated that the 5nm BEOL can be realized with a full dual-damascene module using multi-patterning solutions. With this flow, trenches are created with critical dimensions of 12nm at 16nm.  Metal-cuts (or blocks) perpendicular to the trenches are added in order to create electrically functional lines and then the trenches are filled with metal. Area scaling is further pushed through the introduction of fully self-aligned vias. Moreover, aggressive design rules are explored to better control the variability of the metal tip-to-tips (T2Ts).

Beyond 5nm, imec is exploring alternative metals that can potentially replace Cu as a conductor. Among the candidates identified, low-resistive Ruthenium (Ru) demonstrated great promise. The imec team has realized Ru nanowires in scaled dimensions, with 58nm2 cross-sectional area, exhibiting a low resistivity, robust wafer-level reliability, and oxidation resistance – eliminating the need for a diffusion barrier.

“The emergence of RC delay issues started several technology nodes ago, and has become increasingly more challenging at each node. Through innovations in materials and process schemes, new BEOL architectures and system/technology co-optimization, we can overcome this challenge as far as the 5nm node,” said Zsolt Tokei, imec’s director of the nano-interconnect program. “Imec and its partners have shown attainable options for high density area scaled logic blocks for future nodes, which will drive the supplier community for future needs.”

For the longer term, imec is investigating different options including but not limited to alternative metals, insertion of self-assembled monolayers or alternative signaling techniques such as low-energy spin-wave propagation in magnetic waveguides, exploiting the electron’s spin to transport the signal. For example, the researchers have experimentally shown that spin waves can travel over several micrometers, the distance required by short and medium interconnects in equivalent spintronic circuits.

Imec’s research into advanced logic scaling is performed in cooperation with imec’s key partners in its core CMOS programs including GlobalFoundries, Huawei, Intel, Micron, Qualcomm, Samsung, SK Hynix, Sony Semiconductor Solutions and TSMC.

Presto Engineering, Inc., an outsourced operations provider to semiconductor and Internet of Things (IoT) device manufacturers, announces a management expansion: Cedric Mayor has been named Chief Operating Officer (COO) and Martin Kingdon has been appointed VP Sales.

“We have experienced growing demand for IoT and related turnkey production & operations outsourcing,” said Michel Villemain, CEO, Presto Engineering. “Our expanded management team will complement our talented employee base to help meet this market demand and advance Presto Engineering into the next phase of innovation and growth.”

Mayor was previously the Chief Technology Officer for Presto Engineering. In his new role as COO, he will work with Presto’s Europe and Asia-based facilities to take customers’ new product releases from prototype to high-volume production, and through wafer procurement to finished goods. He has been with the company for more than seven years and has over a decade of experience in semiconductor design and manufacturing. A graduate of Ecole Centrale Marseille, France, Mayor has a Master’s degree in Physics and Electrical Engineering and holds several patents in chip design.

Kingdon has more than 20 years of experience in sales and marketing of semiconductor devices, IP, and test & manufacturing. Prior to joining Presto as VP Sales, Kingdon served as European sales director for the test and manufacturing services division of TT Electronics plc. Kingdon graduated from the University of York, UK, and holds a Master’s degree in Electronic Systems Engineering.

CMOS image sensor sales are on pace to reach a seventh straight record high this year and nothing ahead should stop this semiconductor product category from breaking more annual records through 2021 (Figure 1), according to IC Insights’ 2017 O-S-D Report—A Market Analysis and Forecast for Optoelectronics, Sensors/Actuators, and Discretes.

After rising 9% in 2017 to about $11.5 billion, worldwide CMOS image sensors sales are expected to increase by a compound annual growth rate (CAGR) of 8.7% to $15.9 billion in 2021 from the current record high of $10.5 billion set in 2016, based on the five-year forecast in the 360-page O-S-D Report, which covers more than 40 different product categories across optoelectronics, sensors and actuators, and discrete semiconductors.

Figure 1

Figure 1

After strong growth from the first wave of digital cameras and camera-equipped cellphones, image sensor sales leveled off in the second half of the last decade.  However, another round of strong growth has begun in CMOS image sensors for new embedded cameras and digital imaging applications in automotive, medical, machine vision, security, wearable systems, virtual and augmented reality applications, and user-recognition interfaces.

Competition among CMOS image sensor suppliers is heating up for new three-dimensional sensing capability using time-of-flight (ToF) technology and other techniques for 3D imaging and distance measurements.  ToF determines and senses the distance of faces, hand gestures, and other things by measuring the time it takes for light to bounce back to sensors from emitted light (often an infrared laser or LED).  CMOS technology has progressed to the point of supporting integration of ToF functions into small chip modules and potentially down to a single die.  Sony, Samsung, OmniVision, ON Semiconductor, STMicroelectronics, and others have rolled out and developed 3D image sensors. Infineon has also jumped into the image sensor arena with a 3D offering that is built in ToF-optimized CMOS technology.

Automotive systems are forecast to be the fastest growing application for CMOS image sensors, rising by a CAGR of 48% to $2.3 billion in 2021 or 14% of the market’s total sales that year, says the 2017 O-S-D Report.  CMOS image sensor sales for cameras in cellphones are forecast to grow by a CAGR of just 2% to $7.6 billion in 2021, or about 47% of the market total versus 67% in 2016 ($7.0 billion).  Smartphone applications are getting a lift from dual-camera systems that enable a new depth-of-field effect (known as “bokeh”), which focuses on close-in subjects while blurring backgrounds—similar to the capabilities of high-quality single-lens reflex cameras.

BY PETE SINGER, Editor-in-Chief

What if the automotive industry had achieved the incredible pace of innovation as the semiconductor industry during the last 52 years? A Rolls Royce would cost only $40, go around the world eight times on a gallon of gas, and have a top speed of 2.4 million miles per hour.

That point was made by Subi Kengeri speaking at The ConFab in May. Kengeri is vice president, CMOS Business Unit, at GlobalFoundries. He also noted that if one of today’s high performance graphics chips were produced using 1960 vs state-of-the-art “it would be the size of a football field.”

Clearly, no other industry can match the pace of innovation of the semiconductor industry. “The transistor count per square inch in 1965 was roughly 100. In 52 years, if you follow Moore’s Law of 2 years per innovation cycle, that gives 26 innovation cycles. That’s 100 millionX improvement (2X26),” Kengeri noted.

Of course, there has been plenty of innovation in the automotive industry. Interestingly, most of the exciting new innovations such as backup cameras, collision avoidance, navigation/ infotainment, self-parking, and anti-lock brakes are only possible because of semiconductor technology.

Kengeri said that Moore’s Law scaling will continue – “there’s no question about it,” he said – but there’s a growing need for new innovation to address the increasingly diverse array of semicon- ductor applications. These are driven by growth in mobile computing, development in IoT computing, the emergence of intelligent computing and augmented/virtual reality.

“Leading edge innovation will continue and all the leading manufacturers continue to invest, whether it is litho scaling in terms of EUV, or device archicture,” Kengeri said. “What is really important is how do we continue to innovate, how do we continue to get the value at competitive costs? Trying to get the scaling at any cost is not what is needed in the majority of the markets. It’s still okay at the very high end, for CPUs and servers, but in all markets, managing cost is really critical.”

“On top of all of that, we have to continue to deliver on time. Because of the complexity, things aren’t getting slower. We’re doing everything we can do continue to keep the same pace as we used to,” he added.

Kengeri said continued advances mean changing the way we think about innovation. It will require continued technical Innovation (materials and processes, device architecture and design-technology co-optimization), but – perhaps more importantly – business model innovation. This includes new thinking about long-term R&D focus/ investment, shared investments/learning/reuse, and consolidation and collaboration.

Industry experts answer questions about the new standard in a virtual roundtable.

In recent years, energy consumption has decreased due to several innovations that have helped to improve the energy efficiency of process tools and sub-fab equipment, but an increase in the number of processes and the growing complexity of processing at the current node has resulted in a spike in energy consumption in the fab. Approximately 43% of the energy consumed in the fab is due to the processing equipment and, of this, 20% is vacuum and abatement (8% overall).

A new standard from SEMI, E175, defines energy saving modes, which combined with the EtherCAT signaling standard, can help fabs save energy and other gas/utility costs when the tool is not processing and with no impact on subsequent wafer processing.

EtherCAT, based on industrial Ethernet, provides high- speed control and monitoring. It is the communication standard of choice for the latest semiconductor tool controllers to connect to sensors and actuators around the tool, including vacuum and abatement systems.

SEMI E175 defines how process tools communicate with sub-fab equipment, such as vacuum pumps and gas abatement systems, to reduce utility consumption at times when wafers are not being processed by the tool, and returning to full performance when the tool is again required to process wafers. It builds on SEMI E167, which defines communication between the fab host/ WIP controller and the process tools for the purpose of utility saving.

Collaboration between the E175 and EtherCAT groups has seen a harmonization of the communication standards to provide co-ordinated energy saving across devices in the fab.
We invited experts in this area to answer a few questions in a virtual roundtable. The participants are:

• GERALD SHELLEY, Senior Product Manager Communication and Control at Edwards, and the EtherCAT Chair Abatement / Roughing pump working groups, E175 task force.

• MIKE CZERNIAK, Environmental Solutions Business Development Manager at Edwardsm Co-Chair of SEMI International Standards E167 & E175, and campaigner for energy saving

• GINO CRISPIERI, Applied Materials – Past Co-chair of E175 (originally SEMATECH/ISMI, then independent consultant, prior to Applied Materials)

• MARTIN ROSTAN, Executive Director, EtherCAT Technology Group

Q: Please explain what drove the standards work on energy saving and the achievements to date.

SHELLEY: There is increased pressure on the industry to reduce energy and utility saving from both a cost and environmental standpoint. Subfab equipment is a major consumer of utilities, which is wasted when a tool is not in use. Different manufacturers have implemented energy saving solutions, with minimal direct connection to the tool. However, direct tool connection has emerged as the best way to maximize saving without any risk to wafer processing.

CZERNIAK: This work originated in the ISMI part of SEMATECH as a follow-on to generic work aimed at reducing the overall utilities footprint of modern fabs. In response to this and requests from customers, Edwards developed vacuum pumps and gas abatement systems that had energy-saving functionality. However, it soon became clear that the limitation to implementing such savings was the absence of standardised signalling between the process tool and sub-fab equipment.

CRISPIERI: A SEMATECH project around 2009 started to look into opportunities for saving energy in the semiconductor factories. At that time, suppliers of pumps and abatement systems already had started initiatives to provide their own solutions to the initiative. Since that time, the industry has adopted two new standards: SEMI E167 Specification for Equipment Energy Saving Mode Communication (between factory and semicon- ductor equipment) and SEMI E175 Specification for Subsystem Energy Saving Mode Communication (between semiconductor equipment and subsystems).

Q: Please describe how the energy saving task force was born and why you decided to get involved.

CRISPIERI: Back in 2009 while working for SEMATECH in Austin, Texas, prior to SEMATECH’s move the New York, Thomas Huang an assignee for GlobalFoundries to the EHS Program approached and asked me if I would be interested in helping him drive a standard for equipment suppliers to enable their equipment to save energy during idle times. Because of my previous experience working with equipment suppliers and developing standards for equipment and factory communication, I accepted to chair a task force to drive the equipment supplier’s new capability requirement into a standard. At first, we thought it would be an easy task and that everyone would jump to help create and approve the standard in a short amount of time because of its benefits. A two phase approach was defined to drive the standardization process and engage semiconductor and sub-fab equipment suppliers accordingly. It took almost three years to complete the Phase I (2013) and another three to complete the Phase II (2016) standards.

SHELLEY: The task force was an extension of E167 which previously defined the communication into the tool from the supervisory systems, however to achieve maximum benefit signalling to tool subsystems was key and the E175 task force was the result.

CZERNIAK: Following-on from the above, the ISMI working group became a SEMI Standards Task Force and began work at developing a standard, initially for Host to process tool (E167) and then from tool to sub-fab (E175), which I was co-chair for to ensure continuity and clear the signalling “roadblock”.

Q: How have suppliers collaborated on E175?

CRISPIERI: Compared with the suppliers who partic- ipated in SEMI E167 development, the suppliers involved in the development and approval of SEMI E175 were more committed to make it happen and helped drive the standardization process to conclusion much more efficiently. Edwards, AMAT, TEL, Hitachi- Kokusai and DAS-Europe regularly participated and provided inputs to standardize behavior and require- ments for their own equipment. We run into some difficulty getting aligned with other standard activities that were driven by SEMI’s EHS Committee because their changes affected our standardization process. I must note that the overall participation was excellent in particular from Edwards Vacuum and AMAT.

ROSTAN: Within the ETG Semiconductor Technical Working Group individual task groups already had multiple suppliers collaborating on the detail of the EtherCAT profiles for all devices, with technical support from the EtherCAT Technical Group. We were fortunate to have a delegate from Edwards in both the Semi E175 Task Force and key EtherCAT Task Groups to informally broker agreement between the teams.

SHELLEY: The suppliers were able to use their collective experience to work through a number of options to find the optimum way of controlling subfab equipment, tackling variability in wakeup time and control architec- tures between device types and equipment technology.

CZERNIAK: Suppliers, automation providers, tool OEMs and end-users have all collaborated to help develop a standard that works for everyone and aligns with earlier standards like S23.

Q: How was the EtherCAT collaboration beneficial to E175?

SHELLEY: By sharing information and understanding in real time we demonstrated the E175 concept is achievable using the favored protocol for new tool platforms and defined how it would be implemented. We co-operated to take both these standards to alignment in one simul- taneous step, saving considerable committee time on both sides that would have been necessary to resolve any divergence of the detail.

ROSTAN: By devising the implementation of E175 in parallel the EtherCAT Task Groups involved were able to feedback detailed technical proposals and show the E175 standard could be implemented relatively easily within the existing EtherCAT standards.

CRISPIERI: Participation and collaboration from the EtherCAT Working Group was critical to accelerate the implementation and adoption of the standard. Dry Contacts and EtherCAT communication protocol messages were added to two Related Information sections and included in the SEMI E175 standard at the time of its publication.

CZERNIAK: This enables a “richer” signalling environment than simple dry contacts (which are also supported) that enables even greater utility savings to be made.

Q: How has EtherCAT been able to support the require- ments of the tool and Semi E175?

CZERNIACK: By providing timing information; the longer the time the tool is inactive, the greater the savings possible.

ROSTAN: As the control network of choice for the latest semiconductor tools, EtherCAT has been ideally placed to support enhancements, such as the energy saving connectivity increasingly being requested by the fabs. In particular, it was good to see the Pump and Abatement Task Groups of the existing Semiconductor Technical Working Group formulate an E175 compliant solution within the timescales of the second release of the EtherCAT semiconductor device profiles. The EtherCAT Technology Group was also more than happy to support the publication of extracts of the EtherCAT standards being used as protocol examples in the Imple- mentation guidelines of the Semi E175 document.

SHELLEY: EtherCAT has the fast / deterministic connec- tivity and proven integration with tool controllers that allows E175 functionality to be easily added without any loss of performance. By including the requirements of Semi E175 in the EtherCAT standards, both equipment suppliers and tool vendors can establish energy saving communication quickly and easily.

CRISPIERI: The coordination between EtherCAT Working Group and the SEMI ESEC task force group was conducted by Mr. Gerald Shelley from Edwards Vacuum. With his help and leadership, we reached effortlessly agreement and acceptance for the required messages, parameters and values into the EtherCAT respective Pump and Abatement Profile documents. Havingworking usage scenarios and support from the EtherCAT Working Group has been invaluable.

Q: Why is energy saving important to the industry?

ROSTAN: In the industrial world, EtherCAT users are increasingly using our communication and control technologies to drive down energy consumption. The semiconductor industry operates in parts of the world where energy is a limited and expensive resource, whilst the latest wafer processing requires more power. The manufacturers are therefore in great need for energy saving opportunities, such as when the tool subsystems are not in use.

SHELLEY: The fabs are being squeezed by an increase in the complexity and number of processes involved in manufacturing a wafer, driving consumption up and increasing scarcity of energy supply. This is further compli- cated with associated cost and government pressure to “keep the lights on”.

CRISPIERI: It is not hard to see why is so important for device makers or the semiconductor manufacturing industry to adopt and require energy conservation capabilities in their factories. Energy consumed by many equipment components and support systems, such as pumps and abatement systems, never stop from running even when the equipment is idle and waiting for product to be delivered for processing. These components and support systems can save millions of dollars each year if their power consumption is reduced. This energy consumption reduction extends their life cycle thus reducing costs of maintenance and parts replacement. Any effort to reduce energy consumption helps lower costs and adds gains to not only the manufacturer but to those who have to generate the energy for consumption.

CZERNIACK: Cost reduction is always important, but electrical supply is limited in some areas.