Category Archives: MEMS

Two specialists in the field explain how to make self-healing chips.

BY FRANCKY CATTHOOR and GUIDO GROESENEKEN, imec, Leuven, Belgium

Transistor scaling has brought us a lot of benefits, but also a myriad of reliability issues. To extend the scaling path as far as possible, system archi- tects and technologists have to work together. They have to find solutions – e.g. at system level – to realize self-healing chips, chips that can detect or ‘feel’ where errors occur and that know how to deal with them or in a way ‘cure’ them. Only then will it be feasible to design systems in technologies with transistors scaled down to 5nm dimensions. Two specialists in the field explain how to make such self-healing chips: ‘system architect’ Francky Catthoor and ‘technologist’ Guido Groeseneken.

Until a few years ago, manufacturers of ICs in less- deeply scaled CMOS technology could sell electronics with a guaranteed lifetime. The chips inside were built with devices that all had the same average character- istics and would all age in a predictable way. A so-called guard-band approach guaranteed proper functioning of the circuits and chips: extra margins were added to the average characteristics of the transistors to ensure good functioning, also in extreme scenarios. Due to scaling and related reliability issues, these margins or guard bands have risen from 10% to much higher ranges. As a result, from 14nm on, the guard-band approach will become gradually untenable for systems that require some type of guarantees. Does this mean the premature end of scaling?

Making reliable systems with unreliable devices

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Groeseneken: “Maybe it means the end of the guard- band approach (FIGURE 1), but certainly not the end of scaling. In the past, the reliability of a system was for the larger part guaranteed by the technology engineers. But very soon this will no longer be possible, and we are reaching a point where we, technology engineers, have to work together with system architecture experts to design reliable systems using ‘unreliable’ devices. In our research group, we measure and try to under- stand reliability issues in scaled devices. In the 40nm technology, it is still possible to cope with the reliability issues of the devices and make a good system. But at 7nm, the unreliability of the devices risks to affect the whole system. And conventional design techniques can’t stop this from happening. New design paradigms are therefore urgently needed.”

Device aging becomes a very complex matter in scaled technologies. Groeseneken: “First of all, even with a fixed workload, the devices no longer degrade in a uniform way. Each individual device shows its own degradation level, so we have to start looking at the statistical distributions of degradation. And to make things worse, in a real system, the workload is not fixed. Just imagine a multimedia application in which the workload is dependent on the users’ instructions to the system. This workload dependence makes it very complex to predict the degradation of scaled devices in a system.”

Catthoor: “However, workload dependence doesn’t have to be negative. Ultimately, it even holds the key to the solution we are working on to make reliable systems with deeply scaled devices. Future systems will have distributed monitors that detect local errors in the system, an intelligent controller that gathers this infor- mation and decides what to do, and so-called knobs (actuators) that are regulated by the controller and fix the problem (FIGURE 2).”

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Groeseneken: “You could compare it with our body where the nervous system detects where the pain or infection is situated, sends the results to the brain which is the control organ that steers cells to fix the problem or make the body react to avoid the cause of the pain. We can indeed learn a lot from the way evolution has made the most sophisticated system ever: our body and the human brain.”

Monitoring the chip’s pain

The first requirement to make self-healing chips is to have a distributed monitor that can detect the chip’s pain very locally. Groeseneken: “There are various kinds of device variability that need to be monitored. First of all: the time-zero variability. This is the variation that exists in scaled devices, just after fabrication. Each transistor behaves slightly differently, even before they experience any kind of workload. This can be due to process variations during fabrication of the devices but is more and more dominated by so-called ‘intrinsic’ sources such as random dopant fluctuations or line edge roughness. This time-zero variability tends to become more important with deeply scaled devices. Secondly, there is a time-dependent variability: each device or transistor ages in a different way during the system’s operation. This can again be caused by differences in workload but also by intrinsic mechanisms such as random defect trapping in small devices. One has to make a distinction between functional reliability issues which affect the digital behavior of the device, and parametric reliability problems that affect the parameters of the device such as delay, power consumption, signal-to-noise ratio (SNR).”

The reliability of both the circuits and the whole system depends on the time-zero variability and the time- dependent variability of the devices. Catthoor: “And because these variations become more and more unpre- dictable, monitors are needed for both. A lot of research has been done on these monitors, especially in the academic world, and some are already in use today. For example, most chips today have functional monitors. In memories, where such error detection is rather easy to integrate and execute by doing a parity check. But even in arithmatic data paths, although less straightforward, functional monitors are developed and partly already in use today. Parametric monitors are less common for the moment. They are mainly used in highly-scaled high- performance applications.

An intelligent controller to heal the chip’s functional and parametric pain

The most important part of future self-healing chips is the controller. This chip’s brain will have to deal with both functional and parametric errors. Catthoor: “Both are linked to one another, but it’s important to fix the cause of the problem, not to focus on the consequences. If delay is the problem, then of course the functional behavior of the devices will be different too, but delay is the cause. On the other hand, if bit flipping is locally detected, than functional reliability mitigation has to be executed.”

Functional reliability mitigation is the healing of functional errors.

Catthoor: “Functional reliability mitigation is used in scaled memories (e.g. 90nm). Just think of error-correcting code (ECC) memories in which bit flip problems are detected and corrected. Because in memories the focus is on density and scaling, the related problems and solutions typically first pop up here. With further scaling of memory cells, the ECC becomes more complex, more distributed and eventually the cost will become too high. New techniques are needed.”

Together with top university EPFL (École polytechnique fédérale de Laussane) imec is working on workload- dependent functional mitigation techniques for memories and data paths. Catthoor: “There are three levels at which mitigation can be integrated. Circuit- level mitigation is very generic and can thus be used for every architecture style and application, but it implies an overhead in area and energy. The other extreme is mitigation at application level. This one is very specific but has to be redeveloped for every new application. Most companies don’t want to do this because of the high implied system design cost. In between, there is the mitigation at system-architecture level. This is not too specific and doesn’t create too much overhead. Imec, together with its academic partners, focuses on architecture-level mitigation and circuit-level mitigation (the latter only when fabrication cost can be kept low).

Also for parametric reliability issues, we are developing workload-dependent techniques. Again, our academic partners play a key role. Together with TU Delft we develop circuit-level mitigation techniques for SRAMs. And with NTU Athens we work on architecture-level mitigation techniques. Together we are developing a partly proactive system scenario-based controller. This controller prevents delay errors from propagating and causing damage at the system level. At the device level you can’t prevent these errors, but at the system level you can prevent them from doing harm. The collab- oration with research teams like the one of Guido Groeseneken is very important because they provide us with the data and the models for the failure mecha- nisms that have to be used in the mitigation techniques.”

Groeseneken: “The big advantage for imec of doing this work is that we have all expertise needed under one roof, which puts us in a quite unique position to do this research”.

A fortuneteller for self-healing chips

The ultimate goal of imec and its academic partners is to develop a fully proactive parametric reliability mitigation technique with distributed monitors, a control system and actuators, fully preventing the consequence of delay faults and potentially also of functional faults (FIGURES 3 and 4). Catthoor: “The secret to the solution lies in the workload variation of the system. Based on a deterministic predictor of the future, you determine future slack and use this to compensate for the delay error at peak load. Based on this info on the future, you change the scheduling order and the assignment of operations.” Groeseneken: “Only with this self-healing approach (the fully proactive approach), we will be able to scale down to 5nm technologies. Actually, I believe that this approach is also present in our human body. Our brain and body are not designed (by evolution) to constantly cope with peak loads, but they keep in mind that in the future better times will come and use this slack to cope with current peak loads.”

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Catthoor: “Workload-dependent modeling is essential to making reliable systems with scaled and unreliable devices. Imec brings together the knowledge on monitors, controllers and knobs that is being developed at the universities. We combine this with the knowledge from our technology people to work out simulations

and develop a fully proactive mitigation approach for future chips. The interactions we have with industrial partners allow us to develop an industry-relevant technique. I expect that by 2025, the industry will make true self-healing chips, and consumers will use truly reliable systems and applications. As in so many fields, the solution lies in collab- oration. In bringing the expertise of technologists and system architects together, and in combining the essential contributions of academic groups and research centers that bring the early concepts in reach of the industry and society.”

GUIDO GROESENEKEN is a scientific fellow at imec, covering research fields of advanced devices and reliability physics of sub-10nm CMOS technologies. He is also program director of the imec PhD program. FRANCKY CATTHOOR is an imec fellow and part-time full professor at the EE department of the KU Leuven.

Mergers & acquisitions in 2017


February 19, 2017

BY SEMI STAFF

At SEMI’s Industry Strategy Syposium this year, a merger’s and acquisitions panel, moderated by Robert Maire of Semiconductor Advisors, took a look at how the industry might look in the future. The panel consisted of:

• Patrick Ho, senior research analyst, Semiconductor Capital Equipment at Stifel Nicolaus
• John Ippolito, VP Corporate Development at MKS Instruments
• Israel Niv,former CEO of DCGS ystems
• Tom St.Dennis, chairman of the Board of FormFactor.

Will the huge deals of 2015 and 2016 continue?

Setting up the panel, Maire observed that 2015 and 2016 were huge in transaction size (over $100 billion announced in 2015), but while the values of the deals have jumped, the number of deals has remained fairly consistent over the past several years. Also, China has more significantly moved into the M&A market in 2015, in the range $4 to $5 billion.

It appears that M&A will continue, but not at the same pace as 2015 and 2016 due to increasing political, regulatory, and industry pushback. In the equipment space, while big deals such as Advantest and Verigy were possible in 2011, the current climate has seen big deals falter including Applied Materials and Tokyo Electron; Lam Research and KLA-Tencor; and Aixtron and Fujian Grand Chip.

However, Maire observed that the motivations for M&A continue; for instance, Intel needs to offset a declining PC market and ramp IoT, VR, and Cloud activity and will likely consider M&A as part of its approach. Similarly, opportunities for equipment companies to increase scale and size exist for process control companies and in the back-end segment where further consolidation appears necessary.

China becomes a player

China’s ambitions in M&A may have been complicated by recent events, but with a $150 billion investment fund there are likely more opportunities ahead. China has stated the intent to move from producing just 10 percent of its IC consumption to 70 percent in ten years and catching up technologically by 2030. While some see concerns given China’s investment and later pricing collapses in FPD, PV, and LED, others see China’s efforts to increase its indig- enous production of ICs as similar to what has happened as the industry spread from U.S. and Europe to Japan, Taiwan, and Korea.

The panel responded to questions from Maire, questions submitted from the audience, and live audience questions. Ho noted that big deals in semiconductor equipment appear, for the time being, to be difficult or over. However, there is still low-hanging fruit and smaller deals. There is a need to focus on scale and size because customers (IC manufac- turers) are bigger and fewer. For example, Form Factor’s combination with Cascade brought size and scale and enabled Form Factor to be more competitive.

The future for semiconductor equipment consolidation

Several questions revolved around where M&A would happen in the semiconductor equipment space. There was general consensus that M&A of any of the “big five” (not named, but likely ASML, Applied Materials, Lam Research, Tokyo Electron, and KLA-Tencor) were off the table in the short term due to both regulatory pressure and industry pushback given fears of overly strong supplier power. Niv thought there were opportunities for consolidation in the metrology and process control space. Ippolito thought there might be further consoli- dation opportunities in motion control. St. Dennis thought there were opportunities throughout the whole supply chain. He pointed out that the benefits of acquiring a good company were significant, including great talent (difficult and time consuming to develop organically), synergies in not just SG&A, but in technology and field organizations.

The role of private equity was raised. Ippolito noted that the private market and private equity have roles to play in consoli- dation opportunities, noting the success of Atlas Copco with Edwards Vacuum and Oerlikon Leybold as an example.

Several questions focused on China. Niv pointed out the industry needs to think about China similar to how they thought about Japan when Japan was emerging as an IC manufacturing power. Partnering with Japanese companies was an effective strategy for many and brought long-term success in that market. Ippolito thought that very large China deals might be off the table for a while, but smaller deals would likely go through. He noted that $150 billion (the China investment fund) is a lot of money and that tends to find a way forward.

Invensas Corporation, a wholly owned subsidiary of Tessera Holding Corporation (Nasdaq: TSRA), today announced that Teledyne DALSA, a Teledyne Technologies company, has signed a technology transfer and license agreement for Direct Bond Interconnect (DBI) technology. This agreement enables Teledyne DALSA to leverage Invensas’ revolutionary semiconductor wafer bonding and 3D interconnect technologies to deliver next-generation MEMS and image sensor solutions to customers in the automotive, IoT and consumer electronics markets. Teledyne DALSA is an international leader in high performance digital imaging and semiconductors and also one of the world’s foremost pure-play MEMS foundries.

“DBI technology is a key enabler for true 3D-integrated MEMS and image sensor solutions,” said Edwin Roks, president of Teledyne DALSA. “We are excited about the prospect of developing new products and providing new foundry services to our customers that utilize this technology. By working closely with Invensas, we will be able to move more quickly to deploy this capability efficiently and effectively.”

DBI technology is a low temperature hybrid wafer bonding solution that allows wafers to be bonded instantaneously with exceptionally fine pitch 3D electrical interconnect without requiring bond pressure. The technology is applicable to a wide range of semiconductor devices including MEMS, image sensors, RF Front Ends and stacked memory.

“We are pleased that Teledyne DALSA, a recognized leader in digital imaging products and MEMS solutions, has chosen our DBI technology to accelerate the development and commercialization of their next generation MEMS and image sensor products,” said Craig Mitchell, president of Invensas. “As device makers look for increasingly powerful semiconductor solutions in smaller packages, the need for cost-efficient, versatile 3D technologies is greater than ever before. We are confident that the superior performance and manufacturability of DBI technology will help Teledyne DALSA deliver tremendous value to their customers.”

By Paula Doe, SEMI

The explosive growth in demand for internet bandwidth and cloud computing capacity brings a new set of technology challenges and opportunities for the semiconductor supply chain. “Azure grew by 2X last year, but we can’t pull more performance out of the existing architecture,” noted Kushagra Vaid, Microsoft’s GM Hardware Engineering, Cloud & Enterprise, at last week’s Linley Cloud Hardware Conference in Santa Clara, Calif.  “We are at a junction point where we have to evolve the architecture of the last 20-30 years.” He stressed that the traditional way of designing chips and systems to optimize for particular workloads isn’t working anymore. “We can’t design for a workload so huge and diverse. It’s not clear what part of it runs on any one machine,” he noted. “How do you know what to optimize? Past benchmarks are completely irrelevant.”

Explosive growth in demand for data storage and processing in the cloud means change across the chip world. Source: Cisco VNI Global IP Traffic Forecast

Explosive growth in demand for data storage and processing in the cloud means change across the chip world. Source: Cisco VNI Global IP Traffic Forecast

Roadmap accelerates for networking chips 

Look for accelerating change in the networking chip market. Now that merchant chip suppliers have taken over 75 percent of the networking chip market from the proprietary suppliers, intense competition has meant astonishing improvements in reducing size and power, and two-year technology cycles, reported keynote speaker Andreas Bechtolsheim, Arista Networks Chief Development Officer and Chairman.  “The cloud is accelerating transitions, as the big data centers demand low cost,” he noted, explaining that new technologies no longer see gradual adoption through different applications. They have to start out cheaper to get any traction at all, but then ramp sharply to high volume in six months as high-volume data centers convert.

Data center networks expect transition to 400G to start in 2018. Source: MACOM

Data center networks expect transition to 400G to start in 2018. Source: MACOM

Bechtolsheim said the majority of the network link market will convert from 40G to 100G this year, and to 400G in 2019.  For 800G two years later, chip design will have to start this year. Luckily there’s a clear path for scaling on the chip side, from the current generation’s 28nm technology down to 16nm and 7nm.  But it could be a push for some of the ecosystem. “It’s pushing the packaging vendors, as 1.0mm solder balls are about the limit,” said Bechtolsheim. Companies are also forming a group to speed the standards process by making the 800G standard simply 2X that for 400G, as the 400B standard took eight years.

The 40G chips at the server layer are moving to pulse amplitude modulation (PAM4) to send and receive four signals at once, which will require moving to digital signal processing. Moving from analog bipolar to digital CMOS technology also enables significant scaling of chip size and power, with significant reduction in die area (~50 percent) and power (~40 percent) with 16nm FinFET compared to 28nm, noted MACOM’s Chris Collins, director of Marketing. The company plans 7nm 800G devices next year.

New layers and new types of memory

One likely change is new types and new placement for memory, for higher speeds, different levels of non-volatile cache, and designs and accelerator subsystems that limit the need to move large amounts of data back and forth over limited pipelines. “Data is doubling every 2-2.5 years, but DRAM bandwidth is only doubling every 5 years. It’s not keeping up,” noted Steven Woo, Rambus VP, Systems and Solutions. “We’ll see the addition of more tiers of memory over the next few years.” He suggested the emerging challenge would be what data to place where, using what technology, and how to move memory in general closer to the processing. Racks may become the basic unit instead of servers, so each can be optimized with more memory or more processors as needed.

Handling big data in the cloud means more opportunity for new memory technologies in an emerging tier between DRAM and solid state drives. Source: Rambus

Handling big data in the cloud means more opportunity for new memory technologies in an emerging tier between DRAM and solid state drives. Source: Rambus

Specialized accelerators speed particular applications

Another emerging solution is specialized chips or subsystem boards to accelerate particular types of cloud processing by taking over some jobs from the CPU cores, typically with different types of processors and lots of localized memory. Google and Wave Computing have their accelerator chips optimized for neural network processing. Mellanox offers offload adopter cards based on ASICs, FPGAs or RISC, with increasingly complex functions, claiming the potential to offload as much as of 80 percent of the overhead function of the CPU, to get a 2.7X increase in throughput per server.  MoSys proposes replacing conventional content addressable memory with a programmable search engine, based on an FPGA, a lot of SRAM, and software to search and route with different strategies for different types of applications to significantly increase speeds. Chelsio offers a module to handle encryption and decryption off the CPU without having to shuttle information back and forth to memory. Amazon even is renting FPGAs in its cloud so users can design their own accelerators for their particular workloads. But Microsoft’s Vaid remained skeptical that a proliferation of solutions for particular applications would be the best approach for the general use in the cloud.

300mm production and passive fiber alignment improve silicon photonics

Silicon photonics technology continues to make progress, and may find application in the market for very high bandwidth, mid to long haul transmission (30 meters to 80 kilometer), where spectral efficiency is the key driver, suggested Ted Letavic, Global Foundries, Senior Fellow. “4.5 and 5G communications will use photonics solutions similar to those needed in the data center, for volume that will drive down cost,” he noted. The foundry has now transferred its monolithic process to 300mm wafers, where the immersion lithography enables better overlay and line edge roughness, to reduce losses by 3X.  The company has an automated, passive solution to attach the optical fiber to the edge of the chip, pushing ribbons of multiple fibers into MEMS groves in the chip with an automated pick and place tool.  Letavic said the edge coupling process was in production for a telecommunications application.

Array of optical fibers are passively aligned by sliding into MEMS grooves at the side of the chip for 100Gpbs x 12 = 1.2Tb interconnect in flat form factor. Source: Global Foundries

Array of optical fibers are passively aligned by sliding into MEMS grooves at the side of the chip for 100Gpbs x 12 = 1.2Tb interconnect in flat form factor. Source: Global Foundries

For more information about SEMI, visit www.semi.org. SEMI also offers many events covering electronics manufacturing supply chain issues; for a full list of SEMI events, visit www.semi.org/en/events. SEMI is on LinkedIn and Twitter.

Avnet, Inc. (NYSE: AVT) today announced a collaboration with IBM (NYSE: IBM) to accelerate the time to market for IoT solutions. Led by its Technology Solutions team, Avnet will team with IBM to establish a Watson Internet-of-Things (IoT) Joint Lab within IBM’s newly opened global Watson IoT Center in Munich, Germany. Avnet will use this unique environment to showcase, demonstrate, develop and sell innovative IoT solutions.

“There is no limit to how IoT can be used to improve the world. We’re already seeing tremendous potential in new IoT applications that we’re developing with our customers, which range from protecting our children to preventing Legionnaires’ disease,” said Patrick Zammit, global president of Avnet Technology Solutions. “Avnet’s latest collaboration with IBM will accelerate our ability to provide customers with the foundation they need to rapidly develop marketable IoT solutions.”

At the lab, clients from around the world will be able to engage with Avnet and IBM IoT experts to create working prototypes and solutions that draw on the business benefits of Watson IoT and the power of cognitive computing. They can also enhance their IoT technical expertise through hands-on, on-the-job learning in the lab. Additionally, Avnet and IBM will engage with clients on joint business opportunities.

“With almost 20 billion connected devices in the world today, the Internet of Things is rapidly becoming the biggest source of data on the planet,” said Harriet Green, global head of Watson IoT. “With Watson cognitive computing, we have the opportunity to convert that data into meaningful insight to transform companies, industries and society. We are proud to partner with Avnet at our new Watson IoT HQ in Munich in a new joint lab where our best minds can work together side by side. With this agreement, we are pooling our shared deep history and expertise to deliver on the potential of the Internet of Things.”

The joint lab will help enable and inspire clients to imagine the “art of the possible” with IoT – creating new business models and exploring innovative approaches to industry challenges. One way Avnet will achieve this is through its newly acquired Premier Farnell business, which will use the lab to develop proof-of-concept electronic boards embedded with IBM’s Watson IoT and Bluemix services at the device level. The aim is to create a seamless experience for customers, allowing them to rapidly exploit new use cases for customers.

“Our focus is on helping businesses to bring their ideas to market – proof-of-concepts are a critical aspect of that,” said Richard Curtin, senior director of strategic alliances for Premier Farnell. “In the lab, we will develop new electronic boards with enhanced cloud and software capabilities, giving our customers a huge boost in building smarter IoT solutions that can positively impact our world.”

In addition to the lab, Avnet and IBM are actively collaborating to build IoT offerings to accelerate solution development with the IBM Watson IoT and IBM Bluemix platforms. This includes IoT starter kits from Avnet’s Electronics Marketingand Premier Farnell businesses. Clients will gain access to an extensive catalog of over 150 IBM Bluemix cloud services, including the IBM Watson IoT platform, DevOps, mobile and analytics services through the Avnet Cloud Marketplace. Additionally, clients will have access to in-depth technical training on the IBM Bluemix and IBM Watson IoT Platform through Avnet’s training and education services.

“It often takes 10 or more partners to create a single IoT solution, and it can be a challenging and time-consuming task to find the right partners,” said Mark Martin, Avnet’s vice president, IBM global supplier executive. “We’re taking the guesswork out of this for our partners by continually building a solid ecosystem of known companies they can work with to develop their IoT solutions. The new joint lab will be a key place for customers and partners to come together to collaborate with experts to quickly advance their solution design, and it is a vital resource that will be a key asset of the Technology Solutions portfolio over the long term.”

According to Yole Développement (Yole), the solid-state IC technologies applied to medical imaging applications including CCD, CIS, a-Si FPD, a-Se FPD, SiPM and now cMUT and pMUT are step by step penetrating the medical imaging industry. Yole’s analysts announced a US$350 million in 2016 with a comfortable 8.3% CAGR9 until 2022. In a US$35 billion medical imaging equipment market in 2016 with a 5.5% CAGR until 2022, solid-state IC players are clearly changing the medical imaging landscape by offering competitive disruptive technologies.

The “More than Moore” market research and strategy consulting company, Yole confirmed the growing interest of solid-state technologies in medical imaging applications: in this field, companies aim to reach challenges of minimally invasive solutions, safety of patient and early diagnostic, remote diagnostic and cost effectiveness through miniaturization, low power consumption and serial production.

Under this context, Yole released a new technology & market report entitled Solid-State Medical Imaging. Yole analyzes the medical imaging ecosystem and proposes a relevant overview of solid-state technologies and technological trends. From components to systems, Yole’s MedTech team reviews for each types of equipment the major companies in the supply chains from the sensors to the equipment. Solid-state disruptive solutions bring better performances for existing technologies and pave the way for new market opportunities. Yole’s MedTech analysts offer you today a snapshot of the solid-state IC technologies for medical imaging applications.

medical system

“For some technologies and applications, wafer volume growth is very significant,” explains Yole’s Activity Leader, Pierre Cambou. “For example, the development of SiPM7 in the field of molecular imaging will multiply in quantity by more than 6x over the next five years. This massive transformation from photomultiplier tubes to solid-state IC was derived from the need of multimodal equipment (PET/MRI10) but it’s going to have a direct consequence in the field of PET/CT11 and spread all the way to SPECT12 imaging.”

In the case of endoscopy the switch toward solid-state IC technologies started a decade ago and has completely transformed the landscape. The digitization process is almost complete. The new technological trend is now to move from CCD to CMOS image sensors offering higher image quality and miniaturization perspectives. Small-diameter fiberscope is the last endoscopy domain making the transition.

The medical imaging equipment market is led by 4 major players representing more than 75% of the market share. Indeed Siemens Healthineers, GE Healthcare, Philips Healthcare and Canon/Toshiba medical systems are manufacturing the high end imaging equipment including PET/MRI, PET/CT, SPECT and CT Scanners. But it is an evolving market and several players are focused on smaller systems and are leader on their market. Olympus, Fujifilm or Sirona are covering imaging markets with endoscopy and dental X-Ray equipment for example.

Medical industry and furthermore medical imaging applications require strong competences and knowledge to meet challenges of performances and patient safety from component to the system. Solid-state sensors are based on semiconductor technologies and processes with huge initial investment. Solid-state technologies impose a new paradigm in the supply chain from highly integrated companies to a horizontal network of specialized suppliers.

Yole’s report describes the major players’ position in the supply chain and how, among other, TowerJazz or Hamamatsu are working with Teledyne Dalsa, Perkin Elmer, or Zeiss, as well as large system manufacturers, to provide the best imaging solutions. It is worth noting that the medical imaging industry is also still consolidating through tremendous mergers and acquisitions. A total of US$35 billion of strategic acquisition has been made in the 2 last years at various level of the chain showing an exciting activity of the industry. Most of the companies are expanding field of competences through acquisitions:

Varex acquiring Perkin Elmer x-ray detector field, Canon and Toshiba Medical Systems to meet Canon growth strategy, as well as the US$25 billion acquisition of St. Jude Medical by Abbott.

“In our report, forecasts are paired with each modality’s technology and application overview, since some key players have made significant moves via solid-state technology,” highlights Dr Benjamin Roussel, Business Unit Manager, MedTech at Yole.

“The technologies and related use-cases are constantly evolving, providing space for innovators to differentiate themselves,” comments Jérôme Mouly, Technology & Market Analyst at Yole. And he adds: “Numerous new solid-state innovations are ready to enter the market.”

Intel Corporation yesterday announced plans to invest more than $7 billion to complete Fab 42, a project Intel had previously started and then left vacant. The high-volume factory is in Chandler, Ariz., and is targeted to use the 7 nanometer (nm) manufacturing process. The announcement was made by U.S. President Donald Trump and Intel CEO Brian Krzanich at the White House.

Intel Corporation on Tuesday, Feb. 8, 2017, announced plans to invest more than $7 billion to complete Fab 42. On completion, Fab 42 in Chandler, Ariz., is expected to be the most advanced semiconductor factory in the world. (Credit: Intel Corporation)

Intel Corporation on Tuesday, Feb. 8, 2017, announced plans to invest more than $7 billion to complete Fab 42. On completion, Fab 42 in Chandler, Ariz., is expected to be the most advanced semiconductor factory in the world. (Credit: Intel Corporation)

According to Intel’s official press release, the completion of Fab 42 in 3 to 4 years will directly create approximately 3,000 high-tech, high-wage Intel jobs for process engineers, equipment technicians, and facilities-support engineers and technicians who will work at the site. Combined with the indirect impact on businesses that will help support the factory’s operations, Fab 42 is expected to create more than 10,000 total long-term jobs in Arizona.

Mr. Trump said of the announcement: “The people of Arizona will be very happy. It’s a lot of jobs.”

There will be no incentives from the federal government for the Intel project, the White House said.

Context for the investment was outlined in an e-mail from Intel’s CEO to employees.

“Intel’s business continues to grow and investment in manufacturing capacity and R&D ensures that the pace of Moore’s law continues to march on, fueling technology innovations the world loves and depends on,” said Krzanich. “This factory will help the U.S. maintain its position as the global leader in the semiconductor industry.”

“Intel is a global manufacturing and technology company, yet we think of ourselves as a leading American innovation enterprise,” Krzanich added. “America has a unique combination of talent, a vibrant business environment and access to global markets, which has enabled U.S. companies like Intel to foster economic growth and innovation. Our factories support jobs — high-wage, high-tech manufacturing jobs that are the economic engines of the states where they are located.”

Intel is America’s largest high-technology capital expenditure investor ($5.1 billion in the U.S. 2015) and its third largest investor in global R&D ($12.1 billion in 20151). The majority of Intel’s manufacturing and R&D is in the United States. As a result, Intel employs more than 50,000 people in the United States, while directly supporting almost half a million other U.S. jobs across a range of industries, including semiconductor tooling, software, logistics, channels, OEMs and other manufacturers that incorporate our products into theirs.

The 7nm semiconductor manufacturing process targeted for Fab 42 will be the most advanced semiconductor process technology used in the world and represents the future of Moore’s Law. In 1968, Intel co-founder Gordon Moore predicted that computing power will become significantly more capable and yet cost less year after year.

The chips made on the 7nm process will power the most sophisticated computers, data centers, sensors and other high-tech devices, and enable things like artificial intelligence, more advanced cars and transportation services, breakthroughs in medical research and treatment, and more. These are areas that depend upon having the highest amount of computing power, access to the fastest networks, the most data storage, the smallest chip sizes, and other benefits that come from advancing Moore’s Law.

After the announcement, President Trump tweeted his thanks to Krzanich, calling the factory a great investment in jobs and innovation. In his email to employees, Krzanich said that he had chosen to announce the expansion at the White House to “level the global playing field and make U.S. manufacturing competitive worldwide through new regulatory standards and investment policies.”

“When we disagree, we don’t walk away,” he wrote. “We believe that we must be part of the conversation to voice our views on key issues such as immigration, H1B visas and other policies that are essential to innovation.”

During Mr. Trump’s presidential campaign, Krzanich had reportedly planned a Trump fundraiser event and then cancelled following numerous controversial statements from Trump regarding his proposed immigration policies. Intel has continued to be critical of the Trump administration’s immigration policies, joining over 100 other companies to file a legal brief challenging President Trump’s January 27 executive order which blocked entry of all refugees and immigrants from seven predominantly Muslim countries. Recently, Krzanich took to Twitter to criticize the order, voicing the company’s support of lawful immigration.

In 2012, Paul Otellini, then Intel’s CEO, made a similar promise about Fab 42 in the company of Obama, during a visit to Hillsboro, Oregon.

At the 2017 International Solid-State Circuits Conference in San Francisco (US), imec, the research and innovation hub in nanoelectronics and digital technologies, Holst Centre (set up by imec and TNO) and ROHM today presented an all-digital phase-locked loop (ADPLL) for Internet-of-Things (IoT) radio transceivers. Whereas a PLL is traditionally one of the major power consumers in a radio and can take up to 30% of the radio area, this new ADPLLfeatures a small area (0.18mm² in 40nm CMOS), low power consumption (0.67mW) and excellent performance. With all spurs lower than -56dBc and jitter below 2ps, which is beyond state-of-the-art digital PLLs, the new ADPLL shows an excellent robustness.

The intuitive IoT relies on tiny sensor nodes, invisibly embedded in our environment and wirelessly connected to the internet. As billions of IoT devices are set to be deployed, battery replacement becomes impossible and therefore, power consumption reduction, especially in wireless connectivity, is one of the leading concerns and challenges on low power radio design to address.

The PLL is the radio component for frequency synthesis and has traditionally been an analog component, although the research community has been working on digital alternatives. All-digital PLLs enable a smaller footprint, better control and testability, and improved scaling to advanced CMOS nodes. However, to-date, they have lagged behind in terms of performance, compared to analog solutions.wex`1wq2

Imec and ROHM’s all-digital PLL is an industry-first, combining record-low power consumption of only 0.67mW, with state-of-the-art performance. It supports all specifications of Bluetooth Low Energy (BLE) radios while significantly reducing cost and power consumption below any of today’s solutions. This divider less fractional-N digital PLL features a power-efficient spur-mitigation technique and a digital phase unwrap technique. Both approaches contribute to its excellent performance.

“We are pleased of our collaboration with ROHM to solve yet another challenge and deliver an ADPLL that adds to imec’s world-class record low power radio design portfolio. With this performance, this all-digital PLL has become a mature and superior alternative to the widespread analog PLLs,” commented Kathleen Philips, Program Director at imec/Holst Centre for Perceptive Systems for an Intuitive IoT. “The ADPLL is ready for industrial mass production and is currently being transferred to our industrial partners for product integration.”

At ISSCC2017, imec presents four papers addressing key building blocks for ultra-low power connectivity. The innovations serve power reduction in active, standby, sleep and transient operation of standard radios like Bluetooth, or newcomers in the sub-GHz communication space. 

“We are proud that we have developed the world-class low power ADPLL with imec. We develop the RF transceiver with this ADPLL and integrate ROHM’s ultra-low power sensors and micro controllers into the “sensor edge” module. We hope they will be leaders of IoT market.“ commented Isao Matsumoto, Director LSI Production Headquarters/LSI Product Development Headquarters at ROHM.

Today, at the 2017 International Solid-State Circuits Conference in San Francisco, imec, the world-leading research and innovation hub in nanoelectronics and digital technologies, Holst Centre (established by imec and TNO) and Cartamundi demonstrate a world first thin-film tag on plastic, compatible with the near field communication (NFC) Barcode protocol, a subset of ISO14443-A, which is available as standard in many commercial smartphones. The innovative NFC tag is manufactured in a thin-film transistor technology using indium gallium zinc oxide thin-film transistors (IGZO TFT) on a plastic substrate.

Plastic electronics offers an appealing vision of low-cost smart electronic devices in applications where silicon chips were never imagined before. Item-level identification, smart food packaging, brand protection and electronic paper are just a few examples. Such new applications will require a continuous supply of countless disposable devices.  Imec’s IGZO TFT technology uses large-area manufacturing processes that allow for inexpensive production in large quantities – an ideal technology for ubiquitous electronic devices in the Internet-of-Everything.

“Making a plastic electronics device compatible to the ISO standard originally designed for silicon CMOS was a very challenging research and development expedition” stated Kris Myny, senior researcher at imec. “Our collaboration with Cartamundi enabled us to develop a truly industry-relevant solution”.

The researchers developed a self-aligned TFT architecture with scaled devices optimized for low parasitic capacitance and high cut-off frequency. This allowed design of a clock division circuit to convert incoming 13.56 MHz carrier frequency into system clock of the plastic chip. Optimizations at logic gate and system level reduced power consumption down to 7.5mW, enabling readout by commercial smartphones. “These research innovations are the first major achievements of my ERC starting grant”, stated Kris Myny, principal investigator and holder of the prestigious ERC starting grant FLICs (716426).

 “This innovative hardware solution of plastic NFC tags opens up several new possibilities for NFC deployments,” stated Alexander Mityashin, program manager at imec. “Thanks to the nature of thin-film plastics, the new tags can be made much thinner and they are mechanically very robust. Moreover, the self-aligned IGZO TFT technology offers manufacturing of chips in large volumes and at low cost”.

The results were presented in paper 15.2 (“A Flexible ISO14443-A Compliant 7.5mW 128b Metal-Oxide NFC Barcode Tag with Direct Clock Division Circuit from 3.56MHz Carrier”, by K. Myny, Y.-C Lai, N. Papadopoulos, F. De Roose, M. Ameys, M. Willegems, S. Smout, S. Steudel, W. Dehaene, J. Genoe, Feb. 7, 2017).

Qualcomm Incorporated (NASDAQ:QCOM) and TDK Corporation (TOKYO:6762) today announced the completion of the previously announced joint venture under the name RF360 Holdings Singapore PTE. Ltd. (RF360 Holdings). The joint venture will enable Qualcomm’s RFFE Business Unit to deliver RF front-end (RFFE) modules and RF filters into fully integrated systems for mobile devices and fast-growing business segments, such as Internet of Things (IoT), automotive applications, connected computing, and more. The business being transferred constitutes a part of the TDK SAW Business Group activities.

“The ongoing expansion of mobile communication across multiple industries, and the unprecedented deployment of multi-carrier 4G technologies now reaching over sixty-five 3GPP frequency bands are driving manufacturers of wireless solutions to higher levels of miniaturization, integration and performance, especially for the RFFE in these devices,” said Cristiano Amon, executive vice president, Qualcomm Technologies, Inc., and president, QCT. “Further, 5G will increase the level of complexity even more. To that end, the ability to provide the ecosystem a truly complete solution is essential to enabling our customers to deliver mobile solutions at scale and on time.”

Together with RF360 Holdings, Qualcomm Technologies, Inc. (QTI) will be ideally positioned to design and supply products with end-to-end performance and global scale from the modem/transceiver all the way to the antenna in a fully integrated system.

RF360 Holdings will have a comprehensive set of filters and filter technologies, including surface acoustic wave (SAW), temperature-compensated surface acoustic wave (TC-SAW) and bulk acoustic wave (BAW), to support the wide range of frequency bands being deployed in networks across the globe. Moreover, RF360 Holdings will enable the delivery of RFFE modules from QTI that will include front-end components designed and developed by QTI. These components include CMOS, SOI and GaAs Power Amplifiers, a broad portfolio of Switches, Antenna Tuning, Low Noise Amplifiers (LNAs) and the industry’s leading Envelope Tracking solution.

Deepening collaboration between Qualcomm and TDK

In addition to operating the joint venture, Qualcomm and TDK will deepen their technological cooperation to cover a wide range of cutting-edge technologies for next-generation mobile communications, IoT and automotive applications.

“The deeper collaboration with Qualcomm fits perfectly into our growth strategy,” said Shigenao Ishiguro, President and CEO of TDK Corporation. “It is a further step that aims to open up new promising business opportunities for TDK, while strengthening the company’s innovativeness and thus competitiveness in such attractive future markets as sensors, MEMS, wireless charging and batteries. Our customers will clearly benefit from the resulting unique and comprehensive technologies and products portfolio.”