Category Archives: MEMS

Nowadays, the number of enforceable patents dedicated to miniaturized gas sensors is increasing worldwide, and several companies already stand out by their strong IP position. According Yole Développement’s analysts, the market size of gas sensors for consumer applications should grow from US$12 million in 2015 to more than US$95 million in 2021, with an upside of US$60 million if massive adoption of the innovative technologies is confirmed. With a 33% CAGR between 2014 and 2020, this segment is poised to experience the highest grow rate of the gas sensor market. All of these signs suggest the market start.

gas sensors

“In such emerging market, a strong IP position on miniaturized gas sensors is thus essential for companies to enter in this promising business,” comments Dr Fleur Thissandier, at KnowMade. KnowMade, a Yole Group’s company, has investigated the patent landscape of miniaturized gas sensors that could be used in consumer applications. The Technology Intelligence & IP Strategy consulting player identified more than 1,050 patented inventions worldwide up to August 2016 by more than 440 patent applicants.

KnowMade patent analysis entitled “Miniaturized Gas Sensors Patent Landscape Analysis” is now available and proposes an overview of the patent landscape, the IP profile of key players with a detailed ranking and an analysis of the relative strength of the top patent holders derived from their portfolio size, patent citation networks, countries of patent filings and current legal status of patents.

Today, mobile applications aggregate more and more sensors such as pressure sensors, inertial sensors…, and gas sensors could be the next sensors to be integrated in smart phones and/or wearables devices. Consumer applications are driving new gas sensors development to reduce cost, power consumption and size, especially with MEMS technologies. Such gas sensors are thus referred as “MEMS gas sensors”.

Technical and business requirements have so opened the door to innovation and added a new dimension to the global competition between gas sensor suppliers. Recent mergers and acquisitions reflect this thriving sector in structuration. For example, KnowMade’s analysts identified two main mergers:

•  AMS, Applied Sensors, NXP and Cambridge CMOS
•  TDK and Micronas

First patents on MEMS gas sensors was filed by Japanese companies in the early 1980’s by NEC. However patent activity really emerged between 1985 and 1994 with the apparition of European and American companies: Siemens, Fraunhofer, CEA, SRI, SPX.

Multiple start-ups have been created on the basis of CEA R&D results. A first wave of patent publications occurred between 1994 and 2003 induced by the emergence of IDMs (STMicroelectronics, Micronas, Honeywell, NGK, Bosch), American R&D labs (Caltech, University of Florida) and pure play gas sensor companies (CCMOS Sensors, Applied Sensor). Since then, patent publications have increased thanks to a high patent activity of Chinese universities and European players. The last 3 years newcomers started to file patents on MEMS gas sensors including AMS, Sensirion, APIX, NXP.

Currently, more than 760 patents are granted, mainly in China, Europe and USA, and more than 510 patent applications are pending, mainly in Europe, China and USA. KnowMade believes the significant ratio of patents in force and the high number of patent applications still in the pipeline worldwide is an indication of the technology maturity heralding a future ramp-up of the market of miniaturized gas sensors that could be used in consumer applications.

The most surprising result highlighted by KnowMade is probably the discrepancies between the market leaders including Honeywell, MSA, NGK and Figaro and the “patent” leaders such as Bosch, Siemens, Micronas and Cambridge CMOS. “The market is about to change”, says Dr Nicolas Baron, CEO & Founder at KnowMade. “New patents and related devices are targeting new application, which may disrupt the market.”

Scientists from the Semenov Institute of Chemical Physics of the Russian Academy of Sciences (ICP RAS) and the Moscow Institute of Physics and Technology (MIPT) have demonstrated that sensors based on binary metal oxide nanocomposites are sensitive enough to identify terrorist threats and detect environmental pollutants. The results of their study have been published in Sensors and Actuators B: Chemical.

This is a schematic representation of a binary sensor based on two metal oxides, with the nanoparticles of the catalytically active component (1) in yellow and the nanoparticles of the electron donor component (2) represented by the unshaded circles. Credit: the MIPT press office

This is a schematic representation of a binary sensor based on two metal oxides, with the nanoparticles of the catalytically active component (1) in yellow and the nanoparticles of the electron donor component (2) represented by the unshaded circles. Credit: the MIPT press office

Due to rapid industrial growth and the degradation of the environment, there is a growing need for the development of highly effective and selective sensors for pollutant detection. In addition, gas sensors could also be used to monitor potential terrorist threats.

“Choosing the right sensor composition can make a device at least ten times more effective and enable an exceptionally fast response, which is crucial for preventing terrorist attacks,” says Prof. Leonid Trakhtenberg of the Department of Molecular and Chemical Physics at MIPT, who is the leader of the research team and the head of the Laboratory of Functional Nanocomposites at ICP RAS.

According to the research findings, the most promising detection systems are binary metal oxide sensors, in which one component provides a high density of conductive electrons and another is a strong catalyst.

A mixed system of that kind has the two necessary components for effective gas detection, viz., an electron donor and a substance “accommodating” the reaction. An additional factor contributing to faster sensor response is the formation of chemisorption centers, i.e., the chemically active spots on the nanocrystals that facilitate gas molecule adsorption.

“We are planning further research into the possibilities for sensor design presented by the multicomponent metal oxide nanocomposites incorporating nanofibers. The development of new effective sensor compositions will be based on a reasonably balanced approach involving both the experimental tests and the advancement of our theoretical understanding of the sensing mechanisms,” comments Prof. Trakhtenberg.

A rather promising approach to the development of new gas detection systems is the use of “core-shell type” composite metal oxide nanofibers, where the “core” and the “shell” are composed of two different oxides.

At the Annual Conference on Magnetism and Magnetic Materials, imec, a research and innovation center in nano-electronics and digital technologies, presented breakthrough results supporting the building of technology-relevant majority gates based on spin waves. Reporting two industry-first achievements that are crucial for ultralow-power beyond-CMOS technology, imec demonstrated the generation and detection of spin waves in sub-micron-sized magnetic waveguides with wavelengths smaller than 350nm traveling over 10 micrometer in a 500nm wide waveguide, and proposed models for majority operation in nanoscale spin-wave structures.

Spintronic majority gate devices are promising alternatives to CMOS technology for certain applications, for example for arithmetic circuits. Majority gates are devices where the state of the output is determined by the majority of the inputs: if for example more than 50 percent of the inputs are true, the output has to return true. The output of the spin-wave majority gate is then based on the interference of multiple spin waves that propagate in a so-called spin-wave bus, or waveguide. When miniaturized down to the nanoscale, spin-wave majority gates could enable arithmetic circuits that are much more compact and energy-efficient than CMOS-based circuits.

Imec, in collaboration with the University of Kaiserslautern and Paris-Sud University, studied spin-wave propagation in a 10nm thick magnetic waveguide. Importantly, they found that spin waves, excited by an RF-driven antenna, can travel more than 10 micrometers in a 500nm wide waveguide. In a second experiment, they developed an all-electrical detection method for characterizing propagating spin waves in a magnetic bus. Spin waves with wavelengths as miniscule as 340nm could be detected—more than two times smaller than previously achieved industry results—paving the way towards scaled spin-wave conduits.

Through micromagnetic simulations, the operation of a nanoscaled fork-like spin-wave majority structure was successfully demonstrated. At these small dimensions, magneto-electric cells are used instead of antennas to excite and detect the spin waves. The proposed detection scheme allowed imec to capture the majority phase result of the spin-wave interference in a very short time frame, which was less than three nanoseconds.

“Spin-wave majority gates with micro-sized dimensions have previously been reported, however, for them to be CMOS-competitive, they must be scaled and handle waves with nanometer-sized wavelengths,” stated Iuliana Radu, distinguished member of technical staff coordinating Beyond CMOS at imec. “We propose here a method to scale these spin-wave devices into nanometer dimensions. Today’s exceptional results will open routes towards building spin-wave majority gates that promise to outperform CMOS-based logic technology in terms of power and area reduction.”

A tiny machine


October 31, 2016

In 1959 renowned physicist Richard Feynman, in his talk “Plenty of Room at the Bottom,” spoke of a future in which tiny machines could perform huge feats. Like many forward-looking concepts, his molecule and atom-sized world remained for years in the realm of science fiction.

And then, scientists and other creative thinkers began to realize Feynman’s nanotechnological visions.

In the spirit of Feynman’s insight, and in response to the challenges he issued as a way to inspire scientific and engineering creativity, electrical and computer engineers at UC Santa Barbara have developed a design for a functional nanoscale computing device. The concept involves a dense, three-dimensional circuit operating on an unconventional type of logic that could, theoretically, be packed into a block no bigger than 50 nanometers on any side.

“Novel computing paradigms are needed to keep up with the demand for faster, smaller and more energy-efficient devices,” said Gina Adam, postdoctoral researcher at UCSB’s Department of Computer Science and lead author of the paper “Optimized stateful material implication logic for three dimensional data manipulation,” published in the journal Nano Research. “In a regular computer, data processing and memory storage are separated, which slows down computation. Processing data directly inside a three-dimensional memory structure would allow more data to be stored and processed much faster.”

While efforts to shrink computing devices have been ongoing for decades — in fact, Feynman’s challenges as he presented them in his 1959 talk have been met — scientists and engineers continue to carve out room at the bottom for even more advanced nanotechnology. A nanoscale 8-bit adder operating in 50-by-50-by-50 nanometer dimension, put forth as part of the current Feynman Grand Prize challenge by the Foresight Institute, has not yet been achieved. However, the continuing development and fabrication of progressively smaller components is bringing this virus-sized computing device closer to reality, said Dmitri Strukov, a UCSB professor of computer science.

“Our contribution is that we improved the specific features of that logic and designed it so it could be built in three dimensions,” he said.

Key to this development is the use of a logic system called material implication logic combined with memristors — circuit elements whose resistance depends on the most recent charges and the directions of those currents that have flowed through them. Unlike the conventional computing logic and circuitry found in our present computers and other devices, in this form of computing, logic operation and information storage happen simultaneously and locally. This greatly reduces the need for components and space typically used to perform logic operations and to move data back and forth between operation and memory storage. The result of the computation is immediately stored in a memory element, which prevents data loss in the event of power outages — a critical function in autonomous systems such as robotics.

In addition, the researchers reconfigured the traditionally two-dimensional architecture of the memristor into a three-dimensional block, which could then be stacked and packed into the space required to meet the Feynman Grand Prize Challenge.

“Previous groups show that individual blocks can be scaled to very small dimensions, let’s say 10-by-10 nanometers,” said Strukov, who worked at technology company Hewlett-Packard’s labs when they ramped up development of memristors and material implication logic. By applying those results to his group’s developments, he said, the challenge could easily be met.

The tiny memristors are being heavily researched in academia and in industry for their promising uses in memory storage and neuromorphic computing. While implementations of material implication logic are rather exotic and not yet mainstream, uses for it could pop up any time, particularly in energy scarce systems such as robotics and medical implants.

“Since this technology is still new, more research is needed to increase its reliability and lifetime and to demonstrate large scale three-dimensional circuits tightly packed in tens or hundreds of layers,” Adam said.

The 62nd annual IEDM will be held in San Francisco December 3 – 7, 2016.

For more than six decades, the annual IEEE International Electron Devices Meeting (IEDM) has been the world’s largest and most influential forum for technologists to unveil breakthroughs in transistors and related micro/nanoelectronics devices.

That tradition continues this year with a few new twists, including a supplier exhibition and a later paper- submission deadline (August 10) of a final, four-page paper. Accepted papers will appear in the proceedings without any changes. This streamlined process will ensure that even as the pace of innovation in electronics quickens, IEDM remains the place to learn about the latest and most important developments.

The 62nd annual IEDM will be held in San Francisco December 3 – 7, 2016, beginning with a weekend program of 90-minute tutorials and all-day Short Courses taught by industry leaders and world experts in their respective technical disciplines. These weekend events will precede a technical program of some 220 papers and a rich offering of other events including thought-provoking plenary talks, spirited evening panels, special focus sessions on topics of greatinterest,IEEE awards and an event for entrepreneurs sponsored by IEDM and IEEE Women in Engineering.

“The industry is moving forward at an accelerated pace to match the increasing complexity of today’s world, and a later submission deadline enables us to shorten the time between when results are achieved in the lab and when they are presented at the IEDM,” said Dr. Martin Giles, IEDM 2016 Publicity Chair, Intel Fellow, and Director of Transistor Technology Variation in Intel’s Technology and Manufacturing Group.

Tibor Grasser, IEDM 2016 Exhibits Chair, IEEE Fellow and Head of the Institute for Microelectronics at TU Wien, added, “We have decided to have a supplier exhibition in conjunction with the technical program this year, as an added way to provide attendees with the knowledge and information they need to advance the state-of-the-art.”

Here are some of the noteworthy events that will take place at this year’s IEDM:

Special Focus Sessions

• Wearable Electronics and Internet of Things (IoT) – Wearable technology offers great promise for communica- tions, fitness tracking, health monitoring, speech therapy, elder care/assisted living and many other applications. This Special Focus Session has been organized to benchmark wearable electronics technologies, to address applications with comprehensive system demonstrations, and to learn indus- trial perspectives about the gaps, challenges and opportu- nities for wider uses of wearable and IoT technologies. Papers on flexible/stretchable electronics, MEMs, display devices, sensors, printed electronics, organic devices and 2-D material devices enabling wearables/IoT devices also will be featured.

• Quantum Computing – As traditional CMOS scaling enters the post-Moore’s Law era, quantum computing has emerged as a possible candidate for further device scaling because it exploits the laws of quantum physics and may make much more powerful computers possible. This Special Focus Session will explore relevant semiconductor-related fabri- cation issues and will brainstorm R&D directions for new materials, devices, circuits, and manufacturing approaches for the scalable integration of a large number of qubits with CMOS technology, operating at cryogenic temperatures for the realization of quantum computers.

• System-Level Impact of Power Devices – While there are forums that serve circuit experts for the exchange of ideas and the reporting of breakthroughs, there hasn’t been a suitable forum for bringing device and circuit experts together to consider impacts at the system level, even though that would be fruitful due to the interactions of circuits and devices. IEDM aims to serve as the forum for their dialogue, and so this Special Focus Session has been organized. Papers are expected to explore the system-level impact of power devices, and also to describe various types of power devices targeting the full range of power/power conversion applications such as hybrid vehicles, utility and grid control, computing/telecom power supplies, motor drives, and wireless power transfer.
• Ultra-High-Speed Electronics – There have been many advances and breakthroughs in ultra-high-speed electronics for communications, security and imaging applications, but technology gaps continue to prevent spectrum above milli- meter-wave frequencies from being fully used. This Special Focus Session has been organized to discuss, showcase and benchmark advanced ultra-high speed devices and circuits based on high-electron-mobility transistors (HEMTs), hetero- junction bipolar transistors (HBTs) and conventional CMOS devices; high-speed interconnect; antennas for ultra-high- speed systems; ultra-high-frequency oscillators; and to discuss other possible applications.

90-Minute Tutorials – Saturday, Dec. 3

A program of 90-minute tutorial sessions on emerging technologies will be presented by experts in the fields, to bridge the gap between textbook-level knowledge and leading-edge current research. Advance regis- tration is recommended.

• The Struggle to Keep Scaling BEOL, and What We Can Do Next, Dr. Rod Augur, Distinguished Member of the Technical Staff, GlobalFoundries – Looking ahead, it’s the interconnect that threatens further cost-effective scaling. The tutorial will cover challenges and trade-offs in back- end-of-the-line(BEOL)scaling,andwillevaluateemerging devices from a scaled-BEOL viewpoint.

• Electronic Circuits and Architectures for Neuro- morphic Computing Platforms, Prof. Giacomo Indiveri, Univ. of Zurich and ETH Zurich – This tutorial will cover the principles and origins of neuromorphic (i.e., brain-inspired) engineering, examples of neuromorphic circuits, how neural network architectures can be used to build large-scale multi-core neuromorphic processors, and some specific application areas well-suited for neuromorphic computing technologies.

• Physical Characterization of Advanced Devices, Prof. Robert Wallace, Univ. Texas at Dallas – This tutorial will cover the hardware, physics, and chemistry that enable modern physical characterization of novel electronic materials, and will explore how these techniques can shed light on electronic materials research and development, and on the resultant devices. In addition to introducing examples of novel electronic materials for device applications, example techniques discussed will include high-resolution electron microscopy, scanning tunneling microscopy and spectroscopy, dynamic x-ray photoelectron spectroscopy, and ion mass spectrometry. The detection limits of these techniques and how they relate to device behavior also will be discussed.

• Present and Future of FEOL Reliability—from Dielectric Trap Properties to Reliable Circuit Operation, Dr. Ben Kaczer, Principal Scientist, Imec – This tutorial will introduce the main degradation mechanisms occurring in present-day CMOS. The reliability of novel devices (SiGe, IIIV, gate-all-around nanowires, junctionless FETs, tunnel FETs), of deeply-scaled devices, and of circuits (e.g., “reliability-aware” designs) will be covered in detail. The tutorial will give attendees an overview and background in this area sufficient to allow them to follow and participate in any discussion on reliability in general, and on front-end- of-the-line (FEOL) reliability in particular.

• Spinelectronics: From Basic Phenomena to Magneto- resistive Memory (MRAM) Applications, Dr. Bernard Dieny, Chief Scientist, Spintec CEA — This tutorial will cover spintronics phenomena, magnetic tunnel junctions (growth, magnetic and transport properties), field-written MRAM (toggle and thermally assisted MRAM), STT-MRAM (principle and status of development), 3-terminal MRAM andinnovativearchitecturesthatbenefitfromthesehigh- endurance non-volatile memories.

• Technologies for IoT and Wearable Applications, Including Advances in Cost-Effective and Reliable Embedded Non-Volatile Memories, Dr. Ali Keshavarzi, Vice President of R&D, Cypress Semiconductor — This tutorial will coverarangeoftechnologyopportunitiesforIoTandwearable applications, including embedded non-volatile memories (eNVM), IPs and integrated solutions based on charge-trap memory technologies such as SONOS for low power (LP) and ultra-low-power (ULP) for advanced technology nodes. Technologies will be described for various integrated IoT, wearableandenergy-harvestingsystemsusingprogrammable systems-on-chips (SoCs) with digital and analog capabilities, along with low-energy Bluetooth radio, WiFi radio, solar cells, sensors, actuators, and power management ICs. Advanced small form-factor packaging technologies useful for system integration also will be described.

Short Courses – Sunday, Dec. 4

The Short Courses provide the opportunity to learn about important areas and developments, and to benefit from direct contact with world experts. Advance regis- tration is recommended.

1. Technology Options at the 5-Nanometer Node, organized by An Steegen and Dan Mocuta of Imec (Sr. Vice President of Technology Development/Director of Logic Device and Integration, respectively) – This course will describe the complex technological challenges at the 5nm node and explore innovative potential solutions. It begins with an in-depth discussion of patterning strategies being pursued to print critical features. Then, a pair of lectures will provide an overview of current transistor technologies and their relative strengths/ weaknesses in the context of various applications such as mobility, data centers and IoT. Strategies for effective mitigation of performance-limiting parasitic resistance and capacitance will be discussed, and advanced interconnect technologies including post- copper materials options for BEOL and MEOL appli- cations will be addressed. Lastly, metrology challenges for in-line and end-of-line process technologies will be discussed. The intent of the course is to provide a thorough understanding in process technology targets at the 5nm node and their potential solutions. Attendees will have the opportunity to learn about advanced technology options that are being actively pursued in the industry from leading technologists.

The course consists of lectures from six distinguished speakers:

• Nano Patterning Challenges at the 5nm Node, Akihisa Sekiguchi, VP & Deputy GM, SPE Marketing and Process Development Division, Tokyo Electron, Japan

• Novel Channel Materials for High-Performance and Low-Power CMOS, Nadine Collaert, Distinguished Member of the Technical Staff, imec, Belgium

• Transistor Options & Challenges for 5nm Technology, Aaron Thean, Professor of Electrical & Computer Engineering, National University of Singapore

• Low Resistance Contacts to Enable 5nm Node Technology: Patterning, Etch, Clean, Metallization and Device Performance, Reza Arghavani, Managing Director, Lam Research, USA

• Parasitic R and C Mitigation Options for BEOL and MOL in N5 Technology, Theodorus Standaert, Sr. Engineering Mgr., Manager, Process Integration, IBM, USA

• Metrology Challenges for 5nm Technology, Ofer Adan, Technologist and Global Product Manager, Member of the Technical Staff, Applied Materials, Israel

2. Design/Technology Enablers for Computing Applications, organized by John Chen, Vice President of Technology and Foundry Management, NVIDIA – This course will describe how various design techniques and process technologies can enable computing applications, beginning with the relative advantages and disadvantages of processors such as CPU, GPU and FPGA with regard to today’s high data demands. It then will cover how memory becomes a bottleneck, and will discuss various emerging memory technol- ogies to mitigate the problem. Because managing power dissipation has become critical, it also will offer a broad perspective on power efficiency in computing and how interconnect plays a pivotal role in both performance and energy efficiency. Finally, 2.5-D and 3-D advanced packaging technology is discussed for system integration.

The course consists of lectures from five distinguished speakers:

• The Rise of Massively Parallel Processing: Why the Demands of Big Data and Power Efficiency are Changing the Computing Landscape, Liam Madden, Corporate VP, Hardware & Systems Development, Xilinx, USA

• Breaking the Memory Bottleneck in Computing Applications with Emerging Memory Technologies: a Design and Technology Perspective, Gabriel Molas, PhD Engineer, Leti, France

• Power Management with Integrated Power Devices… and how GaN Changes the Story, Alberto Doronzo, Power System/Apps Engineer, Texas Instruments, USA

• Interconnect Challenges for Future Computing, William J. Dally, Chief Scientist and Sr. VP of Research, NVIDIA, and Stanford Professor, USA

• Advanced Packaging Technologies for System Integration, Douglas Yu, Sr. Director, TSMC, Taiwan

BY PETE SINGER, Editor-in-Chief

I’m delighted to announce that The ConFab, our premier semiconductor manufacturing conference and networking event, will be held at the iconic Hotel del Coronado in San Diego on May 14-17, 2017. For more than 12 years, The ConFab, an invitation-only executive conference, has been the destination for key industry influencers and decision-makers to connect and collab- orate on critical issues.

The ConFab is the best place to seek a deeper under- standing on these and other important issues, offering a unique blend of market insights, technology forecasts and strategic assessments of the challenges and opportu- nities facing semiconductor manufacturers. In changing times, it’s critical for people to get together in a relaxed setting, learn what’s new, connect with old friends, make new acquaintances and find new business opportunities, and that’s what The ConFab is all about.

I’m also pleased to announce the addition of David J. Mount to The ConFab team as marketing and business development manager. Mount has a rich history in the semiconductor manufacturing equipment business and will be instrumental in guiding continued growth, and expanding into new high growth areas.

Mainstream semiconductor technology will remain the central focus of The ConFab, and the conference will be expanded with additional speakers, panelists, and VIP attendees who will participate from other fast growing and emerging areas. These include biomedical, automotive, IoT, MEMS, LEDs, displays, thin film batteries, photonics and advanced packaging. From both the device maker and the equipment supplier perspective, The ConFab 2017 is a must-attend networking conference for business leaders.

The ConFab conference program is guided by a stellar Advisory Board, with high level representatives from GlobalFoundries, Texas Instruments, TSMC, Cisco, Samsung, Intel, Lam Research, KLA-Tencor, ASE, NVIDIA, the Fab Owners Association and elsewhere.

Details on the invitation-only conference are at: www. theconfab.com. For sponsorship inquiries, contact Kerry Hoffman at [email protected]. For those interested in attending as a guest or qualifying as a VIP, contact Sally Bixby at [email protected].

Robert Wolkow is no stranger to mastering the ultra-small and the ultra-fast. A pioneer in atomic-scale science with a Guinness World Record to boot (for a needle with a single atom at the point), Wolkow’s team, together with collaborators at the Max Plank Institute in Hamburg, have just released findings that detail how to create atomic switches for electricity, many times smaller than what is currently used.

Robert Wolkow, University of Alberta physics professor and the Principal Research Officer at Canada's National Institute for Nanotechnology, has developed a technique to switch a single-atom channel. Credit: John Ulan

Robert Wolkow, University of Alberta physics professor and the Principal Research Officer at Canada’s National Institute for Nanotechnology, has developed a technique to switch a single-atom channel. Credit: John Ulan

What does it all mean? With applications for practical systems like silicon semi-conductor electronics, it means smaller, more efficient, more energy-conserving computers, as just one example of the technology revolution that is unfolding right before our very eyes (if you can squint that hard).

“This is the first time anyone’s seen a switching of a single-atom channel,” explains Wolkow, a physics professor at the University of Alberta and the Principal Research Officer at Canada’s National Institute for Nanotechnology. “You’ve heard of a transistor–a switch for electricity–well, our switches are almost a hundred times smaller than the smallest on the market today.”

Today’s tiniest transistors operate at the 14 nanometer level, which still represents thousands of atoms. Wolkow’s and his team at the University of Alberta, NINT, and his spinoff QSi, have worked the technology down to just a few atoms. Since computers are simply a composition of many on/off switches, the findings point the way not only to ultra-efficient general purpose computing but also to a new path to quantum computing.

“We’re using this technology to make ultra-green, energy-conserving general purpose computers but also to further the development of quantum computers. We are building the most energy conserving electronics ever, consuming about a thousand times less power than today’s electronics.”

While the new tech is small, the potential societal, economic, and environmental impact of Wolkow’s discovery is very large. Today, our electronics consume several percent of the world’s electricity. As the size of the energy footprint of the digital economy increases, material and energy conservation is becoming increasingly important.

Wolkow says there are surprising benefits to being smaller, both for normal computers, and, for quantum computers too. “Quantum systems are characterized by their delicate hold on information. They’re ever so easily perturbed. Interestingly though, the smaller the system gets, the fewer upsets.” Therefore, Wolkow explains, you can create a system that is simultaneously amazingly small, using less material and churning through less energy, while holding onto information just right.

When the new technology is fully developed, it will lead to not only a smaller energy footprint but also more affordable systems for consumers. “It’s kind of amazing when everything comes together,” says Wolkow.

Wolkow is one of the few people in the world talking about atom-scale manufacturing and believes we are witnessing the beginning of the revolution to come. He and his team have been working with large-scale industry leader Lockheed Martin as the entry point to the market.

“It’s something you don’t even hear about yet, but atom-scale manufacturing is going to be world-changing. People think it’s not quite doable but, but we’re already making things out of atoms routinely. We aren’t doing it just because. We are doing it because the things we can make have ever more desirable properties. They’re not just smaller. They’re different and better. This is just the beginning of what will be at least a century of developments in atom-scale manufacturing, and it will be transformational.”

“Time Resolved Single Dopant Charge Dynamics in Silicon” appeared in the October 26 edition of Nature Communications, an open-access journal in the group of Nature, world-leading scientific publications.

Researchers have developed a prototype of a next-generation lithium-sulphur battery which takes its inspiration in part from the cells lining the human intestine. The batteries, if commercially developed, would have five times the energy density of the lithium-ion batteries used in smartphones and other electronics.

This is a computer visualization of villi-like battery material. Credit: Teng Zhao

This is a computer visualization of villi-like battery material. Credit: Teng Zhao

The new design, by researchers from the University of Cambridge, overcomes one of the key technical problems hindering the commercial development of lithium-sulphur batteries, by preventing the degradation of the battery caused by the loss of material within it. The results are reported in the journal Advanced Functional Materials.

Working with collaborators at the Beijing Institute of Technology, the Cambridge researchers based in Dr Vasant Kumar’s team in the Department of Materials Science and Metallurgy developed and tested a lightweight nanostructured material which resembles villi, the finger-like protrusions which line the small intestine. In the human body, villi are used to absorb the products of digestion and increase the surface area over which this process can take place.

In the new lithium-sulphur battery, a layer of material with a villi-like structure, made from tiny zinc oxide wires, is placed on the surface of one of the battery’s electrodes. This can trap fragments of the active material when they break off, keeping them electrochemically accessible and allowing the material to be reused.

“It’s a tiny thing, this layer, but it’s important,” said study co-author Dr Paul Coxon from Cambridge’s Department of Materials Science and Metallurgy. “This gets us a long way through the bottleneck which is preventing the development of better batteries.”

A typical lithium-ion battery is made of three separate components: an anode (negative electrode), a cathode (positive electrode) and an electrolyte in the middle. The most common materials for the anode and cathode are graphite and lithium cobalt oxide respectively, which both have layered structures. Positively-charged lithium ions move back and forth from the cathode, through the electrolyte and into the anode.

The crystal structure of the electrode materials determines how much energy can be squeezed into the battery. For example, due to the atomic structure of carbon, each carbon atom can take on six lithium ions, limiting the maximum capacity of the battery.

Sulphur and lithium react differently, via a multi-electron transfer mechanism meaning that elemental sulphur can offer a much higher theoretical capacity, resulting in a lithium-sulphur battery with much higher energy density. However, when the battery discharges, the lithium and sulphur interact and the ring-like sulphur molecules transform into chain-like structures, known as a poly-sulphides. As the battery undergoes several charge-discharge cycles, bits of the poly-sulphide can go into the electrolyte, so that over time the battery gradually loses active material.

The Cambridge researchers have created a functional layer which lies on top of the cathode and fixes the active material to a conductive framework so the active material can be reused. The layer is made up of tiny, one-dimensional zinc oxide nanowires grown on a scaffold. The concept was trialled using commercially-available nickel foam for support. After successful results, the foam was replaced by a lightweight carbon fibre mat to reduce the battery’s overall weight.

“Changing from stiff nickel foam to flexible carbon fibre mat makes the layer mimic the way small intestine works even further,” said study co-author Dr Yingjun Liu.

This functional layer, like the intestinal villi it resembles, has a very high surface area. The material has a very strong chemical bond with the poly-sulphides, allowing the active material to be used for longer, greatly increasing the lifespan of the battery.

“This is the first time a chemically functional layer with a well-organised nano-architecture has been proposed to trap and reuse the dissolved active materials during battery charging and discharging,” said the study’s lead author Teng Zhao, a PhD student from the Department of Materials Science & Metallurgy. “By taking our inspiration from the natural world, we were able to come up with a solution that we hope will accelerate the development of next-generation batteries.”

For the time being, the device is a proof of principle, so commercially-available lithium-sulphur batteries are still some years away. Additionally, while the number of times the battery can be charged and discharged has been improved, it is still not able to go through as many charge cycles as a lithium-ion battery. However, since a lithium-sulphur battery does not need to be charged as often as a lithium-ion battery, it may be the case that the increase in energy density cancels out the lower total number of charge-discharge cycles.

“This is a way of getting around one of those awkward little problems that affects all of us,” said Coxon. “We’re all tied in to our electronic devices – ultimately, we’re just trying to make those devices work better, hopefully making our lives a little bit nicer.”

Harvard University researchers have made the first entirely 3D-printed organ-on-a-chip with integrated sensing. Built by a fully automated, digital manufacturing procedure, the 3D-printed heart-on-a-chip can be quickly fabricated in customized form factors allowing researchers to easily collect reliable data for short-term and long-term studies.

This new approach to manufacturing may one day allow researchers to rapidly design organs-on-chips, also known as microphysiological systems, that match the properties of a specific disease or even an individual patient’s cells.

The research is published in Nature Materials.

“This new programmable approach to building organs-on-chips not only allows us to easily change and customize the design of the system by integrating sensing but also drastically simplifies data acquisition,” said Johan Ulrik Lind, first author of the paper and postdoctoral fellow at the Harvard John A. Paulson School of Engineering and Applied Sciences (SEAS). Lind is also a researcher at the Wyss Institute for Biologically Inspired Engineering at Harvard University.

“Our microfabrication approach opens new avenues for in vitro tissue engineering, toxicology and drug screening research,” said Kit Parker, Tarr Family Professor of Bioengineering and Applied Physics at SEAS, who coauthored the study. Parker is also a Core Faculty Member of the Wyss Institute.

Organs-on-chips mimic the structure and function of native tissue and have emerged as a promising alternative to traditional animal testing. Harvard researchers have developed microphysiological systems that mimic the microarchitecture and functions of lungs, hearts, tongues and intestines.

However, the fabrication and data collection process for organs-on-chips is expensive and laborious. Currently, these devices are built in clean rooms using a complex, multi-step lithographic process and collecting data requires microscopy or high-speed cameras.

“Our approach was to address these two challenges simultaneously via digital manufacturing,” said Travis Busbee, coauthor of the paper and graduate student in the Lewis Lab. “By developing new printable inks for multi-material 3D printing, we were able to automate the fabrication process while increasing the complexity of the devices.”

The researchers developed six different inks that integrated soft strain sensors within the micro-architecture of the tissue. In a single, continuous procedure, the team 3D printed those materials into a cardiac microphysiological device — a heart on a chip — with integrated sensors.

“We are pushing the boundaries of three-dimensional printing by developing and integrating multiple functional materials within printed devices,” said Jennifer Lewis, Hansjorg Wyss Professor of Biologically Inspired Engineering, and coauthor of the study. “This study is a powerful demonstration of how our platform can be used to create fully functional, instrumented chips for drug screening and disease modeling.”

Lewis is also a Core Faculty Member of the Wyss Institute.

The chip contains multiple wells, each with separate tissues and integrated sensors, allowing researchers to study many engineered cardiac tissues at once. To demonstrate the efficacy of the device, the team performed drug studies and longer-term studies of gradual changes in the contractile stress of engineered cardiac tissues, which can occur over the course of several weeks.

“Researchers are often left working in the dark when it comes to gradual changes that occur during cardiac tissue development and maturation because there has been a lack of easy, non-invasive ways to measure the tissue functional performance,” said Lind. “These integrated sensors allow researchers to continuously collect data while tissues mature and improve their contractility. Similarly, they will enable studies of gradual effects of chronic exposure to toxins.”

“Translating microphysiological devices into truly valuable platforms for studying human health and disease requires that we address both data acquisition and manufacturing of our devices,” said Parker. “This work offers new potential solutions to both of these central challenges.”

Knowles, Goertek and AAC ranked as the top three global suppliers of packaged MEMS microphones for 2015, according to the latest analysis from IHS Markit (NASDAQ: INFO), a world leader in critical information, analytics and solutions.

MEMS (micro-electromechanical systems) technology is utilized to produce microphones used in laptops, hearing aids, wearables and smartphones among many other products. Last year, MEMS microphones remained the healthiest sensors segment for suppliers, in terms of unit volume and revenue, said Marwan Boustany, senior analyst for IHS Technology.

“Our updated analysis of 2015 MEMS microphone supplier market share, shows that Knowles remained the dominant supplier with more than two times the units and revenue of the second-place supplier, Goertek,” Boustany said. “In addition to offering a wide range of analog and digital output microphones for many applications, Knowles has also started shipping its VoiceIQ ‘intelligent’ microphones with local processing as it seeks to address both mobile and IOT applications.”

2016 mems mic growth

Strong growth for MEMS’ runner-ups

Goertek MEMS microphone units grew by an impressive 104 percent CAGR between 2011 and 2015, thanks in large part to its design wins in Apple, the IHS Markit analysis shows. Apple accounts for approximately 70 percent (in units) of Goertek’s MEMS microphone business in 2015. Goertek entered in large volume in the iPhone in 2014 and has since continued to increase its share; this has had the impact of reducing the share of AAC and Knowles in subsequent years.

While still solidly in third position among packaged MEMS suppliers after Goertek, AAC has faced challenges from Goertek in both Apple and in Chinese OEMs. This has resulted in a reduction in unit volume shipped by AAC in 2015 of almost 9 percent, IHS Markit says. However, AAC invested in a new technology for MEMS microphones in 2016 when it officially partnered with Vesper MEMS, a piezoelectric MEMS microphone start-up.

Boosting audio performance in handsets

The general adoption trend for microphones in smartphones has been towards higher performance, IHS Markit says. Driving this trend: OEMs want better quality audio for calls and hand-free communication, noise cancellation, voice recognition such as Siri and Google Now, as well as the availability of lower-cost microphones due to the erosion of ASP (average selling price).

“These types of use cases also drive high-performance microphone adoption in smart watches, tablets, noise cancelling earphones, hearing aids and increasingly in automotive cabins,” Boustany said.

Beyond performance, the average number of microphones per handset increased in 2015 due to Apple adopting four microphones in its iPhone 6S, with most other OEMs using two or three microphones in their mid- to high-end smartphones, the IHS Markit analysis shows. In tablets, smart watches and hearing aids, the number of microphones is between one and two. Adoption of microphones in automotive cabins can potentially exceed eight, depending on use cases and implementation choices in the future.

Knowles tops list for die makers, too

According to the IHS Technology analysis, Knowles – which produces its own microphone dies – holds the number one spot for market share in MEMS microphone production, with a dominant 43 percent market share.

Infineon acts as the major supplier of MEMS microphone dies to Goertek, AAC and BSE among others and stands solidly in second place with a 31 percent market share. In third place is Omron, which has supplied into STMicroelectronics, ACC and Goertek among others and has a 13 percent market share, the analysis shows. Neither Infineon nor Omron supply fully packaged MEMS microphone die.