Category Archives: MEMS

Leti, an institute of CEA Tech, is hosting a one-day conference covering “System Reliability & Security in a Connected World” in Lyon, France, on June 23.

Held at the Lyon Congress Center, this Leti Innovation Day event will explore novel, effective ways to ensure security in the emerging new phase of the digital revolution launched by the Internet of Things.

According to Alain Merle, Leti’s strategic marketing manager for security, this rapidly changing digital environment requires new paradigms for reliability, privacy and security in order to ensure a safe ecosystem for both industrials and consumers.  Hacking, data and identity theft, all digital threats to the real world, immediately follow the introduction or expansion of new applications of digital technology. The frontier between physical and digital security has vanished, he said.

“Companies must start implementing IoT security solutions at the start of the production cycle, and every new industrial project should be ruled not only by cost control, performance enhancement and energy savings, but also by security control,” added Lionel Rudant, Leti’s strategic marketing manager for IoT.

Presenters include Leti experts and industry leaders whose companies are collaborating with Leti on new security and reliability solutions for the next phase of the digital revolution. The lineup includes executives from Bureau Veritas, GLOBALFOUNDRIES, Intel, Mentor Graphics, Oberthur Technologies, Safran and STMicroelectronics, who will share their insights on topics such as enabling a connected world, assessing security and reliability, anticipating security challenges and how advanced technologies can strengthen security.

Leti is a world leader in security evaluations through advanced technology, applications and medical platforms prototyping new digital services and driving innovative requirements for integrated system architectures.

Visit Leti Innovation Day for the complete program, list of speakers and registration information.

Gartner, Inc. said global smartphone sales will continue to slow and will no longer grow in double digits. Worldwide smartphone sales are expected to grow 7 percent in 2016 to reach 1.5 billion units. This is down from 14.4 percent growth in 2015. In 2020, smartphone sales are on pace to total 1.9 billion units.

“The smartphone market will no longer grow at the levels it has reached over the last seven years,” said Roberta Cozza, research director at Gartner. “Smartphone sales recorded their highest growth in 2010, reaching 73 percent.”

Slowing replacement of phones

Today, the smartphone market has reached 90 percent penetration in the mature markets of North America, Western Europe, Japan and Mature Asia/Pacific, slowing future growth. Furthermore, users in these regions are not replacing or upgrading their smartphone as often as in previous years.

“In the mature markets, premium phone users are extending life cycles to 2.5 years, which is not going to change drastically over the next five years,” said Ms. Cozza.

Communications service providers (CSPs) have moved away from subsidies providing a “free” smartphone every two years, which has led to more varied upgrade cycles. On the other hand, CSPs have introduced financing programs and vendors such as Apple now offer upgrade programs that provides users with new hardware after only 12 months. “These programs are not for everyone, as most users are happy to hold onto their phone for two years or longer than before. They do so especially as the technology updates have become incremental rather than exponential,” added Ms. Cozza.

In emerging markets, the average lifetime of premium phones is between 2.2 and 2.5 years, while basic phones have an average lifetime of three years and more. “2015 was the year when sales of smartphones overtook those of feature phones for the first time in Sub-Saharan Africa. This region represents an attractive market for vendors that can persuade users to migrate to their first smartphone,” said Ms. Cozza.

India is the main focus for growth opportunity

Since mature markets are saturated, the focus for many vendors is on India and China. “India has the highest growth potential,” said Annette Zimmermann, research director at Gartner. “Sales of feature phones totaled 167 million units in 2015, 61 percent of total mobile phone sales in India.”

Smartphones are expensive for users in India, but with the average selling prices (ASPs) of low-end models falling, Gartner estimates that 139 million smartphones will be sold in India in 2016, growing 29.5 percent year over year. ASPs of mobile phones in India remain under $70, and smartphones under $120 will continue to contribute around 50 percent of overall smartphone sales in 2016.

After recording growth of 16 percent in 2014, sales of smartphones in China were flat in 2015. “In this saturated yet highly competitive smartphone market, there is little growth expected in China in the next five years,” said Ms. Zimmermann. Sales of smartphones in China represented 95 percent of total mobile phone sales in 2015. Similar to India, falling ASPs for smartphones will make them more affordable for users.”

“The worldwide smartphone market remains complex and competitive for all mobile phone vendors, and we are not expecting the vendor landscape to get smaller,” said Ms. Zimmermann. “In such a fluid vendor landscape, some will exit the market while newcomers, including mobile manufacturers or internet service providers from China and India, could make their debut.”

Gartner forecasts that by 2018, at least one nontraditional phone maker will be among the top five smartphone brands in China. “Chinese internet companies are increasingly investing in mobile device hardware development, platforms and distribution as they aim to grow their user bases and increase user loyalty and engagement,” concluded Ms. Zimmermann.

By Paula Doe, SEMI

The changing market for ICs means the end of business as usual for the greater semiconductor supply chain. Smarter use of data analytics looks like a key strategy to get new products more quickly into high yield production at improved margins.

Emerging IoT market drives change in manufacturing

The emerging IoT market for pervasive intelligence everywhere may be a volume driver for the industry, but it will also put tremendous pressure on prices that drive change in manufacturing. Pressure to keep ASPs of multichip connected devices below $1 to $5 for many IoT low-to-mid end applications, will drive more integration of the value chain, and more varied elements on the die. “The value chain must evolve to be more effective and efficient to meet the price and cost pressures for such IoT products and applications,” suggests Rajeev Rajan, VP of IoT, GLOBALFOUNDRIES, who will speak on the issue in a day-long forum on the future of smart manufacturing in the semiconductor supply chain at SEMICON West 2016 on July 14.

“It also means tighter and more complete integration of features on the die that enable differentiating capabilities at the semiconductor level, and also fewer, smaller devices that reduce the overall Bill of Materials (BOM), and result in more die per wafer.” He notes that at 22nm GLOBALFOUNDRIES is looking to enable an integrated connectivity solution instead of a separate die or external chip. Additional requirements for IoT are considerations for integrating security at the lower semiconductor/hardware layers, along with the typical higher layer middleware and software layers.

This drive for integration will also mean demand for new advanced packaging solutions that deliver smaller, thinner, and simpler form factors. The cost pressure also means than the next nodes will have to offer tangible power/performance/area/cost (PPAC) value, without being too disruptive a transition from the current reference flow. “Getting to volume yields faster will involve getting yield numbers earlier in the process, with increasing proof-points and planning iterations up front with customers, at times tied to specific use-cases and IoT market sub-segments,” he notes.

Rapid development of affordable data tools from other industries may help

Luckily, the wide deployment of affordable sensors and data analysis tools in other industries in other industries is developing solutions that may help the IC sector as well.  “A key trend is the “democratization” – enabling users to do very meaningful learning on data, using statistical techniques, without requiring a Ph.D. in statistics or mathematics,” notes Bill Jacobs, director, Advanced Analytics Product Management, Microsoft Corporation, another speaker in the program. “Rapid growth of statistics-oriented languages like R across industries is making it easier for manufacturers and equipment suppliers to capture, visualize and learn from data, and then build those learnings into dashboards for rapid deployment, or build them directly into automated applications and in some cases, machines themselves.”

Intel has reported using commercially available systems such as Cloudera, Aquafold, and Revolution Analytics (now part of Microsoft) to combine, store, analyze and display results from a wide variety of structured and unstructured manufacturing data. The system has been put to work to determine ball grid placement accuracy from machine learning from automatic comparison of thousands of images to select the any that deviate from the known-good pattern,  far more efficiently than human inspectors, and also to analyze tester parametrics to predict 90% of potential failures of the test interface unit before they happen.

“The IC industry may be ahead in the masses of data it gathers, but other industries are driving the methodology for easy management of the data,” he contends. “There’s a lot that can be leveraged from other industries to improve product quality, supply chain operations, and line up-time in the semiconductor industry.”

Demands for faster development of more complex devices require new approaches

As the cost of developing faster, smaller, lower power components gets ever higher, the dual sourcing strategies of automotive and other big IC users puts even more pressure on device makers to get the product right the first time. “There’s no longer time to learn with iterations to gradually improve the yield over time, now we need to figure out how to do this faster, as well as how to counter higher R&D costs on lower margins,” notes Sia Langrudi, Siemens VP Worldwide Strategy and Business Development,   who will also speak in the program.

The first steps are to recognize the poor visibility and traceability from design to manufacturing, and to put organizational discipline into place to remove barriers between silos. Then a company needs good baseline data, to be able to see improvement when it happens. “It’s rather like being an alcoholic, the first step is to recognize you have a problem,” says Langrudi. “People tell me they already have a quality management system, but they don’t. They have lots of different information systems, and unless they are capturing the information all in one place, the opportunity to use it is not there.”

Other speakers discussing these issues in the Smart Manufacturing Forum at SEMICON West July 14 include Amkor SVP Package Products Robert Lanzone, Applied Materials VP New Markets & Services Chris Moran, Intel VP IoT/GM Industrial Anthony Neal Graves, NextNine US Sales Manager Don Harroll, Optimal+ VP WW Marketing David Park, Qualcomm SVP Engineering Michael Campbell, Rudolph Technologies VP/GM Software Thomas Sonderman, and Samsung Sr Director, Engineering Development, Austin, Ben Eynon.

Learn more about the speakers at the SEMICON West 2016 session “Smart Manufacturing: The Key Opportunities and Challenges of the Next Generation of Manufacturing for the Electronics Value Chain.” To see all sessions in the Extended Supply Chain Forum, click here.

Scientists at UC San Diego, MIT and Harvard University have engineered “topological plexcitons,” energy-carrying particles that could help make possible the design of new kinds of solar cells and miniaturized optical circuitry.

The researchers report their advance in an article published in the current issue of Nature Communications.

Within the Lilliputian world of solid state physics, light and matter interact in strange ways, exchanging energy back and forth between them.

“When light and matter interact, they exchange energy,” explained Joel Yuen-Zhou, an assistant professor of chemistry and biochemistry at UC San Diego and the first author of the paper. “Energy can flow back and forth between light in a metal (so called plasmon) and light in a molecule (so called exciton). When this exchange is much faster than their respective decay rates, their individual identities are lost, and it is more accurate to think about them as hybrid particles; excitons and plasmons marry to form plexcitons.”

Materials scientists have been looking for ways to enhance a process known as exciton energy transfer, or EET, to create better solar cells as well as miniaturized photonic circuits which are dozens of times smaller than their silicon counterparts.

“Understanding the fundamental mechanisms of EET enhancement would alter the way we think about designing solar cells or the ways in which energy can be transported in nanoscale materials,” said Yuen-Zhou.

The drawback with EET, however, is that this form of energy transfer is extremely short-ranged, on the scale of only 10 nanometers (a 100 millionth of a meter), and quickly dissipates as the excitons interact with different molecules.

One solution to avoid those shortcomings is to hybridize excitons in a molecular crystal with the collective excitations within metals to produce plexcitons, which travel for 20,000 nanometers, a length which is on the order of the width of human hair.

Plexcitons are expected to become an integral part of the next generation of nanophotonic circuitry, light-harvesting solar energy architectures and chemical catalysis devices. But the main problem with plexcitons, said Yuen-Zhou, is that their movement along all directions, which makes it hard to properly harness in a material or device.

He and a team of physicists and engineers at MIT and Harvard found a solution to that problem by engineering particles called “topological plexcitons,” based on the concepts in which solid state physicists have been able to develop materials called “topological insulators.”

“Topological insulators are materials that are perfect electrical insulators in the bulk but at their edges behave as perfect one-dimensional metallic cables,” Yuen-Zhou said. “The exciting feature of topological insulators is that even when the material is imperfect and has impurities, there is a large threshold of operation where electrons that start travelling along one direction cannot bounce back, making electron transport robust. In other words, one may think about the electrons being blind to impurities.”

Plexcitons, as opposed to electrons, do not have an electrical charge. Yet, as Yuen-Zhou and his colleagues discovered, they still inherit these robust directional properties. Adding this “topological” feature to plexcitons gives rise to directionality of EET, a feature researchers had not previously conceived. This should eventually enable engineers to create plexcitonic switches to distribute energy selectively across different components of a new kind of solar cell or light-harvesting device.

By Debra Vogler, SEMI

A forum of industry experts at SEMICON West 2016 will discuss the challenges associated with getting from node 10 — which seems set for HVM — to nodes 7 and 5. Confirmed speakers at the “Node 10 to Node 5 ─ Dealing with the Slower Pace of Traditional Scaling (Track 2)” session on Tuesday, July 12, 2:00pm-4:00pm, are Lode Lauwers (imec), Guy Blalock (IM Flash), Kelvin Low (Samsung), Mike Chudzik (Applied Materials), Kevin Heidrich (Nanometrics), and David Dutton (Silvaco). SEMI interviewed Lauwers and Chudzik to see what challenges they see ahead as the industry progresses from node 7 to node 5.

According to Mike Chudzik, senior director, Cross-Business Unit Modules Team at Applied Materials, “The top tw or three process development challenges facing the industry at node 7 are RC reduction, RC reduction, and RC reduction,” Chudzik told SEMI. “At the 7nm node, parasitic resistance and parasitic capacitance delays are predicted to be greater than the inherent transistor delay.” Among the solutions he cites are new materials such as cobalt for the contact fill, lower-k spacers, and integration solutions, such as air-gap and replacement contact schemes. “While FinFETs are expected to scale to the 7nm node, their days are numbered. If you want to scale to the true historical 0.7X 7nm node, it’s a challenge for FinFETs because continuing to scale the gate length requires scaling the fin width.” He also explained that the variability in patterned fins will cause serious device performance challenges at near 5nm fin width on account of quantum confinement. “Something new like gate-all-around (GAA) devices are needed to fuel the next-generation of device scaling.”

Figure 1: At the 7nm node (CD of 13nm), the resistance of the TiN/W fill materials for the contact plug is expected to become higher than the interfacial contact resistance. SOURCE: Applied Materials

Figure 1: At the 7nm node (CD of 13nm), the resistance of the TiN/W fill materials for the contact plug is expected to become higher than the interfacial contact resistance. SOURCE: Applied Materials

Among the materials challenges in getting to nodes 7 and 5 are cobalt implementation for the contact, and Si/SiGe superlattices for the 5nm node, explained Chudzik. “The former challenge concerns replacing tungsten in the contact plug, and the latter is needed to form horizontal GAA structures.” Figure 1 shows that at the 7nm node (CD of 13nm) the resistance of the TiN/W fill material for the contact plug is expected to become higher than the interfacial contact resistance. “A TiN/Co solution provides relief.”

In addition to improving the performance of the interconnect, Lode Lauwers, VP, business development for CMOS technology at imec, told SEMI that getting to node 7 will require very advanced fin technology combined with a patterning solution. Looking ahead to node 5, he said it is expected that the fin will still be the reference technology, along with the introduction of new materials such as SiGe, and a high concentration of Ge in the channel as a mobility improvement, and possibly even the consideration of III-V materials (particularly at N5) (see Figures 2 and 3).

Figure 2: Performance and energy efficiency roadmap: devices architectures. SOURCE: imec

Figure 2: Performance and energy efficiency roadmap: devices architectures. SOURCE: imec

Figure 3: Performance and energy efficiency roadmap: transistor features that are driving the logic roadmap. SOURCE: imec

Figure 3: Performance and energy efficiency roadmap: transistor features that are driving the logic roadmap. SOURCE: imec

In looking out towards the horizon, Lauwers pointed out that the industry has to consider alternatives to the fin because there is an engineering limit to how small the fin dimensions can be made. “There is the possibility that at node 5 the industry will consider alternatives to the traditional fin, said Lauwers. “For example, the GAA structure (also referred to as a lateral or horizontal nanowire, HGAA) is superior in terms of gate control and will have better leakage control. That means you will be able to have better performance over a lower supply voltage with a lower threshold voltage.”

Beyond HGAA structures, Lauwers observed that the industry could move to a vertical nanowire structure (VGAA). But there are several contenders (see Figure 2). “It’s not up to imec to choose and it’s too early to say what will be the right option,” Lauwers told SEMI. “Maybe for certain applications or a certain technology positioning, a device maker might make a different compromise.”

In addition to imec and Applied Materials, speakers from IM Flash, Nanometrics, Samsung, and Silvaco will present at the “Scaling: Node 10 to Node 5” session of the three-day Advanced Manufacturing Forum (see Schedule-at-a-Glance) at SEMICON West 2016 which takes place July 12-14 in San Francisco, Calif.

Today, SEMI announced that 19 new fabs and lines are forecasted to begin construction in 2016 and 2017, according to the latest update of the SEMI World Fab Forecast report. While semiconductor fab equipment spending is off to a slow start in 2016, it is expected to gain momentum through the end of the year. For 2016, 1.5 percent growth over 2015 is expected while 13 percent growth is forecast in 2017.

Fab equipment spending ─ including new, secondary, and in-house ─ was down 2 percent in 2015. However, activity in the 3D NAND, 10nm Logic, and Foundry segments is expected to push equipment spending up to US$36 billion in 2016, 1.5 percent over 2015, and to $40.7 billion in 2017, up 13 percent. Equipment will be purchased for existing fabs, lines that are being converted to leading-edge technology, as well as equipment going into new fabs and lines that began construction in the prior year.

Table 1 shows the regions where new fabs and lines are expected to be built in 2016 and 2017. These projects have a probability of 60 percent or higher, according to SEMI’s data. While some projects are already underway, others may be subject to delays or pushed into the following year. The SEMI World Fab Forecast report, published May 31, 2016, provides more details about the construction boom.

new fab lines

Breaking down the 19 projects by wafer size, 12 of the fabs and lines are for 300mm (12-inch), four for 200mm, and three LED fabs (150mm, 100mm, and 50mm). Not including LEDs, the potential installed capacity of all these fabs and lines is estimated at almost 210,000 wafer starts per month (in 300mm equivalents) for fabs beginning construction in 2016 and 330,000 wafer starts per month (in 300mm equivalents) for fabs beginning construction in 2017.

In addition to announced and planned new fabs and lines, SEMI’s World Fab Forecast provides information about existing fabs and lines with associated construction spending, e.g. when a cleanroom is converted to a larger wafer size or a different product type.

In addition, the transition to leading-edge technologies (as we can see in planar technologies, but also in 3D technologies) creates a reduction in installed capacity within an existing fab. To compensate for this reduction, more conversions of older fabs may take place, but also additional new fabs and lines may begin construction.

For insight into semiconductor manufacturing in 2016 and 2017 with details about capex for construction projects, fab equipping, technology levels, and products, visit the SEMI Fab Database webpage and order the SEMI World Fab Forecast Report. The report, in Excel format, tracks spending and capacities for over 1,100 facilities including over 60 future facilities, across industry segments from Analog, Power, Logic, MPU, Memory, and Foundry to MEMS and LEDs facilities.

VTT Technical Research Centre of Finland developed an extremely efficient small-size energy storage, a micro-supercapacitor, which can be integrated directly inside a silicon microcircuit chip. The high energy and power density of the miniaturized energy storage relies on the new hybrid nanomaterial developed recently at VTT. This technology opens new possibilities for integrated mobile devices and paves the way for zero-power autonomous devices required for the future Internet of Things (IoT).

Supercapacitors resemble electrochemical batteries. However, in contrast to for example mobile phone lithium ion batteries, which utilize chemical reactions to store energy, supercapacitors store mainly electrostatic energy that is bound at the interface between liquid and solid electrodes. Similarly to batteries supercapacitors are typically discrete devices with large variety of use cases from small electronic gadgets to the large energy storages of electrical vehicles.

The energy and power density of a supercapacitor depends on the surface area and conductivity of the solid electrodes. VTT’s research group has developed a hybrid nanomaterial electrode, which consists of porous silicon coated with a few nanometre thick titanium nitride layer by atomic layer deposition (ALD). This approach leads to a record large conductive surface in a small volume. Inclusion of ionic liquid in a micro channel formed in between two hybrid electrodes results in extremely small and efficient energy storage.

The new supercapacitor has excellent performance. For the first time, silicon based micro-supercapacitor competes with the leading carbon and graphene based devices in power, energy and durability.

Micro-supercapacitors can be integrated directly with active microelectronic devices to store electrical energy generated by different thermal, light and vibration energy harvesters and to supply the electrical energy when needed. This is important for autonomous sensor networks, wearable electronics and mobile electronics of the IoT.

VTT’s research group takes the integration to the extreme by integrating the new nanomaterial micro-supercapacitor energy storage directly inside a silicon chip. The demonstrated in-chip supercapacitor technology enables storing energy of as much as 0.2 joule and impressive power generation of 2 watts on a one square centimetre silicon chip. At the same time it leaves the surface of the chip available for active integrated microcircuits and sensors.

VTT is currently seeking a party interested in commercializing the technique.

IC Insights has just released the Update to its 2016 IC Market Drivers Report that examines and evaluates key existing and emerging end-use applications that will support and propel the IC industry through 2019.

In 2015 and early 2016, there were numerous reports of slowing in the Chinese smartphone market. Since most of the Chinese smartphone producer’s sales are to Chinese customers, this slowdown became evident in some of their 2015 and 1Q16 smartphone sales figures.  For example, China-based Coolpad’s smartphone sales dropped by 44% in 2015 to only 25.5 million units.  Moreover, Xiaomi, a real “high-flyer” in smartphone sales in 2013 and 2014 saw its growth slow to 16% last year.  While a 16% growth rate is still very commendable, its sales of about 71 million smartphones last year was well below the company’s earlier stated goal of shipping 100 million smartphones in 2015.

Figure 1 depicts actual 1Q16 smartphone unit sales by the top 12 companies with a forecast for their full-year 2016 unit volume shipments.  As shown, eight of the top 12 companies are headquartered in China with an Indian company (Micromax) making the list for the first time.   Gionee, a China-based smartphone supplier, just missed making the 1Q16 top 12 ranking after shipping 4.8 million handsets in the quarter.

IC Insights believes that there will be very little middle ground with regard to smartphone shipment growth rates among the top 12 suppliers this year.  As shown, seven of the top twelve companies are forecast to register 2016 growth rates of 6% or less while the other five companies are expected to each log 29% or better increases.  Further illustrating the maturing of the smartphone market, the top two suppliers, Samsung and Apple, are each forecast to show a slight decline in smartphone shipments this year.

Three companies are expected to drop out of the top 12 ranking this year as compared to 2015—Japan-based Sony, U.S.-based Microsoft, and China-based Coolpad.  These three companies saw their 1Q16 sales of smartphones drop to 3.4, 2.3, and 4.0 million, respectively.  Although Microsoft announced it intends to sell its non-smartphone business later this year, its early 2016 Lumia smartphones shipments put it on a path to sell less than 15 million units in 2016.

chinese ic suppliers fig 1

Figure 1

Additional details on the cellphone IC market are included in the 2016 Update of IC Insights’ IC Market Drivers—A Study of Emerging and Major End-Use Applications Fueling Demand for Integrated Circuits. This report examines the largest, existing system opportunities for ICs and evaluates the potential for new applications that are expected to help fuel the market for ICs through the end of this decade.