Category Archives: MEMS

Systematic – and predictive – cost reduction in semiconductor equipment manufacturing

BY TOM MARIANO, Foliage, Burlington, MA

After a period of double-digit growth, the semiconductor equipment industry has now stabilized to the point where recent market forecasts are predicting anemic single-digit growth rates. This is driven by total market demand from chipmakers. For example, despite strong growth of 12.9 percent in 2014, Gartner, Inc. projects worldwide semiconductor capital spending to only grow 0.8 percent in 2015, to $65.7 billion. [1] Additionally, this industry has always been subject to volatile demand cycles that are notoriously difficult to predict.

Translation: It’s extremely challenging for today’s semiconductor equipment manufacturers to improve their financial performance. There are fewer and fewer opportunities to grow topline revenue through innovation and new product development. And, after several years of cutting costs on existing products and not realizing enough cost reduction to improve margins, it’s difficult to know how to do it differently.

Yet a viable alternative to improve financial performance does exist: A disciplined, rigorous, and systematic approach to reducing costs that delivers more predictive results.

A systematic approach to cost reduction

Where cutting costs was once perceived as the end result of “desperate times, desperate measures,” many innovators are now using this approach much more proactively. By
meeting the idea of cost reduction head on – as an opportunity, not a last resort – many semiconductor equipment makers are uncovering wasteful, inefficient, and costly processes, often in areas they once overlooked. At this point, you may be thinking, “All of this sounds great, but what is a systematic approach to cost reduction, and how is it different from what I’m doing?”

Remember that many manufacturers (in all industries) tend to have a hard time driving costs down. They may set cost reduction goals and then attempt to achieve them using various ad hoc approaches. But they really need to understand exactly what their true costs are, where they exist, and which areas will improve their margins.

A systematic approach to cost reduction gives them this insight. With improved visibility into the entire organization, various processes, and how they execute, semiconductor equipment manufacturers can’t identify the right places to cut costs and hit their cost savings goals. This is a very detailed and planned approach in which organizations closely examine areas such as cost of goods sold, R&D, and service to make more informed decisions that will position their business for long-term success. This is the value of a systematic approach to cost reduction.

This approach also introduces the element of speed, helping equipment makers realize cost savings much faster than ad hoc cost-cutting initiatives and puts them on a path to achieve more predictive results. Beyond the positive (and more obvious) impact successful cost reduction has on a semiconductor equipment manufacturer’s bottom line, it also provides a number of significant benefits such as improving productivity, freeing up key personnel, and providing needed capital to fuel new growth.

The path to predictive results

Even if the concept of a more strategic approach to cutting costs sounds reasonable, many semiconductor equipment manufacturers struggle with how to begin and where to focus. All to often they resort to making reactive decisions regarding existing products without the necessary data, leading them to ask questions such as, “Should we have an obsolescence plan for this product?” “How much could we save?” and “Will this lead to bigger problems down the road?”

Without understanding where your best opportunities for cost cutting are, it’s a lot larder to predict when, and if, cost reduction goals will be met. A systematic approach to cost reduction includes establishing clear cost targets, communicating them to leadership, and measuring and reporting results along the way.

The first step is to engage with an outside firm that has a singular focus on cost reduction, and one that is clearly separated from day-to-day operations and current organizational dynamics. Such an engagement will yield an actionable list of improvements with specific cost targets, realistic timelines for achieving these goals, and future plans for reinvesting the cost savings.

More specifically, a systematic cost reduction approach will focus on three key areas: material costs, R&D costs, and service costs:

1. Material costs: The bill of materials is one of the most common ways to see all the components needed to produce the end product. But this goes well beyond the pure cost of materials. Research has shown that improving the way these components are managed can affect 80-90% of the product’s total costs.[2]

For semiconductor equipment manufacturers, the cost reduction process should start with the selection of the products or sub-assemblies that have the highest potential for savings. Focus on those products that are still generating significant revenue, but may not be receiving much attention in terms or engineering upgrades and enhancements. Thoroughly examine the bill of materials for these products by addressing materials, design, complexity reduction, the potential to create common assemblies, and more.

Value engineering efforts can simultaneously improve product functionality and performance while reducing bill of material costs. This effort should factor in ways to meet RoHS requirements and when to make end-of-life decisions for various electrical components to improve design efficiency and the effectiveness of the product.

A realistic cost reduction goal can then be created and a resulting value-engineering project can commence, often using low-cost offshore resources to best achieve those savings.

2. R&D costs: Making better decisions related to R&D processes and product development can shave considerable costs. Some areas to focus on include:

• When to officially end of life non-performing products
• When to consolidate products, or possibly even entire R&D departments
• When and how to move sustaining engineering efforts offshore, or to other lower-cost alternatives

The critical next step is to look at all products and all product variations to determine if an official end-of-life program should be employed. These decisions are notoriously hard to make and often require difficult conversations with key customers, but they are necessary nonetheless.

Many semiconductor equipment manufacturers have grown through acquisitions, creating redundant engineering groups that can be eliminated or downsized. Performing an organizational analysis of all R&D activities may uncover opportunities to consolidate and combine functions or create centers of excellence that focus on specific technical areas eliminating redundancies of technical specialty.

3. Service costs: Examine engineering and design processes to find ways to improve performance, reliability, and costs. For example, adding data collection technology or product diagnostics to enhance remote support efforts and predictive maintenance.

Improvement of product reliability is usually a large multiplier when it comes to service and spare parts costs. Collect and analyze field data to find the most significant issues driving service costs and then look to cut where possible.

For example, equipment in the field often does not have the capability to report enough information to effectively identify a problem. Adding increased data logging and communication can be used to clarify machine status and point services in the right direction. Connectivity can also help with remote diagnostics, all of which helps reduce costs, uptime, and customer satisfaction.

Cost Reduction as a Competitive Advantage

Short-term market forecasts will continue to make it challenging for semiconductor equipment manufacturers to deliver improved financial results. Yet the concept of a systematic approach to cost reduction is a proven way for them to proactively cut costs – in the right places – and also make better decisions related to existing products and other business systems and processes.

By taking a disciplined, rigorous, and objective look at any and all parts of their organization, semiconductor equipment makers can capitalize on new opportunities to free valuable resources, improve processes and future technology, and reinvest savings for future growth. For many equipment manufacturers the greatest obstacle to successfully exploiting these opportunities is insufficient experience and expertise with a disciplined and unconventional way of approaching cost reduction projects. A systematic approach to cost reduction will be the key to success for companies looking to improve their competitive advantage.

References

1. Gartner, Inc., “Gartner Says Worldwide Semiconductor Capital Spending to Increase 0.8 Percent in 2015: Conser- vative Investment Strategies Paving the Way to Slower Growth in 2015,” January 13, 2015. http://www.gartner. com/newsroom/id/2961017.

2. Forbes, “Product Lifecycle Management: A New Path to Shareholder Value?” August 5, 2011, http://www. forbes.com/sites/ciocentral/2011/08/05/product-lifecycle- management-a-new-path-to-shareholder-value/.

Security by design


November 13, 2015

Chowdary_Yanamadala-150x150By Chowdary Yanamadala, Senior Vice President of Business Development, ChaoLogix

The advent of Internet-connected devices, the so-called Internet of Things (IoT), offers myriad opportunities and significant risks. The pervasive collection and sharing of data by IoT devices constitutes the core value proposition for most IoT applications. However, it is our collective responsibility, as an industry, to secure the transport and storage of the data. Failing to properly secure the data risks turning the digital threat into a physical threat.  

Properly securing IoT systems requires layering security solutions. Data must be secured at both the network and hardware level. As a hardware example, let’s concentrate, on the embedded security implemented by semiconductor chips.

Authentication and encryption are the two main crypto functions utilized to ensure data security. With the mathematical security of the standardized algorithms (such as AES, ECDSA, SHA512, etc.) is intact, hackers often exploit the implementation defects to compromise the inherent security provided by the algorithms.

One of the most dangerous and immediate threats to data security is a category of attacks called Side Chanel Analysis attacks (SCA). SCA attacks exploit the power consumption signature during the execution of the crypto algorithms. This type of attack is called Differential Power Analysis (DPA). Another potent attack form of SCA is exploiting the Electromagnetic emanations that are occurring during the execution of the crypto algorithm – or Differential Electromagnetic Analysis attacks (DEMA).

Both DPA and DEMA attacks rely on the fact that sensitive data, such as secret keys, leaks via the power signature (or EM signature) during execution of the crypto algorithm.

DPA and DEMA attacks are especially dangerous, not only because of their effectiveness in exploiting security vulnerabilities but also due the low cost of the equipment required for the attack. An attacker can carry out DPA attacks against most security chips using equipment costing less than $2,000.

There are two fundamental ways to solve the threat of DPA and DEMA. One approach is to address the symptoms of the problem. This involves adding significant noise to the power signature in order to obfuscate the sensitive data leakage. This is an effective technique.  However, it is an ad-hoc and temporary measure against a potent threat to data security. Chip manufacturers can also apply this technique as a security patch, or afterthought, once  and architecture work is completed.

Another way (and arguably a much better way) to solve the threat of DPA is to address the problem at the source. The source of the threat derives from the leakage of sensitive data the form of power signature variations. The power signature captured during the crypto execution is dependent on the secret key that is processed during the crypto execution. This makes the power signature indicative of the secret key.

What if we address the problem by minimizing the relation between the power signature and the secret key that is used for crypto computation? Wouldn’t this offer a superior security? Doesn’t addressing the problem at the source provide more fundamental security? And arguably a more permanent security solution?

Data security experts call this Security By Design. It is obvious that solving a problem at the source is a fundamentally better approach than providing symptomatic relief to the problems. This is true in the case of data security as well. In order to achieve the solution (against the threat of DPA and DEMA) at the source, chip designers and architects need to build the security into the architecture.

Security needs to be a deliberate design specification and needs to be worked into the fabric of the design. Encouragingly, more and more chip designers are moving away from addressing security as an afterthought and embracing security by design.

As an industry, we design chips for performance, power, yield and testability. Now it is time to start designing for security. This is especially true for chips used in IoT applications. These chips tend to be small, have limited computational power and under tight cost constraints. It is, therefore, difficult, and in some cases impossible, to apply security patches as an afterthought. The sound approach is to start weaving security into the building blocks of these chips.

In sum, designing security into a chip is as much about methodology as it is about acquiring various technology and tools. As IoT applications expand and the corresponding demand for inherently secure chips grows, getting this methodology right will be a key to successful deployment of secure IoT systems.

Related data security articles: 

Security should not be hard to implement

ChaoLogix introduces ChaoSecure technology to boost semiconductor chip security

From laptops and televisions to smartphones and tablets, semiconductors have made advanced electronics possible. These types of devices are so pervasive, in fact, that Northwestern Engineering’s Matthew Grayson says we are living in the “Semiconductor Age.”

“You have all these great applications like computer chips, lasers, and camera imagers,” said Grayson, associate professor of electrical engineering and computer science in Northwestern’s McCormick School of Engineering. “There are so many applications for semiconductor materials, so it’s important that we can characterize these materials carefully and accurately. Non-uniform semiconductors lead to computer chips that fail, lasers that burn out, and imagers with dark spots.”

Grayson’s research team has created a new mathematical method that has made semiconductor characterization more efficient, more precise, and simpler. By flipping the magnetic field and repeating one measurement, the method can quantify whether or not electrical conductivity is uniform across the entire material – a quality required for high-performance semiconductors.

“Up until now, everyone would take separate pieces of the material, measure each piece, and compare differences to quantify non-uniformity,” Grayson said. “That means you need more time to make several different measurements and extra material dedicated for diagnostics. We have figured out how to measure a single piece of material in a magnetic field while flipping the polarity to deduce the average variation in the density of electrons across the sample.”

Remarkably, the contacts at the edge of the sample reveal information about the variations happening throughout the body of the sample.

Supported by funding from the Air Force’s Office of Scientific Research, Grayson’s research was published on October 28 online in the journal Physical Review Letters. Graduate student Wang Zhou is first author of the paper.

One reason semiconductors have so many applications is because researchers and manufacturers can control their properties. By adding impurities to the material, researchers can modulate the semiconductor’s electrical properties. The trick is making sure that the material is uniformly modulated so that every part of the material performs equally well. Grayson’s technique allows researchers and manufacturers to directly quantify such non-uniformities.

“When people see non-uniform behavior, sometimes they just throw out the material to find a better piece,” Grayson said. “With our information, you can find a piece of the material that’s more uniform and can still be used. Or you can use the information to figure out how to balance out the next sample.”

Grayson’s method can be applied to samples as large as a 12-inch wafer or as small as an exfoliated 10-micron flake, allowing researchers to profile the subtleties in a wide range of semiconductor samples. The method is especially useful for 2-D materials, such as graphene, which are too small for researchers to make several measurements across the surface.

Grayson has filed a patent on the method, and he hopes the new technique will find use in academic laboratories and industry.

“There are companies that mass produce semiconductors and need to know if the material is uniform before they start making individual computer chips,” Grayson said. “Our method will give them better feedback during sample preparation. We believe this is a fundamental breakthrough with broad impact.”

Gartner, Inc. forecasts that 6.4 billion connected things will be in use worldwide in 2016, up 30 percent from 2015, and will reach 20.8 billion by 2020. In 2016, 5.5 million new things will get connected every day.

Gartner estimates that the Internet of Things (IoT) will support total services spending of $235 billion in 2016, up 22 percent from 2015. Services are dominated by the professional category (in which businesses contract with external providers in order to design, install and operate IoT systems), however connectivity services (through communications service providers) and consumer services will grow at a faster pace.

“IoT services are the real driver of value in IoT, and increasing attention is being focused on new services by end-user organizations and vendors,” said Jim Tully, vice president and distinguished analyst at Gartner.

Enterprises to Bolster IoT Revenue

“Aside from connected cars, consumer uses will continue to account for the greatest number of connected things, while enterprise will account for the largest spending,” said Mr. Tully. Gartner estimates that 4 billion connected things will be in use in the consumer sector in 2016, and will reach 13.5 billion in 2020 (see Table 1).

Table 1: Internet of Things Units Installed Base by Category (Millions of Units)

Category 2014 2015 2016 2020
Consumer 2,277 3,023 4,024 13,509
Business: Cross-Industry 632 815 1,092 4,408
Business: Vertical-Specific 898 1,065 1,276 2,880
Grand Total 3,807 4,902 6,392 20,797

Source: Gartner (November 2015)

In terms of hardware spending, consumer applications will amount to $546 billion in 2016, while the use of connected things in the enterprise will drive $868 billion in 2016 (see Table 2).

Table 2: Internet of Things Endpoint Spending by Category (Billions of Dollars)

Category 2014 2015 2016 2020
Consumer 257 416 546 1,534
Business: Cross-Industry 115 155 201 566
Business: Vertical-Specific 567 612 667 911
Grand Total 939 1,183 1,414 3,010

Source: Gartner (November 2015)

In the enterprise, Gartner considers two classes of connected things. The first class consists of generic or cross-industry devices that are used in multiple industries, and vertical-specific devices that are found in particular industries.

Cross-industry devices include connected light bulbs, HVAC and building management systems that are mainly deployed for purposes of cost saving. The second class includes vertical-specific devices, such as specialized equipment used in hospital operating theatres, tracking devices in container ships, and many others.

“Connected things for specialized use are currently the largest category, however, this is quickly changing with the increased use of generic devices. By 2020, cross-industry devices will dominate the number of connected things used in the enterprise,” said Mr. Tully.

 

Analog ICs are critical to nearly all electronic devices. The world electronics market will consume over 121 billion analog ICs in 2015. This translates to several analog ICs per electronic device.

Analog ICs experienced stronger than average growth over the last several years as the mobility product segment grew at double digit rates. These products have a higher than average analog content, thus growth has exceeded the overall semiconductor market. However, this appears to be changing as the markets for end applications like smartphones and tablets are now growing at a slower rate as these markets saturate and replacements become the growth driver.

“The Internet of Things presents a great growth potential for analog and sensors, but large volumes for that market are still a few years away,” said Jim Feldhan, president of Semico Research.  “Consequently, we are seeing an inflection point in the analog market. Over the next five years, analog sales growth will slow to a CAGR of 4.4% in dollar terms and 5.3% in unit terms.” This growth rate will lead to a market size of $56.5 billion by 2020.

Semico Research’s newest report, Analog Market: Making Digital Systems Come Alive, forecasts 35 analog product categories from general purpose analog to power management to automotive and medical chips. The accompanying Excel spreadsheet includes quarterly data for these categories. Many of these products are made on older process technologies and account for 41.3% of total analog revenues. This report also includes regional data and detailed analog wafer demand data.

 

A recent report from Navigant Research analyzes the global market opportunity for residential Internet of Things (IoT) devices, including forecasts for shipments, installed base, and revenue, segmented by region and device type, through 2025.

According to the report, global revenue from shipments of these residential IoT devices is expected to total more than $330 billion from 2015 to 2025. The report also concludes that yearly revenue will grow from $7.3 billion in 2015 to $67.7 billion in 2025. Through devices such as smart thermostats that allow users to remotely control household temperatures or LED lights that can be switched on and off from a smartphone, the much-hyped IoT concept has arrived in the residential setting. Major companies are beginning to recognize the opportunity that these communicating devices offer for increased efficiency, automation, security, and comfort in the home.

“The IoT is like putting together a jigsaw puzzle without any edge pieces, with the number of pieces growing exponentially into the billions,” says Neil Strother, principal research analyst with Navigant Research. “Communicating devices in the IoT traverse a wide range of industries and sectors—virtually all areas of life can expect to see some form of this connected world.”

Despite the many drivers for the residential IoT market, there are at present multiple protocols and standards that are creating an interoperability barrier, according to the report. Wi-Fi, ZigBee, Bluetooth, and others are all vying for market viability, which is creating confusion for consumers and stalling overall adoption.

The report, IoT (Internet of Things) for Residential Customers, defines the emerging residential IoT market and examines the global market opportunity related to IoT technologies. The study provides an analysis of the key market drivers and barriers associated with residential IoT devices, including smart meters, smart thermostats, lighting, smart appliances, security and management systems, and smart plugs. Global market forecasts for shipments, installed base, and revenue, segmented by region and device type, extend through 2025. The report also examines the key technologies related to residential IoT devices, as well as the competitive landscape. An Executive Summary of the report is available for free download on the Navigant Research website.

Cambridge, UK — November 9, 2015 — Xaar plc, a world leader in industrial inkjet technology, and Lawter, along with its parent company Harima Chemicals Group (HCG), announced a collaboration to optimize the performance of a line of nanosilver conductive inks in the Xaar 1002 industrial inkjet printhead. The combined solution will be of particular interest to manufacturers of consumer electronics goods looking for a robust and reliable method for printing antennas and sensors with silver nanoparticle ink as part of their manufacturing processes.

Industrial inkjet offers significant advantages over traditional print technologies to manufacturers of consumer electronics products. Inkjet is a cleaner process than other methods of printing silver inks; this is especially relevant when printing onto a substrate, such as a display, in which any yield loss is very expensive. With inkjet, manufacturers can very precisely control the amount of ink dispensed in certain areas of a pattern so that the ink or fluid deposited can be thicker in some areas and thinner in others. Similarly, inkjet enables the deposition of a much thinner layer of fluids than traditional methods, which is significant for the manufacturers looking to produce thinner devices. In addition, inkjet is one of the few technologies able to print a circuit over a substrate that has a structured surface.

“This is an excellent opportunity to showcase our latest technological breakthroughs and demonstrate the unique value that our revolutionary nanoparticle inkjet solutions can play as part of an integrated system solutions in the PE world,” says Dr. Arturo Horta Ph.D., Business Development Manager for Lawter Innovation Group.

HCG pioneered the development and manufacture of silver nanoparticle conductive inks for the printed electronics industry over 20 years ago and has over 100 patents related to its nanoparticle dispersion technology. This line of nanosilver conductive inks for inkjet printing offers a unique combination of low temperature sintering and high circuit conductivity. In addition, Lawter’s novel inks are compatible with a range of photonic curing tools as well as a variety of substrates.  These value-added features, together for the first time in a single product, provide increased project efficiency, decreased raw material costs and finer line printing.  All of this adds up to significant, quantifiable benefits for the end-user.

Xaar, also a major player in industrial manufacturing applications, has been delivering inkjet technology for 25 years. Its leading printhead, the Xaar 1002 is particularly suitable for Lawter’s nanosilver conductive inks due to the printhead’s unique TF Technology™ (fluid recirculation) which ensures a continuous flow of the heavy particulate in the ink to deliver uninterrupted high volume production printing.

“The applications that will benefit from the combination of Lawter’s nanosilver conductive inks and Xaar’s 1002 printhead are exciting,” says Keith Smith, Director of Advanced Manufacturing at Xaar. “We are seeing more and more that the consumer electronics market is looking for a printing solution that provides the quality of the Lawter ink and production reliability of the Xaar GS6 1002 to allow designers to make thinner devices.  The printhead and ink combination, along with photonic sintering, is unlocking mechanical and electrical designs never thought possible before.”

 

WEST LAFAYETTE, Ind. — Silver nanowires hold promise for applications such as flexible displays and solar cells, but their susceptibility to damage from highly energetic UV radiation and harsh environmental conditions has limited their commercialization.

New research suggests wrapping the nanowires with an ultrathin layer of carbon called graphene protects the structures from damage and could represent a key to realizing their commercial potential.

“We show that even if you have only a one-atom-thickness material, it can protect from an enormous amount of UV radiation damage,” said Gary Cheng, an associate professor of industrial engineering at Purdue University.

The lower images depict how graphene sheathing protects nanowires even while being subjected to 2.5 megawatts of energy intensity per square centimeter from a high-energy laser, an intensity that vaporizes the unwrapped wires. The upper images depict how the unwrapped wires are damaged with an energy intensity as little as .8 megawatts per square centimeter. (Purdue University image)

The lower images depict how graphene sheathing protects nanowires even while being subjected to 2.5 megawatts of energy intensity per square centimeter from a high-energy laser, an intensity that vaporizes the unwrapped wires. The upper images depict how the unwrapped wires are damaged with an energy intensity as little as .8 megawatts per square centimeter. (Purdue University image)

Devices made from silver nanowires and graphene could find uses in solar cells, flexible displays for computers and consumer electronics, and future “optoelectronic” circuits for sensors and information processing. The material is flexible and transparent, yet electrically conductive, and is a potential replacement for indium tin oxide, or ITO. Industry is seeking alternatives to ITO because of drawbacks: It is relatively expensive due to limited abundance of indium, and it is inflexible and degrades over time, becoming brittle and hindering performance, said Suprem Das, a former Purdue doctoral student and now a postdoctoral researcher at Iowa State University and The Ames Laboratory.

However, a major factor limiting commercial applications for silver nanowires is their susceptibility to harsh environments and electromagnetic waves.

“Radiation damage is widespread,” said Das, who led the work with Purdue doctoral student Qiong Nian (pronounced Chung Nee-an). “The damage occurs in medical imaging, in space applications and just from long-term exposure to sunlight, but we are now seeing that if you wrap silver nanowires with graphene you can overcome this problem.”

Findings appeared in October in the journal ACS Nano, published by the American Chemical Society. The paper was authored by Das; Nian; graduate students Mojib Saei, Shengyu Jin and Doosan Back; previous postdoctoral research associate Prashant Kumar; David B. Janes, a professor of electrical and computer engineering; Muhammad A. Alam, the Jai N. Gupta Professor of Electrical and Computer Engineering; and Cheng.

Raman spectroscopy was performed by the Purdue Department of Physics and Astronomy. Findings showed the graphene sheathing protected the nanowires even while being subjected to 2.5 megawatts of energy intensity per square centimeter from a high-energy laser, which vaporizes the unwrapped wires. The unwrapped wires were damaged with an energy intensity as little as .8 megawatts per square centimeter. (The paper is available at http://pubs.acs.org/doi/abs/10.1021/acsnano.5b04628.)

“It appears the graphene coating extracts and spreads thermal energy away from the nanowires,” Das said. The graphene also helps to prevent moisture damage.

The research is a continuation of previous findings published in 2013 and detailed in this paper: http://onlinelibrary.wiley.com/doi/10.1002/adfm.201300124/full. The work is ongoing and is supported by the National Science Foundation and a National Research Council Senior Research Associateship.

By Dr. Dan Tracy, Senior Director, Industry Research and Statistics, SEMI

With the recent release of Apple’s 6s and the form factors of internet enabled mobile devices and the emergence of the IoT (Internet of Things), advanced packaging is clearly the enabling technology providing solutions for mobile applications and for semiconductor devices fabricated at 16 nm and below process nodes. These packages are forecasted to grow at a compound annual growth rate (CAGR) of over 15% through 2019.  In addition, the packaging technologies have evolved and continue to evolve so to meet the growing integration requirements needed in newer generations of mobile electronics. Materials are a key enabler to increasing the functionality of thinner and smaller package designs and for increasing the functionality of system-in-package solutions.

Figure 1: Packaging Technology Evolution – Great Complexity in Smaller, Thinner Form Factors, courtesy of TechSearch International, Inc.

Figure 1: Packaging Technology Evolution – Great Complexity in Smaller, Thinner Form Factors, courtesy of TechSearch International, Inc.

The observations related to mobile products include:

  • New package form factors to satisfy high-performance, high-bandwidth, and low power consumption requirements in a thinner and smaller package.
  • Packaging solutions to deliver systems-in-package capabilities while satisfying low-cost requirements.
  • Shorter lifetimes and differing reliability requirements. For example, high-end smartphones and tablets, the key high reliability requirement is to pass the drop test; and packaging material solutions are essential to delivering such reliability.
  • Shorter production ramp times to meet time-to-market demands of end product. This is becoming critical and causes redundancy in capacity to be required, capacity that is underutilized for part of the year

Packaging must provide a low-cost solution and have an infrastructure in place to meet steep ramps in electronic production. The move towards bumping and flip chip has only accelerated with the growth in mobile electronics, though leadframe and wirebond technologies remain as important low-cost alternatives for many devices. Wafer bumping has been a major packaging market driver for over a decade, and with the growth in mobile the move towards wafer bumping and flip chip has only accelerated with finer pitch copper pillar bump technology ramping up. Mobile also drives wafer-level packaging (WLP) and Fan-Out (FO) WLP. New wafer level dielectric materials and substrate designs are required for these emerging package form factors.

Going forward, the wearable and IoT markets will have varying packaging requirements depending on the application, the end use environment, and reliability needs. Thin and small are a must though like other applications cost versus performance will determine what package type is adopted for a given wearable product, so once more leadframe and wirebonded packages could be the preferred solution. And in many wearable applications, materials solutions must provide a lightweight and flexible package.

Such packaging solutions will remain the driver for materials consumption and new materials development, and the outlook for these packages remain strong. Materials will make possible even smaller and thinner packages with more integration and functionality.  Low cost substrates, matrix leadframe designs, new underfill, and die attach materials are just some solutions to reduce material usage and to improve manufacturing throughput and efficiencies.

SEMI and TechSearch International are once again partnering to prepare a comprehensive market analysis of how the current packaging technology trend will impact the packaging manufacturing materials demand and market.  The new edition of “Global Semiconductor Packaging Materials Outlook” (GSPMO) report is a detailed market research study in the industry that quantifies and highlights opportunities in the packaging material market. This new SEMI report is an essential business tool for anyone interested in the plastic packaging materials arena. It will benefit readers to better understand the latest industry and economic trends, the packaging material market size and trend, and the respective market drivers in relation to a forecast out to 2019. For example, FO-WLP is a disruptive technology that impacts the packaging materials segment and the GSPMO addresses this impact.

 

TOKYO – November 4, 2015 – SEMI today announced further details on SEMICON Japan, bringing innovation to Tokyo Big Sight on December 16 through 18. SEMICON Japan, already the largest and most important gathering of the semiconductor manufacturing industry, has increased exhibition and programing in the high-growth Internet of Things (IoT) applications and technologies with its World of IoT pavilion. SEMICON Japan will also, for the first time, feature the Innovation Village, showcasing high-tech startups that bring the potential for new driving forces and new ideas for the future growth of the microelectronics supply chain.

Held in conjunction with SEMICON Japan, the World of IoT is a “show-within-a-show” and is the only exhibition showcase and conference in Japan to cover the complete Internet of Things supply chain, from silicon to system. Global key IoT industry players will showcase their applications and technologies including:

  • Alps Electric
  • Amazon Web Services*
  • Dassault Systems
  • Hitachi
  • IBM Research-Tokyo
  • Intel
  • SECOM
  • SIEMENS
  • Toshiba Healthcare Company
  • Toyota Motor
  • Tesla Motors*

*Amazon Web Services and Tesla Motors will have their booth at a SEMICON show for the first time ever.

The IoT conference programming will also feature speakers from the IoT key players including:

  • Amazon Japan – Kazufumi Watanabe, Vice President of Hardlines
  • Cisco Systems – Kazuhiro Suzuki, Managing Director, Cisco Consulting Services
  • Fujitsu – Chairman and Representative Director, FUJITSU LTD
  • Google – Shinichi Abe, Managing Director, Google for Work, Japan
  • IBM Japan – Toshifumi Yoshizaki, IBM Executive Staff, Watson
  • Microsoft Japan – Madoka Sawa, MTC Lead, Microsoft Technology Center
  • Nissan Motor Company – Haruyoshi Kumura, Fellow
  • Rakuten – Masaya Mori, Executive Officer and Representative, Rakuten Institute of Technology

Innovation Village is a new feature at SEMICON Japan that includes 20 emerging startups in an interactive exposition showcase arena. Attendees to the Innovation Village will gain key insights into new technologies and products, advanced research solutions, investment opportunities, as well as technology transfer and partnerships opportunities. The Innovation Village program will include start-up pitches and a “speed-dating” format for matchmaking between start-ups and venture capitals and corporate venture capitals.

Osamu Nakamura, president of SEMI Japan said “The World of IoT and Innovation Village bring new and fresh ideas, technologies, and partnership to SEMICON Japan visitors and exhibitors that are moving forward together to the IoT era.”

Platinum sponsors of SEMICON Japan 2015 include Applied Materials, Disco, and Tokyo Electron. Gold sponsors include Advantest, ASE Group, Daihen, Ebara, Hitachi Chemical, Hitachi High-Tech, JSR, Lam Research, Screen Semiconductor Solutions, and Tokyo Seimitsu.

For complete information of exhibits and programs, visit www.semiconjapan.org/en.