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At SEMICON Europa, attendees and exhibitors will delve into the technologies that shape the future of the microtech, nanotech, medtech and cleantech industries. Representing the entire supply chain from materials to electronic systems and services, 35 major European start-ups will participate in the Innovation Village and present their new technologies at SEMICON Europa.  The largest and most important semiconductor event in Europe, SEMICON Europa  will be held 7-9 October in the Grenoble location for the first time. The new three-day Innovation Village program will be the stage for emerging innovators, industry leaders, strategic investors, and venture capitalists to discuss the needs of the industry’s innovation engine. Attendees will gain insights on technology, capital, partnership, and collaboration strategies necessary for mutual success.

Innovation Village consists of a start-up exhibition (7-9 October), Silicon Innovation Forum (7 October) and Innovation Conference (8 October). As part of the Silicon Innovation Forum, all selected start-ups will have the opportunity to “pitch” to investors and SEMICON Europa visitors. The pitch session will be followed by a start-up panel discussion  “Fundraising for the Future Champions of European Electronics,” led by Jean-Pascal Bost of SATT-GIFT with panelists: Jacques Husser (Sigfox), Eric Baissus (Kalray), Serguei Okhonin (ActLight) and Mike Thompson (Hotblock Onboard).

The Innovation Conference, sponsored by Fidal Innovation, will bring together notable names in European innovation to discuss current practices and relevant funding issues facing semiconductor and high-tech start-ups today. Keynote speakers will include Nicolas Leterrier (Schneider Electric) on Innovation Practices and Dan Armbrust (Silicon Catalyst) on Lean Innovation. Christine Vaca (Gate1) will act as the conference chair.

“For the inaugural SEMICON Europa in Grenoble, our team was intent on developing a program that would highlight the strength of the local and the European ecosystems in innovation and new technology,” explains Anne-Marie Dutron, director of the SEMI Grenoble office. “At Innovation Village, visitors will discover the creativity of 35 European start-up companies, presenting their products, partnership and investment opportunities.”

Participating start-ups were chosen by a selection committee which included ten of the most recognizable venture firms in the industry: Applied Ventures LLC, Robert Bosch Venture GmbH, TEL Venture,3M Ventures, CEA Investissement, Samsung Ventures, Air Liquid Electronics, ASTER Capital), VTT Ventures, and  Capital-E.

Start-ups include ActLight (Switzerland), BlinkSight (France), BluWireless Technology (UK), Calao-Systems (France) and Silicon Line (Germany). For more information about Innovation Village, participating start-ups or about the Innovation Conference, please visit the SEMICON Europa website: www.semiconeuropa.org/Segments/InnovationVillage

All events in Innovation Village, including the three-day start-up exhibition, Silicon Innovation Forum and Innovation Conference will be available at no charge for all SEMICON Europa guests and visitors. The event will be co-hosted by SEMI Grenoble and Gate1. The mission of GATE1 is to support the creation of new technology-driven businesses by capitalizing on the proximity of numerous university laboratories and research centers. GATE1 offers programs for technology maturation, business incubation and business acceleration.

Kateeva  announced that it has closed its Series D round with $38 million in financing. The newest participant is Samsung Venture Investment Corporation (SVIC). Existing investors also contributed. They include: Sigma Partners, Spark Capital, Madrone Capital Partners, DBL Investors, New Science Ventures, and VEECO Instruments, Inc.

The company has raised more than $110 million since it was founded in 2008.

Kateeva makes the YIELDjet™ platform — a precision deposition platform that leverages inkjet printing to mass produce flexible and large-size OLED panels. The new funds will be used to support the company’s manufacturing strategy and expand its global sales and support infrastructure. Production systems are currently being built at the company’s facility in Menlo Park, Calif. to fulfill early orders.

The funding news coincides with the 2014 OLEDs World Summit taking place this week in Berkeley, Calif.

“Kateeva is a technology leader and has built a significant business in the OLED space,” said Michael Pachos, Senior Investment Manager at SVIC. “The company has demonstrated both a technical and business vision in driving adoption of OLED displays and lighting, and we look forward to contributing to its progress.”

“We believe that OLEDs on flexible substrates play a major role in the insatiable quest for ultra-durable, high-performance, and unbreakable mobile displays, and Kateeva has proven to hold the keys to a critical industry problem,” said Fahri Diner, Managing Director of Sigma Partners and a member of the Board of Directors of Kateeva. “Moreover, we are very excited about Kateeva’s impressive innovations that are poised to make large-panel OLED televisions finally an affordable reality — perhaps the Holy Grail of the display world. In partnership with SVIC, we’re delighted to offer continued support to Kateeva as they rapidly scale operations to support accelerating demand for OLED manufacturing solutions,” Diner continued.

Kateeva Chief Executive Officer Alain Harrus said: “SVIC’s investment speaks volumes about our technology’s enabling value to world-class OLED producers. It will reinforce our leading position and help serve all our customers better. Also, we appreciate our existing investors for their enduring commitment and trusted guidance. Thanks to their confidence in our technology and execution, mass producing OLEDs will be much smoother for leading display manufacturers.”

A new Department of Energy grant will fund research to advance an additive manufacturing technique for fabricating three-dimensional (3D) nanoscale structures from a variety of materials. Using high-speed, thermally-energized jets to deliver both precursor materials and inert gas, the research will focus on dramatically accelerating growth, improving the purity and increasing the aspect ratio of the 3D structures.

Known as focused electron beam induced deposition (FEBID), the technique delivers a tightly-focused beam of high energy electrons and an energetic jet of thermally excited precursor gases – both confined to the same spot on a substrate. Secondary electrons generated when the electron beam strikes the substrate cause decomposition of the precursor molecules, forming nanoscale 3D structures whose size, shape and location can be precisely controlled. This gas-jet assisted FEBID technique allows fabrication of high-purity nanoscale structures using a wide range of materials and combination of materials.

nanoscale-additive3

By allowing the rapid atom-by-atom “direct writing” of materials with controlled shape and topology, the work could lead to a nanoscale version of the 3D printing processes now revolutionizing fabrication of structures at the macro scale. The technique could be used to produce nano-electromechanical sensors and actuators, to modify the morphology and composition of nanostructured optical and magnetic materials to yield unique properties, and to engineer high performance interconnect interfaces for graphene and carbon nanotube-based electronic devices.

“This unique nanofabrication approach opens up new opportunities for on-demand growth of structures with high aspect ratios made from high-purity materials,” said Andrei Fedorov, the project’s leader and a professor in the Woodruff School of Mechanical Engineering at the Georgia Institute of Technology. “By providing truly nanoscale control of geometries, it will impact a broad range of applications in nanoelectronics and biosensing.”

nanoscale-additive2

Researchers have demonstrated the feasibility of the technique, and expect the three-year $660,000 grant to help them develop a fundamental understanding of how the process works, accelerate the rate of materials growth and provide improved control over the process. The research will include both theoretical modeling and experimental evaluation. Proof of principle for using thermally-energized gas jets as part of the FEBID technique was reported by Fedorov’s group in the journal Applied Physics Letters in 2011.

“Wherever electrons strike the surface, you can grow the deposit,” explained Fedorov. “That provides a tool for growing complex three-dimensional structures from a variety of materials with resolution at the tens of nanometers. Electron beam induced deposition is much like inkjet printing, except that it uses electrons and precursor molecules in a vacuum chamber.”

Two major challenges lie ahead for using the technique to manufacture 3D nanostructures: increasing the rate of deposition and eliminating the unwanted deposits of carbon that are formed as part of the process. To address these challenges, Fedorov and his team are using energetic jets of inert argon gas to clean substrate surfaces and carefully tune the energy of the desired molecules delivered in another jet to enhance the rate at which the precursor sticks to the substrate.

“If the energy of the jet is sufficiently high, the inert gas molecules striking the surface can knock away the adsorbed hydrocarbon contamination so that there is no parasitic carbon co-deposition,” he said. “We can also tune the properties of the precursor molecules so they stick more effectively to the surface. We have shown that we can increase the rate of growth by an order of magnitude or more while maintaining a high aspect ratio of deposited nanostructures.”

Overall, about two dozen materials have been successfully deposited using FEBID on different substrates, including semiconductors, dielectrics, metals and even plastics. The researchers also plan to create nanostructures containing more than one material, allowing them to create unique properties not available in each individual material. Examples might include new types of ferromagnetic materials and photonic bandgap structures with unique properties.

Fedorov’s group has used FEBID to fabricate low-resistance contacts to carbon nanotubes and graphene, a unique carbon-based material with attractive electronic properties.

Major technical challenges for the project include making tightly focused jets of thermally-energized precursor molecules to provide precise control of the fabrication. In operation, precursor molecules enter the reaction chamber from the micron-scale nozzle at sonic speeds, and accelerate in the vacuum environment to even greater speed, forming a molecular beam that impinges on the substrate. To make structures of the desired morphology, researchers will have to control the spreading of the generated molecular beam and its energy state at the point of contract with the substrate.

“We will be growing structures ranging in size from tens to hundreds of nanometers,” Fedorov noted. “This means we will not only have to confine electrons to very small regions, but we will also need to confine the precursor molecules to these same domains.”

The FEBID technique will likely not be used for high-volume fabrication because the process is difficult to scale up, Fedorov said. Accelerating the deposition rate will allow more rapid fabrication, but the 3D structures will still need to be produced one at a time. A partial solution to the scale-up challenge lies in the use of multiple electron beams and precursor jets operating in parallel.

The new technique will allow researchers to take better advantage of the unique properties of materials at the nanometer scale. Researchers will also have to account for those differences in developing the new manufacturing technique, as the interactions between electrons, precursor materials in the jet and substrate continually change with growth of the deposit.

“This research will open up the potential for some new discoveries in areas we may not be able to predict now,” said Fedorov. “We need to understand the basic physics of what is happening. That basic understanding could lead us to some truly unique applied capabilities, and the possibilities are almost limitless.”

Nanofluidic channels are useful for many biological and chemical applications, such as DNA sequencing, drug delivery, blood cell sorting and molecular sensing and detection. But in the effort to build a versatile lab-on-a-chip, it has been challenging to develop a wafer-scale nanochannel fabrication process compatible with CMOS technology.

At the upcoming International Electron Devices Meeting (IEDM), to be held December 9-11 in Washington, D.C., IBM researchers will report on a CMOS-compatible 200 mm wafer-scale sub-20nm nanochannel fabrication method that enables stretching, translocation and real-time fluorescence microscopy imaging of single DNA molecules.

Through the use of sacrificial XeF2 etching and various UV and e-beam lithography methods, sub-20-nm patterns in silicon were converted into macro-scale fluidic ports, micro-scale fluidic feed channels, and nano-scale channels for DNA imaging. Gradient nanopillars were located in the channels to stretch DNA molecules prior to imaging them. Fluid wasn’t pumped through the channels, but instead was transported by the force of gravity. The researchers say their techniques lead to highly manufacturable structures and can produce chips for a variety of biological applications.

A schematic of the nanochannel architecture. Grey represents silicon layers, while blue represents SiO2.  The silicon layers serve as sacrificial material.

A schematic of the nanochannel architecture. Grey represents silicon layers, while blue represents SiO2. The silicon layers serve as sacrificial material.

The etching sequence of the silicon layers is shown: A) silicon-patterning with sub-20 nm features (note the inset SEM electron microscope photo); B) capping-oxide deposition followed by vent-hole patterning: and C) XeF2 gas-phase etching of silicon patterns embedded in SiO2.

The etching sequence of the silicon layers is shown: A) silicon-patterning with sub-20 nm features (note the inset SEM electron microscope photo); B) capping-oxide deposition followed by vent-hole patterning: and C) XeF2 gas-phase etching of silicon patterns embedded in SiO2.

SEM electron microscope photo of silicon nanochannels.

SEM electron microscope photo of silicon nanochannels.

Optical photos showing A,B) nanochannels with vent holes on 1-2 µm SiO2 capping layer, on top of silicon patterns; and C,D) following gas etching and removal of silicon patterns.

Optical photos showing A,B) nanochannels with vent holes on 1-2 µm SiO2 capping layer, on top of silicon patterns; and C,D) following gas etching and removal of silicon patterns.

Wang (14.1) Fig.12 (450x338)

 

Jordan Valley Semiconductors Ltd., a supplier of X-ray based metrology tools for advanced semiconductor manufacturing lines, received another order for its recently introduced JVX7300LMI scanning X-ray in-line metrology tool for patterned and blanket wafers.  The system has been purchased for advanced process development and production ramp-up for 14nm and 10nm nodes.

The tool provides fully automated advanced metrology for epitaxial materials such as SiGe, Si:C/P and III-V on silicon FinFET structures, as well as high-k and metal gate stacks and other critical layers.

Isaac Mazor, JV CEO, said: “We are pleased to have been selected by key customers to support their FEOL (Front-End-Of-Line) process metrology.  This selection represents the customers’ confidence in Jordan Valley’s ability to provide valuable metrology solutions for their most demanding advanced applications, trusting first principle X-ray based metrology to provide unique process control solutions.”

Mazor added, “Advanced logic devices set new metrology challenges and requirements for key transistor level structure such as FinFET, Ge and III/V materials on silicon, as well as high-k and metal gate stacks used to enhance the transistor performance. Jordan Valley was able to meet the customers’ stringent process requirements in a short period of development time.”

“In choosing the JVX7300LMI platform, the customers acknowledged the significant contribution of the product in shortening the process development cycle, coupled with enabling process performance and extendibility to future technology nodes.” Mazor concluded, “We believe that the JVX7300LMI can be a strong contributor to assure high yield in the current and next generation process nodes.”

The JVX7300LMI is an X-ray metrology system for 14nm and 10nm nodes R&D and production ramp for FEOL applications such as SiGe, Si:C/P, FinFETs, high-k/metal gate and replacement channel materials such as Ge and III-V layers on Si. It is also used for the development and production of the emerging GaN on Si market.

JVX7300LMI


This tool enables scanning HRXRD, XRR and (GI)XRD measurements. HRXRD is capable of measuring epitaxial layer composition, thickness, density, strain and relaxation of single and multi-layer stacks. Additionally, with XRR and (GI)XRD channels, the tool provides information on the thickness, density, phase and crystallinity of ultra-thin layers typically used in the FEOL process. Unlike optical or spectroscopic tools, the HRXRD and XRR are first principle techniques that deliver accurate and precise results without calibration.

InGaAs is a promising channel material for high-performance, ultra low-power n-MOSFETs because of its high electron mobility, but multiple-gate architectures are required to make the most of it, because multiple gates offer better control of electrostatics. In addition, it is difficult to integrate highly crystalline InGaAs with silicon, so having multiple gates offers the opportunity to take advantage of the optimum crystal facet of the material for integration.

Transistors with high mobility channels will likely be required for the 10nm and 7nm device generations, scheduled to go into production in 2016/2016 and 2017/2018, respectively. InGaAs is a good candidate for NFETS, while germanium is the candidate of choice for PFET devices.

At the upcoming International Electron Devices Meeting (IEDM), to be held December 8-11 in Washington, D.C., a research team led by Japan’s AIST will describe how they built triangular InGaAs-on-insulator n-MOSFETs with smooth side surfaces along the <111>B crystal facet and with bottom widths as narrow as 30nm, using a metalorganic vapor phase epitaxy (MOVPE) growth technique. The devices demonstrated a high on-current of 930 µA/µm at a 300nm gate length, showing they have great potential.

 

Triangular transistors produced with MOVPE demonstrate a high on-current of 930 µA/µm at a 30nm gate length.

Triangular transistors produced with MOVPE demonstrate a high on-current of 930 µA/µm at a 30nm gate length.

The National Institute of Advanced Industrial Science and Technology (AIST) is a public research institution largely funded by the Japanese government. About 2300 researchers (about 2050 with tenure: about 80 from abroad) and a few thousands of visiting scientists, post-doctoral fellows, and students from home and abroad are working at AIST.  About 650 permanent administrative personnel and many temporary staff support research works of AIST.

At the International Electron Devices Meeting (IEDM) in December, IBM researchers will describe a silicon nanowire (SiNW)-based MOSFET fabrication process that produced gate-all-around (GAA) SiNW devices at sizes compatible with the scaling needs of 10nm CMOS technology. They built a range of GAA SiNW MOSFETs, some of which featured a 30nm SiNW pitch with a gate pitch of 60 nm.

Devices with a 90nm gate pitch demonstrated the highest performance ever reported for a SiNW device at a gate pitch below 100 nm— peak/saturation current of 400/976 µA/µm, respectively, at 1 V. Although this work focused on NFETs, the researchers say the same fabrication techniques can be used to produce PFETs as well, opening the door to a potential ultra-dense, high-performance CMOS technology.

IBM F2

The integration scheme allows for a reduced, more uniform diffusion distance, affording a more abrupt junction.

The integration scheme allows for a reduced, more uniform diffusion distance, affording a more abrupt junction.

A new two-step anneal process shows that the nanowires can be smoothened with no loss of density compared to planar processes.

A new two-step anneal process shows that the nanowires can be smoothened with no loss of density compared to planar processes.

The TEM electron microscope images above show: a) a cross section of a completed device through a gate, illustrating the spacer, epitaxial source/drain and contacts;  (b) the cross section of a silicon nanowire (SiNW) decorated with a high-Z film to better show the nanowire’s boundary. The effective SiNW diameter shown is 12.8 nm; (c) a close up of the region of interest indicated in a), showing that the source/drain is epitaxially regrown from the cut face of the nanowire. The lattice planes in the epi region are registered to that of the original SiNW channel (parallel red dashed lines).

The TEM electron microscope images above show: a) a cross section of a completed device through a gate, illustrating the spacer, epitaxial source/drain and contacts; (b) the cross section of a silicon nanowire (SiNW) decorated with a high-Z film to better show the nanowire’s boundary. The effective SiNW diameter shown is 12.8 nm; (c) a close up of the region of interest indicated in a), showing that the source/drain is epitaxially regrown from the cut face of the nanowire. The lattice planes in the epi region are registered to that of the original SiNW channel (parallel red dashed lines).