Category Archives: MEMS

December 20, 2012 – Ultratech has acquired the assets of Cambridge Nanotech, a developer and supplier of atomic-layer deposition (ALD) technology with hundreds of installed systems in the field. Financial terms were not disclosed.

The company says adding the ALD technology will expand its nanotechnology and IP portfolio, enabling it to address new areas within the electronics industry and entry into new markets such as biomedical and energy. "By increasing our IP and expanding our nanotechnology portfolio to new levels, we expect to generate a new revenue stream in existing and new markets," stated Ultratech chairman/CEO Art Zafiropoulo.

Cambridge Nanotech was founded in 2003 by Jill Becker based on her Ph.D work in ALD at Harvard University. Weeks ago Cambridge Nanotech was quietly put up on the auction block; an announcement by Gerbsman Partners, the firm retained by the firm’s main backer Silicon Valley Bank, noted that the company had ceased operations on November 9 and that an auction would take place on Dec. 14. The firm indicated Cambridge Nanotech’s sales from 2004-2011 increased at a 84% CAGR (to $18.7M in 2011, according to a local report), with initial profitability after the first year but "lumpy" since then. "Recent working capital constraints and an overly leveraged balance sheet" were cited as the reasons for the decision to sell the company’s assets.

The asset sale includes several ALD product and technology lines, in place at academic and manufacturing environments for a range of electronics, MEMS/MOEMS, display/lighting, and energy applications:

– "Savannah" — R&D lab equipment
– "Fiji" — R&D lab equipment with plasma and additional
– "Phoenix" and "Tahiti" — Production equipment for high-volume manufacturing
– "Preboost" — To proliferate the use of more precursors in any ALD system
– "Roll2Roll" — Fast ALD; high throughput; atmospheric ALD

Canon U.S.A., Inc. recently launched the FPA-3030i5+ i-line stepper, designed for the manufacturing of LEDs, MEMS and power semiconductors. The FPA-3030 platform is an upgrade to earlier Canon “FPA-3000 platform” steppers.  The FPA-3030i5+ features an overhauled software structure and electrical control system that allow application of optional advanced hardware (e.g., projection lens, wafer stage, and alignment system) that is not compatible with traditional FPA-3000 platform steppers.

The FPA-3030i5+ is capable of providing imaging resolution below 0.35mm, while maintaining overlay accuracy of less than or equal to 40nm and throughput equal to or in excess of 104 wafers per hour. 

The FPA-3030 platform allows the use of optional equipment designed for the processing of silicon (Si), sapphire (Al2O3), silicon carbide (SiC) and a wide variety of wafer materials used in  environmentally conscious device manufacturing. Optional equipment for the FPA-3030i5+ includes warped-wafer handling systems to allow processing of distorted substrates, and advanced image processing systems for clear substrates.

With the purchase of the optional Multi-Size Wafer Kit, the FPA-3030i5+ stepper can also be configured to process multiple wafer sizes, and can be equipped with other optional equipment to help improve productivity and efficiency.

IBM (NYSE: IBM) unveiled the seventh annual  "IBM 5 in 5" – a list of innovations that have the potential to change the way people work, live and interact during the next five years. The IBM 5 in 5 is based on market and societal trends as well as emerging technologies from IBM’s R&D labs around the world that can make these transformations possible.

This year’s IBM 5 in 5 explores innovations that will be the underpinnings of the next era of computing, which IBM describes as the era of cognitive systems. This new generation of machines will learn, adapt, sense and begin to experience the world as it really is. This year’s predictions focus on one element of the new era, the ability of computers to mimic the human senses—in their own way, to see, smell, touch, taste and hear.

These sensing capabilities will help us become more aware, productive and help us think – but not think for us. Cognitive computing systems will help us see through complexity, keep up with the speed of information, make more informed decisions, improve our health and standard of living, enrich our lives and break down all kinds of barriers—including geographic distance, language, cost and inaccessibility. 

“IBM scientists around the world are collaborating on advances that will help computers make sense of the world around them,” said Bernie Meyerson, IBM Fellow and VP of Innovation. “Just as the human brain relies on interacting with the world using multiple senses, by bringing combinations of these breakthroughs together, cognitive systems will bring even greater value and insights, helping us solve some of the most complicated challenges.”

Here are five predictions that will define the future:                                           

Touch: You will be able to touch through your phone 

Imagine using your smartphone to shop for your wedding dress and being able to feel the satin or silk of the gown, or the lace on the veil, all from the surface of the screen? Or to feel the beading and weave of a blanket made by a local artisan half way around the world? In five years, industries such as retail will be transformed by the ability to “touch” a product through your mobile device.  

IBM scientists are developing applications for the retail, healthcare and other sectors using haptic, infrared and pressure sensitive technologies to simulate touch, such as the texture and weave of a fabric — as a shopper brushes her finger over the image of the item on a device screen. Utilizing the vibration capabilities of the phone, every object will have a unique set of vibration patterns that represents the touch experience: short fast patterns, or longer and stronger strings of vibrations. The vibration pattern will differentiate silk from linen or cotton, helping simulate the physical sensation of actually touching the material.  

Current uses of haptic and graphic technology in the gaming industry take the end user into a simulated environment. The opportunity and challenge here is to make the technology so ubiquitous and inter-woven into everyday experiences that it brings greater context to our lives by weaving technology in front and around us. This technology will become ubiquitous in our everyday lives, turning mobile phones into tools for natural and intuitive interaction with the world around us.  

Sight: A pixel will be worth a thousand words 

We take 500 billion photos a year. 72 hours of video is uploaded to YouTube every minute. The global medical diagnostic imaging market is expected to grow to $26.6 billion by 2016. Computers today only understand pictures by the text we use to tag or title them; the majority of the information — the actual content of the image — is a mystery.  

In the next five years, systems will not only be able to look at and recognize the contents of images and visual data, they will turn the pixels into meaning, beginning to make sense out of it similar to the way a human views and interprets a photograph. In the future, “brain-like” capabilities will let computers analyze features such as color, texture patterns or edge information and extract insights from visual media. This will have a profound impact for industries such as healthcare, retail and agriculture.  

Within five years, these capabilities will be put to work in healthcare by making sense out of massive volumes of medical information such as MRIs, CT scans, X-Rays and ultrasound images to capture information tailored to particular anatomy or pathologies. What is critical in these images can be subtle or invisible to the human eye and requires careful measurement. By being trained to discriminate what to look for in images — such as differentiating healthy from diseased tissue — and correlating that with patient records and scientific literature, systems that can “see” will help doctors detect medical problems with far greater speed and accuracy. 

Hearing: Computers will hear what matters  

Ever wish you could make sense of the sounds all around you and be able to understand what’s not being said? 

Within five years, a distributed system of clever sensors will detect elements of sound such as sound pressure, vibrations and sound waves at different frequencies. It will interpret these inputs to predict when trees will fall in a forest or when a landslide is imminent. Such a system will “listen” to our surroundings and measure movements, or the stress in a material, to warn us if danger lies ahead.  

Raw sounds will be detected by sensors, much like the human brain. A system that receives this data will take into account other “modalities,” such as visual or tactile information, and classify and interpret the sounds based on what it has learned. When new sounds are detected, the system will form conclusions based on previous knowledge and the ability to recognize patterns. 

For example, “baby talk” will be understood as a language, telling parents or doctors what infants are trying to communicate. Sounds can be a trigger for interpreting a baby’s behavior or needs. By being taught what baby sounds mean – whether fussing indicates a baby is hungry, hot, tired or in pain – a sophisticated speech recognition system would correlate sounds and babbles with other sensory or physiological information such as heart rate, pulse and temperature.  

In the next five years, by learning about emotion and being able to sense mood, systems will pinpoint aspects of a conversation and analyze pitch, tone and hesitancy to help us have more productive dialogues that could improve customer call center interactions, or allow us to seamlessly interact with different cultures. 

Today, IBM scientists are beginning to capture underwater noise levels in Galway Bay, Ireland to understand the sounds and vibrations of wave energy conversion machines, and the impact on sea life, by using underwater sensors that capture sound waves and transmit them to a receiving system to be analyzed.

Taste: Digital taste buds will help you to eat smarter 

What if we could make healthy foods taste delicious using a different kind of computing system that is built for creativity?  

IBM researchers are developing a computing system that actually experiences flavor, to be used with chefs to create the most tasty and novel recipes. It will break down ingredients to their molecular level and blend the chemistry of food compounds with the psychology behind what flavors and smells humans prefer. By comparing this with millions of recipes, the system will be able to create new flavor combinations that pair, for example, roasted chestnuts with other foods such as cooked beetroot, fresh caviar, and dry-cured ham. 

A system like this can also be used to help us eat healthier, creating novel flavor combinations that will make us crave a vegetable casserole instead of potato chips.  

The computer will be able to use algorithms to determine the precise chemical structure of food and why people like certain tastes. These algorithms will examine how chemicals interact with each other, the molecular complexity of flavor compounds and their bonding structure, and use that information, together with models of perception to predict the taste appeal of flavors. 

Not only will it make healthy foods more palatable — it will also surprise us with unusual pairings of foods actually designed to maximize our experience of taste and flavor. In the case of people with special dietary needs such as individuals with diabetes, it would develop flavors and recipes to keep their blood sugar regulated, but satisfy their sweet tooth.   

Smell: Computers will have a sense of smell

During the next five years, tiny sensors embedded in your computer or cell phone will detect if you’re coming down with a cold or other illness. By analyzing odors, biomarkers and thousands of molecules in someone’s breath, doctors will have help diagnosing and monitoring the onset of ailments such as liver and kidney disorders, asthma, diabetes and epilepsy by detecting which odors are normal and which are not. 

Today IBM scientists are already sensing environmental conditions and gases to preserve works of art. This innovation is beginning to be applied to tackle clinical hygiene, one of the biggest challenges in healthcare today. For example, antibiotic-resistant bacteria such as Methicillin-resistant Staphylococcus aureus (MRSA), which in 2005 was associated with almost 19,000 hospital stay-related deaths in the United States, is commonly found on the skin and can be easily transmitted wherever people are in close contact. One way of fighting MRSA exposure in healthcare institutions is by ensuring medical staff follow clinical hygiene guidelines. In the next five years, IBM technology will “smell” surfaces for disinfectants to determine whether rooms have been sanitized. Using novel wireless “mesh” networks, data on various chemicals will be gathered and measured by sensors, and continuously learn and adapt to new smells over time. 

Due to advances in sensor and communication technologies in combination with deep learning systems, sensors can measure data in places never thought possible. For example, computer systems can be used in agriculture to “smell” or analyze the soil condition of crops. In urban environments, this technology will be used to monitor issues with refuge, sanitation and pollution – helping city agencies spot potential problems before they get out of hand.  

Click here to see an infographic that illustrates the IBM 5 in 5 prediction.

December 14, 2012 – Joining the growing chorus of industry watchers lowering their outlooks on the semiconductor sector, Gartner has reduced both its 2012 and 2013 forecasts for semiconductor sales but is remarkably more bullish on prospects in 2014.

"The looming fiscal cliff, ongoing European debt crisis, slower emerging market growth and regional tensions have all played a part in reduced growth projections for semiconductor revenue in both 2012 and 2013," stated Peter Middleton, principal analyst at Gartner. He also pointed to an inventory buildup; levels were already high, and with softness in PC demand, "simply overshot demand."

The firm now sees global semiconductor revenues slipping by -3% in 2012 to $298B, vs. its previous expectation of essentially flat back in September. Chip sales in 2013 will increase about 4.5% in 2013 to $311B, instead of the expected 6.9% climb to $330B.

Beyond PC chip demand, another dent to the market was continued softness in DRAM pricing; Gartner thinks this won’t recover until 2H13 with supply slowing down and actually creating undersupply. "This should prove a turning point for the semiconductor industry," the firm says; memory will enjoy 15% growth in 2013, boosting total semiconductor revenue in 2014 by 9.9% to $342B — that’s noticeably better than the 5.6% growth Gartner previously foresaw for 2014.

Two chip areas will see better demand than other segments in 2013: NAND memory and ASICs, growing 17% and about 9% respectively, thanks to usage in Apple devices (Gartner counts Apple’s A4/A5/A6 custom and exclusive chips as ASICs). New video game consoles coming in late 2012 and 2013 will also help boost ASIC demand.

One area expected to stay weak overall is PCs, declining -2.5% in 2012 and continuing to be soft in 2013. One exception: ultramobile PCs, which will "grow strongly off a small base," Gartner says. Blame the economic malaise, within which end-users are choosing to hang onto older machines and not upgrade; if they do get a new computer it’s often a tablet instead.

Speaking of tablets, look for eye-popping 38% growth in 2013 to 207M units — that’s an extra 30M units more than Gartner foresaw three months ago. Credit the successes of the Amazon Kindle Fire, Google Nexus 7, and Apple iPad Mini, which are showing that there is a market for smaller tablets at the right price. Even "white-box" tablet demand is stronger than expected, Gartner says.

One end-market category with mixed results is the mobile phone sector. Gartner sees output softening in 2012 and into 2013 (still up 33% in 2013 though), again blaming the economy for reducing short-term demand. However, utility/basic smartphones are seeing better popularity, particularly Android-based devices and in emerging regions. Gartner points out.

Gartner’s new forecast for worldwide semiconductor revenues is
lower for 2012 and 2013, but higher in 2014. (Source: Gartner)

In an IC fab, cycle time is the time interval between when a lot is started and when it is completed. The benefits of shorter cycle time during volume production are well known: reduced capital costs associated with having less work in progress (WIP); reduced number of finished goods required as safety stock; reduced number of wafers affected by engineering change notices (ECNs); reduced inventory costs in case of a drop in demand; more flexibility to accept orders, including short turnaround orders; and shorter response time to customer demands. Additionally, during development and ramp, shorter cycle times accelerate end-of-line learning and can result in faster time to market for the first lots out the door.

Given all the benefits of reducing cycle time, it’s useful to consider how wafer defect inspection contributes to the situation. To begin with, the majority of lots do not accrue any cycle time associated with the inspection, since usually less than 25 percent of lots go through any given inspection point. For those that are inspected, cycle time is accrued by sending a lot over to the inspection tool, waiting until it’s available, inspecting the lot and then dispositioning the wafers. On the other hand, defect inspection can decrease variability in the lot arrival rate—thereby reducing cycle time.

Three of the most important factors used in calculating fab cycle time are variability, availability, and utilization. Of these, variability is by far the most important. If lots arrive at process tools at a constant rate, exactly equal to the processing time, then no lot will ever have to wait and the queue time will be identically zero. Other sources of variability affect cycle time, such as maintenance schedules and variability in processing time, but variability in the lot arrival rate tends to have the biggest impact on cycle time.

In the real world lots don’t arrive at a constant rate and one of the biggest sources of variability in the lot arrival rate is the dreaded WIP bubble—a huge bulge in inventory that moves slowly through the line like an over-fed snake. In the middle of a WIP bubble every lot just sits there, accruing cycle time, waiting for the next process tool to become available. Then it moves to the next process step where the same thing happens again until eventually the bubble dissipates. Sometimes WIP bubbles are a result of the natural ebb and flow of material as it moves through the line, but often they are the result of a temporary restriction in capacity at a particular process step (e.g., a long “tool down”).

When a defect excursion is discovered at a given inspection step, a fab may put down every process tool that the offending lot encountered, from the last inspection point where the defect count was known to be in control, to the current inspection step.  Each down process tool is then re-qualified until, through a process of elimination, the offending process tool is identified.

If the inspection points are close together, then there will be relatively few process tools put down and the WIP bubble will be small.  However, if the inspection points are far apart, not only will more tools be down, but each tool will be down for a longer period of time because it will take longer to find the problem.  The resulting WIP bubble can persist for weeks, as it often acts like a wave that reverberates back and forth through the line creating abnormally high cycle times for an extended period of time. 

Consider the two situations depicted in Figure 1 (below). The chart on the top represents a fab where the cycle time is relatively constant. In this case, increasing the number of wafer inspection steps in the process flow probably won’t help.  However, in the second situation (bottom), the cycle time is highly variable. Often this type of pattern is indicative of WIP bubbles.  Having more wafer inspection steps in the process flow both reduces the number of lots at risk, and may also help reduce the cycle time by smoothing out the lot arrival rate.

 

Because of its rich benefits, reducing cycle time is nearly always a value-added activity. However, reducing cycle time by eliminating inspection steps may be a short-sighted approach for three important reasons. First, only a small percentage of lots actually go through inspection points, so the cycle time improvement may be minimal. Second, the potential yield loss that results from having fewer inspection points typically has a much greater financial impact than that realized by shorter cycle time. Third, reducing the number of inspection points often increases the number and size of WIP bubbles. 

For further discussions on this topic, please explore the references listed at the end of the article, or contact the first author.

Doug Sutherland, Ph.D., is a principal scientist and Rebecca Howland, Ph.D., is a senior director in the corporate group at KLA-Tencor.

Check out other Process Watch articles: “The Dangerous Disappearing Defect,” “Skewing the Defect Pareto,” “Bigger and Better Wafers,” “Taming the Overlay Beast,” “A Clean, Well-Lighted Reticle,” “Breaking Parametric Correlation,” “Cycle Time’s Paradoxical Relationship to Yield,” and “The Gleam of Well-Polished Sapphire.”

References

1.       David W. Price and Doug Sutherland, “The Impact of Wafer Inspection on Fab Cycle Time,” Future Technology and Challenges Forum, SEMICON West, 2007.

2.       Peter Gaboury, “Equipment Process Time Variability: Cycle Time Impacts,” Future Fab International. Volume 11 (6/29/2001).  

3.       Fab-Time, Inc.  “Cycle Time Management for Wafer Fabs:  Technical Library and Tutorial.”

4.       W.J. Hopp and M.L. Spearman, “Factory Physics,” McGraw-Hill, 2001, p 325.

December 11, 2012 – Our slideshow of 14 interesting papers at this week’s IEEE International Electron Devices Meeting (IEDM 2012), did not include what are often some of the more intriguing papers — the ones that come in late and are unavailable for preview. This year there are four such papers, and we’re now able to give you a sneak peek at them, being unveiled starting this afternoon and through the week at IEDM in San Francisco.

ZnNO for next-gen displays

Stability degradation, especially at high mobility regime, limits the application of oxide semiconductors in next-generation displays. Zinc oxynitride, with its high mobility characteristics and small bandgap, is getting attention as an alternative for pixel-switching devices in ultra-high definition and large-area displays. Researchers from Samsung Advanced Institute of Technology and Seoul National University will describe ZnON-thin film transistors (TFTs) with field effect mobility near 100 cm2/Vs and operation stability(< 3 V) under light-illumination bias-stress. The uniformity is observed to be suitable for display applications, and with mobility performance comparable to that of polysilicon (poly-Si). (#5.6, "High mobility zinc oxynitride-TFT with operation stability under light-illuminated bias-stress conditions for large area and high resolution display applications")

Structure of ES-type ZnON-TFT fabricated by photolithography. (left) Top view from optical microscope and (b) cross-sectional TEM image at the vicinity of contact region.

SnO transistor for BEOL-CMOS I/Os

Renesas Electronics’ LSI Research Laboratory has devised a new P-type amorphous SnO thin-film transistor with high Ion/Ioff ratio (>104) as a component to complement N-type IGZO transistors for on-chip voltage-bridging BEOL-CMOS I/Os on conventional Si-LSI Cu-interconnects. (The transistor gives standard LSIs a special add-on function to control high-voltage signals directly.) Their BEOL-transistor (BEOL-Tr) uses a wide-band-gap InGaZnO (IGZO) as the channel and cap-SiN/Cu-interconnect as the gate dielectric/bottom-gate electrode. Normally-off transistor characteristics with relatively high mobility, high-Vd tolerance, high Ion/Ioff ratio, have made the BEOL-Tr attractive for voltage-bridging devices mountable onto advanced MCUs and SoCs. Realization of P-type transistors to complement IGZO-based NFETs and form BEOL-CMOS is also a key function for more sophisticated applications, they claim. (#18.8, "High On/Off-ratio P-type Oxide-based Transistors Integrated onto Cu-interconnects for On-chip High/Low Voltage-bridging BEOL-CMOS I/Os")

XTEM of the integrated device structure with G/D offset of 0.5μm. SnO is integrated onto Cu interconnect to realize P-type BEOL-Tr with high Ion/Ioff ratio. Device integration requires only one mask addition.

III-V TFETs for the 7nm node

III-V tunneling field-effect transistors (TFET) for low-voltage logic applications have gained attention, but their nonoptimized carrier tunneling limit drive currents. Researchers from the Rochester Institute of Technology and SEMATECH set out to map III-V Esaki tunnel diode performance, engineering tunnel diodes (TD) with ultrahigh-current densities while maintaining large peak-valley current ratios. In this paper, they report a comprehensive experimental benchmarking of an Esaki diode, including GaAs, In0.53Ga0.47As, InAs, InAs0.9Sb0.1/Al0.4Ga0.6Sb, and InAs/GaSb. Engineering the hetero-junctions enhances peak and Zener current densities beyond homo-junctions, to a record 2.2 MA/cm2 and 1.1 MA/cm2 (-0.3 V), laying the groundwork for III-V TFETs at the 7nm technology node. (#27.7, "Benchmarking and Improving III-V Esaki Diode Performance With a Record 2.2 MA cm2 Current Density to Enhance TFET Drive Current")

(a) Cross-section of a TD fabrication process flow. (b) SEM image of a characteristic submicron TD after mesa etch. (c) schematic of a fully-fabricated TD.

Integrated CMOS silicon photonics on 90nm

IBM researchers in the US and Europe are demonstrating the first sub-100nm technology (a current 90nm base SOI logic technology) that allows monolithic integration of optical modulators and germanium photodetectors — putting optical and electrical circuits side-by-side on the same chip. The resulting 90nm CMOS-integrated nano-photonics technology is optimized for analog functionality to yield power-efficient, single-die multichannel wavelength-mulitplexed 25Gbps transceivers. (IBM has a fuller description of the technology in a separate press release.) (#33.8, "A 90nm CMOS Integrated Nano-Photonics Technology for 25Gbps WDM Optical Communications Applications")

Cross-sectional SEM view of a 90nm CINP metal stack with Ge PD embedded into the front-end. Zoomed-in image of a photodetector is shown on top left. Optical microscope top-down image is shown on the low left.

Angled view of a portion of an IBM chip showing blue optical waveguides transmitting high-speed optical signals and yellow copper wires carrying high-speed electrical signals.

CMOS is running out of steam, but what comes next? At the International Electron Devices Meeting in San Francisco, An Chen of GLOBALFOUNDRIES presented a survey of emerging nanoelectronic devices, which he divided into two categories: Charge-based and non-charge based.

Chen is well qualified to speak on the topic. In 2009, Chen was an assignee to the National Research Initiative (NRI) program of the SRC to work on emerging logic devices, including graphene electronics and spintronics. He is co-chair of the emerging research device group of the International Technology Roadmap for Semiconductors (ITRS). He is also an expert on memory technology, responsible for collaboration on emerging memories with industry consortia such as imec and SEMATECH.

“We can do better using better materials or device structures with better electrostatics (with existing CMOS technology),” Chen said, “but, facing fundamental limits, we have to ask ourselves ‘What are the solutions that may be available beyond CMOS?’”

One of the major challenges for scaling is escalating power density. “If we continue this trend, we’re going to some ridiculous number (see chart). That could limit how small we can shrink the device. That’s the real limit for the scaling,” Chen said. “We cannot really eliminate power leakage and we cannot reduce the supply voltage in proportion to device dimensions. We have to look for devices that may consume less power during switching,” he added.

To this end, low power beyond-CMOS devices have been developed based on novel state variables and/or computation mechanisms. Chen said that charge-based emerging devices may enable low-power computation by making the FET transition steeper or introducing new switching concepts. Another class of devices based on spin are another option; spintronics are one of the main types of noncharge emerging devices.

Chen provided an overview of the leading nanoelectronic devices, noting key features and potential challenges.

Tunneling FET (TFET)

The tunneling FET employs quantum mechanical band-to-band tunneling mechanism, and offers low Vdd, low power and an FET structure that is compatible with CMOS technology and infrastructure.

Challenges include: low saturation current, a lack of ability to extend low SS (subthreshold slope) over a wide current range; difficult engineering of the source tunneling region with regard to junction abruptness, bandgap, carrier effective mass, etc.; challenges with enhancing gate control on the internal E-field; and problems with interface states.

Impact Ionization MOS (IMOS)

IMOS devices employ a gated p-i-n structure operated in the reverse bias regime, where control of the gate impact ionization enables a steep increase of current via carrier multiplication. Key features include a steep sub-threshold slope and CMOS compatibility.

 

Challenges: IMOS devices are intrinsically slow due to the statistical avalanche charge multiplication process, and speed limitations due to carrier multiplication delay and statistical retardation delay. There are also limitations in scaling the intrinsic supply voltage, and susceptibility to hot carrier degradation.

Nano-electro-mechanical Switch (NEMS)

Advantages of NEMS, which operate as a mechnical switch with a cantilever beam as shown, include zero leakage and  zero sub-threshold swing (in principle), high temperature tolerance, immunity to electromagnetic shocks, and compatibility with CMOS.

Challenges with NEMS include: Slow switching speed related to the beam movement and oscillatory pullout time; anoscale contact reliability; surface forces that causing sticking; tunneling-limited scaling; high pull-in voltage, and variability control.

Negative-Cg FET

Key features of the negative common gate FET: steep SS based on collective effects and internal feedback mechanisms; low-power solutions are possible; it’s compatible with CMOS; there have been demonstrations of negative capacitance in ferroelectric dielectrics and <60mV/dec SS in neg-Cg FET.

Challenges: the industry needs to identify appropriate materials (oxides and ferroelectrics) for the best swing with minimal hysteresis, integration of high quality single crystalline ferroelectric oxides on silicon; scalability has yet to be proven; speed is in question.

Resonant Tunneling Diodes (RTD)

Key features: Inherently high speed; negative differential resistance (NDR); integrating a pair of RTD with CMOS gate achieves bi-stable logic operation; precise control of layer thickness is important for fabrication.

Chen provided several examples of RTD device applications: Monostable-bistable transition logic elements, tunneling-based SRAMs and RTD-based spin-filters.

Single Electron Transistor (SET)

Key features: High speed; potentially high device density; potentially high power efficiency; novel functionalities and applications; compatibility with CMOS

Challenges include: size-temperature tradeoff; modest to low gain; large threshold voltage variation; parasitic capacitance; low output current and high output impedance; limited fan-out; low noise immunity; immature fabrication process.

Mott FET

Key features: FET-type structure with CMOS compatibility; fast phase transition speed; good scalability.

Chen said there has been limited progress on FET recently, although two-terminal Mott devices have been explored for memory applications. Other challenges include: transition temperature; a lack of fundamental understanding of the gate oxide (functional channel interface and the local band structure changes under E-field is limited); Mott transition often coupled with thermal effects and structural changes.

Quantum Cellular Automata (QCA)

QCA, which has been experimentally demonstrated with semiconductor, molecular and magnetic dots could provide potentially low-power, novel information processing and transfer mechanisms, and majority gate operation.

Challenges include operating temperature and patterning at extreme scales.

Atomic Switch

The atomic switch is based on the formation/annihilation of a metallic atomic bridge between two electrodes, which can be gate-controlled.

Key features: Highly scalable; low operation voltage and power; two-terminal device for memory is the same as the conductive-bridge RAM (CBRAM); it’s a relatively simple process with potentially low cost, and is 3D stackable.

Challenges: Improve performance of 3-terminal devices (speed, endurance, uniformity); stability and variability may be concerns; speed is determined by ionic transport and electrochemical reactions at the reactive electrode interface; and a better understanding of the operation mechanisms is needed.

SpinFET

Key features: Spin degree of freedom enables additional signal modulation and control; FET-type structure and compatibility with CMOS; dissipation-less transport in theory; and nonvolatility and programmability.

Challenges: Magnetic materials and processing; requires high efficiency of spin injection and detection for sufficient on/off ratio; strength of gate modulation of spin-orbit interaction; and spin relaxation and lifetime.

Other Spin Transistor concepts include spin-MOSFETs, nonmagnetic spin transistors, non-ballistic spinFETs, and magnetic bipolar transistors.

Nanomagnet Logic (NML)

With NML, logic bits are encoded in magnet polarization directions and computation is by magnetic coupling. Key features:  Majority logic operation; room-temperature operation; potentially low switching energy; nonvolatility; potentially zero standby power; and regularity in layout and design, which makes novel architectures more feasible.

Challenges: Clocking field design and optimization; defect tolerance (e.g., misalignment); slow switching speed; scalability in question; layout efficiency; wire crossing.

Chen noted that room-temperature majority logic gate and cascaded logic operation based on NML have been demonstrated, and that a transition from in-plane to perpendicular magnetization may further improve NML operations.

Spin-Transfer-Torque (STT) for Logic

STT for logic, which is enabled by a magnetic tunnel junction (MTJ), can be a  majority logic gate based on phase locking of STT oscillators, or it can be based on STT switching in a multi-terminal magnetic tunnel junction (e.g., separate writing and sensing paths of MTJ and third-terminal controls).

Key features: Leverages technologies from STT-RAM; potentially low power; multiple logic states possible; non-volatility and programmability; STT oscillator may provide clock functions; and it may enable novel architectures and designs based on combined logic and memory functions.

Challenges: Material and integration; reducing switching current and power; and impedance mismatch with CMOS.

Chen said many conceptual device proposals are supported by device and circuit models and there have been an increasing number of experimental demonstrations, plus significant effort on architectural design.

Spin Wave Logic

With spin wave logic, logic information is  encoded in spin wave phase or amplitude and computation is by wave interference. Key features:  Parallel data processing on multiple frequencies on the same device; potentially low-power operation; integration with magneto-electric cells enables nonvolatile information storage; majority logic gate operation; and information transmission without charge transfer and potential interconnect solution for spintronic devices.

Challenges: Efficiency and power consumption of spin wave generation; spin wave signal degradation during propagation along spin waveguide; low group velocity and speed of signal propagation (~ 107 cm/s); device scalability limited by spin wave length; and there’s the potential for inductive cross-talk.

Chen said prototype spin wave logic devices have been demonstrated, including wave generation, propagation, and detection.  

Domain Wall Logic

Information is stored in a movable domain wall in ferromagnetic wires. It’s an all metallic logic, with potentially low power. Challenges include a high current to drive domain wall migration, a relatively slow switching speed, and the need for an external clock.

All Spin Logic

Key features: Magnets inject spin + spins switch magnets; uses both analog (spin current) and digital (bistable magnet) properties; potentially very low power; low voltage clocking operation; and suitable for non-Von Neumann architectures.

Challenges: Room-temperature switching in a multimagnet networks interacting via spin currents; Introduction of high anisotropy magnetic materials into demonstration; proper choice of channel materials; and current density. So far it’s only theory without direct experimental demonstrations

Bi-layer pseudo-Spin FET (BiSFET)

BiSFETs are based on exciton condensation in bi-layer graphene. It potentially offers low power and fast speed, but challenges exist in terms of operating temperature, device fabrication (e.g., graphene and dielectric quality, alignment, thickness control, etc.), and a low noise margin.

Attendees at this year’s International Electron Devices Meeting (IEDM) were delighted and perhaps somewhat horrified when the plenary speaker popped some electronics gear in his mouth and proclaimed, “It tastes like chicken!” The speaker, John Rogers from the University of Illinois at Champaign-Urbana, was demonstrating the edible nature of what he called transient electronics, which are designed from elements that rapidly decompose and are harmless to the human body and to the environment. One possible application of such bio-integrated electronics: They could be placed below a suture and provide enough heat through a resistive element to kill bacteria over a two week period. Bacteria sewn into the body during an operation are often the cause of a return trip to the hospital and delayed recovery.

He demonstrated that a very thin layer of silicon will dissolve in water fairly rapidly, in a matter of hours, turning into a salicylic acid. Circuits were completed with silicon dioxide as a gate dielectric and insulator and Manganese as the interconnect and resistor material. Levels were well below the FDA’s recommended daily allowance. Silk, already approved by the FDA for such applications, was used as the substrate. “You don’t want to chew,” Rogers quipped during his demonstration.

He said other applications of transient electronics include the use of sensors in chemical spills, which would monitor the presence of the chemical over time and then dissolve away, and even in consumer electronics, where lifetime would be measured in years instead of weeks.

Rogers also described another class of bioelectronics he called silicon membranes. By making silicon-based electronics thin enough, they can be stretchable. With a serpentine design, an applied strain of 30% induces strains that are less than 0.65%. These devices can conformally laminate onto the surface of the skin, in a manner that is mechanically invisible to the user, much like a temporary transfer tattoo. The systems, referred to as epidermal electronics, attach intimately and physically couple to rough skin surfaces, via van der Waals forces alone, with the ability accommodate natural and induced motions, Rogers noted in the accompanying paper.

Other bioelectronic applications include brain surgery, interfaces for human/computer control systems, skin-based physiological status monitors, high resolution electrical mapping systems for electrocorticography, and “instrumented” multifunctional balloon catheters for cardiac ablation therapy.

Rogers provides an overview of transient applications in this video and more details on his website.

December 10, 2012 – Japanese consumer electronics giants Sony and Toshiba have shrugged off weak financial performances and increased their investments in new products to revitalize their businesses, notes IHS. Sony’s spending on semiconductors will rise about 5% in 2013 to $8.4B and will just barely increase in 2014 (0.1%), while Toshiba will spend about 2% more in 2013 (to $6.1B) and over 6% in 2014 ($6.5B). That’s in contrast to other major Japanese electronics OEMS — Panasonic and Sharp will both pull back their investments in the next two years.

"All the Japanese consumer electronics OEMs are struggling financially, prompting them to take measures to cut costs in order to shore up their profits," stated Myson Robles-Bruce, senior analyst for semiconductor spending and design activity at IHS. "But even in these grim circumstances, Sony and Toshiba remain optimistic about the future, and are taking steps to invest in innovative products."

Economic slowdown in various key global markets, lower demand in certain product segments, and increased competition from South Korea and China have weighed down Japan’s major consumer electronics manufacturers; all four aforementioned OEMs are projected to lose money this year on collectively -7% lower sales, IHS notes. Sony, for example, has issued bonds twice this year to raise funding (even as its credit rating plummeted), is eliminating up to 10,000 jobs in the current fiscal year, and selling off manufacturing plants and JVs. "The Japanese consumer electronics companies face a changed marketplace, due to the rising influence of Apple and other competitors that have redefined some of the product segments or else simply just taken away share in key areas," noted Robles-Bruce.

Nonetheless, Sony and Toshiba made splashes at CEATEC in October, Japan’s version of the big US Consumer Electronics Show (CES), he notes. Sony demo’d everything from smartphones and tablets to PCs, cameras, televisions, home networking, and storage equipment. Highlights included the Bravia 4K LCD TV and new hybrid PCs that can be used as either tablets or laptops. Toshiba, meanwhile, showed off its own 4K resolution TV, as well as ultrabooks and tablets. Products were on display in small, medium, and large screen sizes. It also introduced new REGZA HD TVs with built-in DVR capabilities.

Will these investments in new technologies and products pay off for the struggling Japanese OEMs? IHS sees a mixed bag: Sony’s sales are expected to rebound 3.7% in 2013, but Toshiba’s sales will slip another -1%, and declines are expected to continue at Panasonic and Sharp.

The real question, according to Robles-Bruce, is whether these persistent declines can be overcome or if they represent a long-term trend. "The Japanese consumer electronics companies face a changed marketplace, due to the rising influence of Apple and other competitors that have redefined some of the product segments or else simply just taken away share in key areas," he writes. "Based upon the current financial evidence, it appears as though total revenue for Sony might be higher for next year, although estimates for Toshiba actually show a slight decline."

  2012 2013 2014
Sony $7,979    $8,352 $8,363
Toshiba   $6,025 $6,148 $6,535

Net semiconductor spend forecast for Sony and Toshiba, in US $M. (Source: IHS iSuppli)

December 6, 2012 – Semiconductor equipment demand is persistently sluggish as the industry takes a break from a "multiyear expansion period" to digest recent investments and wrestle with a broader economic slowdown. But make no mistake: leading-edge technology investments are still happening, and growth will return in the typical cyclical pattern, predicts SEMI in its updated year-end forecast, issued this week at SEMICON Japan.

Sales of semiconductor manufacturing equipment overall is now seen declining -12.2% in 2012 to $38.22B, after a 9% increase in 2011 to $43.53B and a 151% spike in 2010 to $39.92B, according to SEMI’s updated numbers. SEMI’s midyear forecast released at SEMICON West called for a -2.6% in overall equipment sales to $42.38B, followed by a 10.2% growth rebound in 2013. A significant downgrade had been expected, as after a strong early part of the year monthly data trends in semiconductor equipment demand have continued to turn sour.

"Sales of semiconductor manufacturing equipment in 2012 reflect significant investments over the prior two years, normal patterns of industry cyclicality and a slowdown in the broader economy," stated SEMI president/CEO Denny McGuirk. "What’s more important is that technology investments at the advanced nodes and in leading-edge packaging remain important drivers, and when market confidence returns, we expect capacity investments to increase."

Forecast by region. (Source: SEMI)

By region, only two areas will see any growth in 2012: Taiwan (12.7% to $9.60B) and South Korea (10.7% to $9.59B). Both will leapfrog the North American market, which is seen sliding -14% to $7.95B. Biggest declines will be in the smaller regions: Rest-of-World (-38% to $2.12B), Europe (-36% to $2.68B), and Japan (-36% to $3.72B). Among the drivers in Korea’s market are obviously numerous investments by Samsung (Lines 16, S1-A, and S1-C, and technology upgrades to other lines) and Hynix (upgrades to M10 and M11+M4, and the ramp of M12), noted Lara Chamness from SEMI Industry Research and Statistics. In Taiwan, TSMC is pouring resources into Fab 12, Fab 14, and Fab 15. "Other smaller device manufacturers are making non-trivial investments in the region," she added.

By equipment type, 2012 is being weighted down by the wafer processing segment, by far the largest segment, at nearly a -15% dropoff from 2011. The backend categories will decline but only about -5%, while the "other" category (facilities, mask reticles, other tools) will actually grow about 6%.

The picture brightens somewhat in 2013 with a deceleration of decline, -2.1% to $37.42B. By region there will be slight to moderate growth in China, Taiwan, and Japan, but offset by a -10% dropoff in Korean investments, SEMI predicts. By technology, the tables will turn: wafer processing will actually sneak into the black (0.3%), but backend categories will weigh down the overall picture.

Return to true growth will finally arrive in 2014, with 12.4% growth to $42.08B. All regions, and for all equipment types, will enjoy increased sales generally in the low-teens, predicts SEMI.

Forecast by equipment type. (Source: SEMI)