Category Archives: MEMS

May 24, 2011 — Analog Devices Inc. (ADI) released the ADXL206 high precision, low power, dual-axis iMEMS accelerometer with signal conditioned analog voltage outputs. "Instead of using additional temperature compensation circuitry, ADI’s design techniques ensure that high performance is built into the microelectromechanical system (MEMS)," said Wayne Meyer, marketing and applications manager, MEMS/Sensors Technology Group, Analog Devices.

Because of the designed-in temperature compensation, quantization error and non-monotonic behavior are essentially eliminated, and temperature hysteresis is typically less than 2mg over the entire -40° to +175°C temperature range, said Meyer.

The single-chip ADXL206 measures acceleration with a full-scale range of ±5g and measures both dynamic acceleration such as tilt and static acceleration such as gravity. Offering a guaranteed operating temperature range of -40° to +175°C and excellent overall stability, the ADXL206 is well suited for geological downhole tools and other extreme high-temperature industrial applications. The ADXL206 MEMS device is compact, with lower power consumption (from over 10 to under 0.5mA per axis), enabling more information collection in constricted downhole regions.

The ADXL206 iMEMS accelerometer has a typical noise floor of 110 μg/√Hz, allowing signals below 1mg (0.06° of inclination) to be resolved in tilt sensing devices using narrow bandwidths (<60 Hz). 0.5-2.5kHz bandwidths can be selected to suit the application.

ADXL206 iMEMS accelerometer features:

  • -40° to +175°C temperature range
  • 1 mg resolution at 60Hz
  • Low power: 700μA at VS = 5V (typical)
  • High zero g bias repeatability
  • High sensitivity accuracy
  • 3500 g shock survival
  • 13 × 8 × 2mm, 8-lead, side-brazed ceramic dual in-line package (SBDIP) package

ADI also produced the AD8229, 1.0-nV/√Hz high-temperature instrumentation amplifier for high-temperature applications.

Analog Devices recently won a US International Trade Commission (ITC) ruling that found that Knowles Electronics infringed ADI’s Wafer Anti-Stiction Application (WASA) patent, U.S. Pat. No. 7,364,942 on its MEMS microphone technology.

ADI is a leader in data conversion and signal conditioning technology. Download data sheets and view product pages at http://www.analog.com/ADXL206

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May 23, 2011 — The MEMS Industry Group (MIG) is organizing the inaugural "MEMS in the Machine" DemoZone at SEMICON West, on Tuesday, July 12 from 12:45 to 2pm.

SEMICON West, hosted by SEMI, will take place July 12-14 in San Francisco.

MIG members will demo cool applications that rely on MEMS technology, like smartphones and video games, gesture-based IPTV controllers, and other working consumer applications built with MEMS inertial sensors, optical MEMS, micro-mirrors, silicon microphones and more. "New MEMS" — a sector comprising MEMS devices for mobile and consumer applications — will grow by 157.4% in 2011, according to IHS iSuppli.

MIG’s "MEMS in the Machine" DemoZone is a way to show the semiconductor industry compelling examples of MEMS in action, according to the organizers. MEMS are an emerging technology sector within the industry, and share some processes, materials, and packaging technologies with mainstream chips.

Maps of the DemoZone will be available for SEMICON West attendees, and the MEMS companies will have designated booth space to share information on the product and company.

For a sample list of products that integrate MEMS, check out the MEMS in the Machine page: http://www.memsindustrygroup.org/i4a/pages/index.cfm?pageid=3933

MIG will also host "The Future of MEMS: Solutions for Moving from a Niche to a Mainstream Business" on July 12 at 10:30am–12:30pm during the Extreme Electronics TechXPOT, in the South Hall of SEMICON West. Teledyne DALSA Semiconductor, GLOBALFOUNDRIES, imec, Sand9 and others will discuss bringing MEMS into the fast-ramp, high-volume mainstream.

During the NorthOne TechXPOT, 2-4:30pm on the 12th, MIG will present "Heterogeneous Integration with MEMS and Sensors." Panelists will cover the eco-system of integrating MEMS and ICs.

Learn more at www.memsindustrygroup.org

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May 23, 2011 – Marketwire — Cascade Microtech Inc. (NASDAQ:CSCD), IC measurement product provider, released WinCalXE version 4.5 calibration software, with improved model and process quality. The new version "provides advanced calibration capabilities for the full line of Cascade Microtech probe solutions," said Michael Burger, president and CEO.

WinCalXE 4.5 is a single software tool that contains the features of WinCalXE and SussCal, and operates with all manual and semi-automatic Cascade Microtech and former SUSS MicroTec probe stations.

Burger notes that CSCD is in the midst of many integration tasks stemming from its acquisition of SUSS MicroTec Test Division’s systems and accessories in January 2010 for $98 million. The test systems business specializes in wafer-level test solutions for devices under test (DUT).

WinCalXE 4.5 is used with a vector network analyzer to make on-wafer high-frequency measurements. WinCalXE 4.5 S-parameter data is critical to accurate device characterization, says Cascade Micro.

Vector Network Analyzers do not have internal calibration tools specific to on-wafer measurements, and none offer probe station control, automatic calibrations or advanced on-wafer algorithms. WinCalXE 4.5 can accurately calibrate the measurement system and make automated measurements, data collection and data transformation on Vector Network Analyzers for on-wafer measurements, or measurements requiring on-wafer S-parameter measurements at any frequency up to 500GHz.

WinCalXE 4.5 advanced calibration methods include LRRM and a new LRM+ calibration algorithm. Users can get quick and easy data validation and reporting with automatic measurements using powerful sequencing tools. Users have access to an advanced set-up wizard and multimedia tutorials. WinCalXE 4.5 is fully compatible with Cascade Microtech |Z|Probe, ACP probe and Infinity Probe families and can be used with both ISS and CSR calibration substrates. It is compatible with most commercially available Vector Network Analyzers, ProberBench 7 and all versions of Nucleus probe station software.

Customers with WinCalXE 4.2 or greater, or with any version of SussCal, will receive an upgrade to WinCalXE 4.5 free of charge. Contact the local Cascade Microtech sales office for pricing and order information.

Cascade Microtech Inc. (NASDAQ: CSCD) is a worldwide leader in the precise electrical and mechanical measurement and test of integrated circuits (ICs) and other small structures. For technology businesses and scientific institutions that need to evaluate small structures, Cascade Microtech delivers access to electrical data from wafers, ICs, IC packages, circuit boards and modules, MEMS, 3D TSV, LED devices and more. Cascade Microtech’s leading-edge semiconductor production test products include unique probe cards and test sockets that reduce manufacturing costs of high-speed and high-density semiconductor chips. For more information visit www.cascademicrotech.com.

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May 23, 2011 — SiTime Corporation, an analog semiconductor company, launched the SiT820X family of MEMS-based programmable oscillators for telecom, networking, storage and wireless applications. The SiT820X family consists of the SiT8208 and SiT8209 programmable oscillators that operate from 1 to 80MHz and 80 to 220MHz respectively. They are fabricated with SiTime’s MEMS and analog semiconductor technologies and offer drop-in replacements for quartz, SAW, and overtone oscillators.

The new MEMS oscillators claim unprecedented jitter performance; 600 Femtoseconds of integrated RMS phase jitter measured from 12kHz to 20MHz. These devices achieve 2x better stability over the industrial temperature range than quartz-based solutions, the company reports.

Programmable features enable over 200 part numbers, each of which can be a drop-in replacement for existing quartz, SAW or overtone oscillators.
 
The SiT8208 and SiT8209 feature:

  • 600 Femtoseconds of typical integrated RMS phase jitter (measured per SONET-specified 12 kHz to 20 MHz range)
  • Any frequency with 6 decimal places of accuracy
  • Frequency stability as low as ±10PPM for enhanced system reliability against the effects of spurious noise
  • Programmable drive strength for impedance matching and EMI reduction
  • High-drive options that can be used to drive multiple loads
  • Available in industry standard 3225, 5032 and 7050 packages
  • Industrial (-40 to +85°C) and commercial temperature (-20 to +70°C) operation
  • 1.8V and 2.5-3.3V operation

Samples of the SiT8208 and SiT8209 will be available in early June 2011 with production in Q3 2011. SiTime ships customized samples in one week and production quantities in 3-5 weeks.

SiTime Corporation, an analog semiconductor company, offers MEMS-based silicon timing solutions that replace legacy quartz products. Learn more at www.sitime.com

Also read: SiTime enters resonator market with MEMS resonator for real-time clock and time-keeping apps

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May 19, 2011 — The MF3 Microfluidics Consortium, which includes Philips, STMicroelectronics (STM) and others, recognizes a need for standards in how microfluidic chips are connected to systems. Since microfluidics perform diverse tasks, three main interconnect types were identified: high temperature/pressure, electrical/optical interconnects to chip holders, and disposable chip interconnects. The consortium will first tackle high-temperature/pressure.

The MF-3 Microfluidic Consortium comprises a group of companies including SonyDADC, Philips, ST-Microelectronics, Biocartis, Dolomite and Micronit.

The industrial and consumer use of microfluidic solutions in components and instruments is hampered by the lack of standardized interconnects, says the MF-3 Microfluidic Consortium. General adoption of microfluidics will only be possible with an agreement on standardized interconnects between chips and systems.

Microfluidics are more diverse than conventional electronics and different applications will need different classes of interconnect. Multinational and SME Members of the MF3 consortium have put forward suggestions for addressing a variety of applications for microfluidic interconnects. The MF-3 Microfluidic Consortium has divided the requisite interconnect schemes into three groups:

At the consortium’s recent meeting in Milan, a draft proposal for higher temperature/ pressure interconnects was accepted and will be published shortly.

The MF3 consortium is now calling for further expressions of user requirements for microfluidic interconnects. These proposals will be discussed in workshops organized by the Consortium later this year.

The MF3 Microfluidics Consortium brings together stakeholders from all parts of the value chain with a shared interest in growing the market for microfluidics-enabled solutions to challenges in healthcare, environment and beyond. The consortium was launched in June 2008 and is open for further members worldwide. For more information, visit www.microfluidicsinfo.com

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May 18, 2011 — For the first time, the semiconductor industry is moving to 3D device structures, such as through silicon vias. This is significantly different than moving to thinner devices, says Raj Jammy, SEMATECH, at The ConFab 2011. He speaks with senior technical editor Debra Vogler.

Conformality of the gate dielectric, conformality of the contacts, and design all come into play. Semiconductor makers must still create robust and high-yield devices to be sucessful.

The biggest challenges for high-volume manufacturing of through silicon vias (TSV), Jammy says, are all through the process flow. Bonding and de-bonding is one major example, with poor throughput. Materials stresses, especially on thinned dies, are another.

SoC technologies are on the verge of some significant changes, Jammy predicts. For example, an entire smartphone could be fit onto one SoC. With system in package (SiP), additional functionality will be integrated, even MEMS devices.

Jammy also reviews SEMATECH’s roadmaps for logic and memory.

Read a summary of Jammy’s ConFab 2011 presentation on new device architectures.

May 18, 2011 – GLOBE NEWSWIRE — Northrop Grumman Corporation (NYSE:NOC), in partnership with the Georgia Institute of Technology, will develop a new type of microelectromechanical systems (MEMS) gyroscope technology for the Defense Advanced Research Projects Agency’s (DARPA) Microscale Rate Integrating Gyroscope program.

Utilizing a new MEMS fabrication process, the Northrop Grumman-led team will produce a proof-of-concept micro gyro that can perform as well as current silicon MEMS devices in a smaller size, lighter weight, and lower power package.

"The Northrop Grumman and Georgia Tech team will [enable] the extreme miniaturization of highly stable navigation devices, with small energy dissipation," said Farrokh Ayazi, a professor in the School of Electrical and Computer Engineering (ECE) at Georgia Tech. Dr. Ayazi is a principal investigator for this project and serves as co-director for ECE’s Center for MEMS and Microsystems Technology.

The MEMS technology developed by Northrop Grumman and Georgia Tech during the initial 12-month award period will form the basis for a micro resonator gyro capable of achieving navigation-grade performance. The new MEMS fab process will enable gyros for unmanned vehicles to handheld devices, Charles Volk, vice president and chief technology officer of Northrop Grumman’s Navigation Systems Division.

DARPA’s Microscale Rate Integrating Gyroscope program seeks to develop miniature navigation-grade gyros for use in personal navigation, unmanned vehicle navigation, GPS denied/challenged locations, and other size and power constrained applications requiring precision navigation. Northrop Grumman, in partnership with Georgia Tech, was awarded a research and development contract for the preliminary design, development and testing of micro-resonator devices.

Northrop Grumman produces navigation products using fiber-optic gyro-based systems, Northrop Grumman’s exclusive hemispherical resonator gyro, unique ZLG gyros, spinning mass gyros, ring laser gyros and micro-electro-mechanical-system gyros, among other technologies. Please visit www.northropgrumman.com for more information.

The Georgia Institute of Technology is one of the world’s premier research universities. The Institute offers research opportunities to both undergraduate and graduate students and is home to more than 100 interdisciplinary units plus the Georgia Tech Research Institute. www.gatech.com

Also read: Introduction to MEMS gyroscopes

May 17, 2011 — Wafer bonding is a complex process, used on 2" to 12" wafers for MEMS, CMOS image sensors, advanced packaging, LEDs, and other chips. Yole Développement published a technology study and market research report, "Permanent wafer bonding," to derive trends in the market and technology through 2016. The report aims at analyzing the market perspectives and technical trends for permanent bonding.

Yole Développement has estimated that the wafer bonding market will grow significantly for the next year. The growth will be driven small-size wafers for LEDs and 12" wafers for 3D die stacking and CIS.

The wafer bonding market is a very complex one, crossing different wafer sizes (from 2" to 12"), different applications (MEMS, CMOS image sensors [CIS], LEDs, power devices, RF and advanced packaging), and different bonding technologies (adhesive, anodic, fusion, direct oxide, eutectic, glass frit, metal diffusion).

Click to Enlarge

Wafer bonding is usually defined as a process that temporarily or permanently joins two wafers or substrates using a suitable process. Historically developed for MEMS and then SOI wafers, wafer bonding technology has shifted to non-mainstream IC applications over the last years.

"MEMS has been the first application where wafer bonders have been massively used (the wafer bonding step is mostly used to protect the MEMS sensitive element), explained Dr Eric Mounier, project manager at Yole Développement. MEMS manufacturers are currently shifting from glass frit for eutectic/metal-based bonding, yielding smaller bond frames. Metal direct bonding also provides hermeticity and mechanical stability for many MEMS applications. For example, Nasiri uses eutectic bonding of the MEMS directly on the aluminum layer of the CMOS wafer. This leads to smaller package footprints & package heights. STMicroelectronics’ latest 3-axis accelerometer (LIS3DH) also shows a new sealing technique: gold eutectic sealing allows a dramatic die size reduction.

CMOS image sensors are also a strong wafer bonding application. Up to two different wafer bonding steps can be necessary for next-generation CMOS image sensor fab: one for back-side illumination, the second for wafer-level chipscale packaging (WLCSP). For CIS, the advent of backside illumination (BSI) technology has raised a competition between molecular bonding and adhesive bonding. Here, cost and final application will drive the final technology choice.

Besides MEMS and CIS manufacturing, wafer bonding also can be used for LED and power device fab. In a typical LED active region, spontaneous emission scatters photons in all directions. If the substrate material has a smaller band gap than the active region, approximately half of the light is absorbed in the substrate; significantly reducing device performance. So, one of the manufacturing solutions for photon loss involves bonding a wafer containing an array of devices to another wafer that provides both a reflective surface for maximum light extraction and a heatsink for thermal management.

Companies cited in the report:

Acreo, AML, APM/UMC, Avago, Ayumi, Bosch, Colibrys, Dalsa, Discera, EVGroup, FhG IMS, FLIR, IBM, Icemos, IMEC, IMT, Infineon, Infineon, Invensense, KTH, Leti, Lumileds, MEMStech, Micralyne, Mitsubishi Heavy Industries, Okmetic, Omron, Osram, Qualcomm, Raytheon, RPI, Sand9, Semefab, Sensonor, Silex, SOITEC, STM, SUSS MicroTEC, Tezzaron, TI, tMt, Tohoku University, TowerJazz, Tracit, Triquint, Tronic’s, TSMC, VTI, Xcom, Ziptronix

Over the 5 past years, much attention has been given to wafer bonding for 3D integration of memories, for example, and other die.

Although EV Group (EVG) is the market leader in permanent bonding, the growth of the bonding equipment market is attracting challengers.

Yole Développement’s report analyzes the technical & economical evolution of the permanent wafer bonding process. It gives 2010-2016 market forecasts for permanent bonding, equipment, an overview of the different bonding approaches and equipment players market shares and competitive information, This market & technology report also presents the trends for permanent bonding, wafer-to-wafer (W2W) vs. chip-to-wafer (C2W) analysis for 3D integration. It describes the applications for wafer bonding with main characteristics and challenges.
 
Report author:
Dr. Eric Mounier has a PhD in microelectronics from the INPG in Grenoble. Since 1998 he is a co-founder of Yole Développement, a market research company based in France. At Yole Développement, Dr. Eric Mounier is in charge of market analysis for MEMS, equipment & material. Yole Développement is a group of companies providing market research, technology analysis, strategy consulting, media in addition to finance services. Learn more at www.yole.fr

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May 17, 2011 — Wafer bonding is a complex process, used on 2" to 12" wafers for MEMS, CMOS image sensors, advanced packaging, LEDs, and other chips. Yole Développement published a technology study and market research report, "Permanent wafer bonding," to derive trends in the market and technology through 2016. The report aims at analyzing the market perspectives and technical trends for permanent bonding.

Yole Développement has estimated that the wafer bonding market will grow significantly for the next year. The growth will be driven small-size wafers for LEDs and 12" wafers for 3D die stacking and CIS.

The wafer bonding market is a very complex one, crossing different wafer sizes (from 2" to 12"), different applications (MEMS, CMOS image sensors [CIS], LEDs, power devices, RF and advanced packaging), and different bonding technologies (adhesive, anodic, fusion, direct oxide, eutectic, glass frit, metal diffusion).

Click to Enlarge

Wafer bonding is usually defined as a process that temporarily or permanently joins two wafers or substrates using a suitable process. Historically developed for MEMS and then SOI wafers, wafer bonding technology has shifted to non-mainstream IC applications over the last years.

"MEMS has been the first application where wafer bonders have been massively used (the wafer bonding step is mostly used to protect the MEMS sensitive element), explained Dr Eric Mounier, project manager at Yole Développement. MEMS manufacturers are currently shifting from glass frit for eutectic/metal-based bonding, yielding smaller bond frames. Metal direct bonding also provides hermeticity and mechanical stability for many MEMS applications. For example, Nasiri uses eutectic bonding of the MEMS directly on the aluminum layer of the CMOS wafer. This leads to smaller package footprints & package heights. STMicroelectronics’ latest 3-axis accelerometer (LIS3DH) also shows a new sealing technique: gold eutectic sealing allows a dramatic die size reduction.

CMOS image sensors are also a strong wafer bonding application. Up to two different wafer bonding steps can be necessary for next-generation CMOS image sensor fab: one for back-side illumination, the second for wafer-level chipscale packaging (WLCSP). For CIS, the advent of backside illumination (BSI) technology has raised a competition between molecular bonding and adhesive bonding. Here, cost and final application will drive the final technology choice.

Besides MEMS and CIS manufacturing, wafer bonding also can be used for LED and power device fab. In a typical LED active region, spontaneous emission scatters photons in all directions. If the substrate material has a smaller band gap than the active region, approximately half of the light is absorbed in the substrate; significantly reducing device performance. So, one of the manufacturing solutions for photon loss involves bonding a wafer containing an array of devices to another wafer that provides both a reflective surface for maximum light extraction and a heatsink for thermal management.

Companies cited in the report:

Acreo, AML, APM/UMC, Avago, Ayumi, Bosch, Colibrys, Dalsa, Discera, EVGroup, FhG IMS, FLIR, IBM, Icemos, IMEC, IMT, Infineon, Infineon, Invensense, KTH, Leti, Lumileds, MEMStech, Micralyne, Mitsubishi Heavy Industries, Okmetic, Omron, Osram, Qualcomm, Raytheon, RPI, Sand9, Semefab, Sensonor, Silex, SOITEC, STM, SUSS MicroTEC, Tezzaron, TI, tMt, Tohoku University, TowerJazz, Tracit, Triquint, Tronic’s, TSMC, VTI, Xcom, Ziptronix

Over the 5 past years, much attention has been given to wafer bonding for 3D integration of memories, for example, and other die.

Although EV Group (EVG) is the market leader in permanent bonding, the growth of the bonding equipment market is attracting challengers.

Yole Développement’s report analyzes the technical & economical evolution of the permanent wafer bonding process. It gives 2010-2016 market forecasts for permanent bonding, equipment, an overview of the different bonding approaches and equipment players market shares and competitive information, This market & technology report also presents the trends for permanent bonding, wafer-to-wafer (W2W) vs. chip-to-wafer (C2W) analysis for 3D integration. It describes the applications for wafer bonding with main characteristics and challenges.
 
Report author:
Dr. Eric Mounier has a PhD in microelectronics from the INPG in Grenoble. Since 1998 he is a co-founder of Yole Développement, a market research company based in France. At Yole Développement, Dr. Eric Mounier is in charge of market analysis for MEMS, equipment & material. Yole Développement is a group of companies providing market research, technology analysis, strategy consulting, media in addition to finance services. Learn more at www.yole.fr

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May 17, 2011 — Catalan Institute of Nanotechnology Professor Adrian Bachtold and his research group created resonators from nanoscale graphene and carbon nanotubes (CNT) that exhibit nonlinear damping. This result could lead to supersensitive detectors of force or mass.

The team formed nanoscale resonators by suspending tiny graphene sheets or carbon nanotubes and clamping them at each end. These devices, similar to guitar strings, can be set to vibrate at very specific frequencies.

Click to Enlarge
Figure. A depiction of the nanoscale mechanical resonators constructed with graphene and CNTs. SOURCE: Catalan Institute of Nanotechnology.

Mechanical resonators mark time in electronic components and stabilize radio transmissions. In all mechanical resonators studied to date, from large objects several metres in size down to tiny components just a few tens of nanometers in length, damping has always been observed to occur in a highly predictable, linear manner.

Bachtold’s research demonstrates that this linear damping paradigm breaks down for resonators with critical dimensions on the atomic scale. The damping is strongly nonlinear for resonators based on nanotubes and graphene, a characteristic that facilitates amplification of signals and dramatic improvements in sensitivity.

Damping is central to the physics of nanoelectromechanical (NEMS) resonators, lying at the core of quantum and sensing experiments. Therefore many predictions that have been made for nanoscale electro-mechanical devices now need to be revisited when considering nanotube and graphene resonators. Prof. Bachtold’s group has achieved a new record in quality factor for graphene resonators and ultra-weak force sensing with a nanotube resonator, using these atomic-level devices.

Results will be published in Nature Nanotechnology (DOI 10.1038/NNANO.2011.71). To retrieve the abstract and full text, visit http://dx.doi.org/ DOI 10.1038/ NNANO.2011.71

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