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Rudolph Technologies, Inc., a provider of process characterization, photolithography equipment and software for the semiconductor, FPD, LED and solar industries, today released three new application-specific configurations of its industry-leading NSX 320 Automated Macro Defect Inspection System. The suite includes specially-designed configurations for wafer level packaging, 2.5D (interposer) and 3DICs using through-silicon via (TSV) as interconnects. The first NSX 320 Metrology System for wafer level packaging shipped in June to a major outsourced assembly and test (OSAT) facility in Asia.

“These new application-specific configurations of our established NSX 320 System are designed to address the emerging need for fast, precise three-dimensional (3D) measurements in the rapidly growing advanced packaging market sector,” said Rajiv Roy, vice president of business development and director of back-end marketing at Rudolph Technologies. “We have completed the integration of 3D measurement sensors, recently acquired from Tamar Technology, into the NSX System. Tamar’s sensor technology is well recognized and widely used, and integrating it into the NSX 320 System adds critical capability required for enabling advanced packaging applications such as copper pillar bumping and TSV.”

The NSX 320 wafer level packaging configuration is designed to measure film thickness (polymers, photoresist, glass), thin remaining silicon thickness (RST), surface topography, copper pillar height and solder bump height. The advanced wafer level packaging configuration adds measurements of the wafer profile (warp and bow), total stack thickness and thick/thin RST (bonded wafer before and after grind). The 3DIC configuration is capable of all the above measurements plus via depth, trench depth, bonded wafer TTV and adhesive layers.

Roy stated, “3DIC device volume is forecasted to grow to $38.4B by 2017, according to Yole Développement. Rudolph is positioned to address the growth requirements for wafer level packaging, as well as 2.5D and other advanced packaging technologies, with industry-proven metrology tools that offer superior speed and measurement solutions.”

IC Insights’ new 250-page Mid-Year Update to the 2013 McClean Report, which is slated to be released by the end of July, describes why a very clear distinction should be made between the IC market (i.e., consumption) in China and IC production within China.  Although China has been the largest individual market for ICs since 2005, it does not necessarily mean that large increases in IC production within China would immediately follow, or ever follow. IC production in China represented only 11.1 percent of its $81 billion IC market in 2012.  Moreover, IC Insights forecasts that this share will increase only about three percentage points to 14.4 percent in 2017.

China-based IC production is forecast to exhibit a very strong 2012-2017 CAGR of 17.6 percent.  However, considering that China-based IC production was only about $8.9 billion in 2012, this growth will come off a relatively small base.  In 2012, SK Hynix, TSMC, and Intel were the major foreign IC manufacturers that had significant IC production in China.  In fact, SK Hynix’ China fab had the most capacity of any of its fabs last year.  In 2012, Intel continued to ramp-up its 300mm fab in Dalian, China (it started production in late October 2010), which is expected to give a noticeable boost to the China-based IC production figures over the next few years.  This fab currently has an installed capacity of 30,000 300mm wafers per month with a maximum capacity of 52,000 wafers per month.

In early 2012, Samsung gained approval from the South Korean government to construct a 300mm IC fabrication facility to produce NAND flash memory in Xian, China.  Samsung started construction of the fab in September of 2012 with production set to begin in the first half of 2014.  The company expects to invest $2.3 billion in the first phase of the fab with $7.0 billion budgeted in total.  This facility is targeting NAND flash production using a 10-19nm feature size process technology.

If China-based IC production rises to $20.0 billion in 2017 as forecast, it would still represent only 5.6 percent of the total forecasted 2017 worldwide IC market of $359.1 billion.  Even after adding a significant “markup” to many of the Chinese producers’ IC sales figures (since many of the Chinese IC producers are foundries that sell their ICs to companies that re-sell these products to the electronic system producers), China-based IC production would still represent less than 10 percent of the global IC market in 2017.

China's IC producers

Historically, the lack of consistent intellectual property protection has been a major deterrent for foreign firms seeking to establish state-of-the-art IC fabrication facilities in China.  The lack of intellectual property protection is also a reason many large fabless IC suppliers (e.g., Qualcomm, Broadcom, etc.) have not brought leading-edge IC designs into China for the indigenous Chinese IC foundries to manufacture.  It should also be noted that, thus far, Chinese IC foundries have also been unable to offer large amounts of IC production using leading-edge feature sizes.

IC Insights believes that the future size of the IC production base in China is more dependent upon whether foreign companies continue to locate, or re-locate, IC fabrication facilities in China than on the success of indigenous Chinese IC producers (e.g., SMIC, Hua Hong Grace, etc.).  As a result, IC Insights forecasts that at least 70 percent of IC production in China in 2017 will come from foreign companies such as SK Hynix, TSMC, Intel, and Samsung.

Ulsan National Institute of Science and Technology (UNIST) researchers report considerable improvement in device performance of polymer-based optoelectronic devices. Published in Nature Photonics, the new plasmonic material, can be applied to both polymer light-emitting diodes (PLEDs) and polymer solar cells (PSCs), with world-record high performance, through a simple and cheap process.

The contrary demands of these devices mean that there are few metal nanoparticles that can enhance performance in PLEDs and PSCs at the same time.

Most semiconducting optoelectronic devices (OEDs), including photodiodes, solar cells, light emitting diodes (LEDs), and semiconductor lasers, are based on inorganic materials. Examples include gallium nitride for light-emitting diodes and silicon for solar cells.

Due to the limited availability of raw materials and the complex processing required to manufacture OEDs based on inorganic materials, the cost of device fabrication is increasing. There is great interest in thin-film OEDs that are made from alternative semiconductors.

Among these materials, organic semiconductors have received much attention for use in next-generation OEDs because of the potential for low-cost and large-area fabrication using solution processing.

Despite extensive efforts to develop new materials and device architectures enhancing the performance of these devices, further improvements in efficiency are needed, before there can be widespread use and commercialization of these technologies.

The material prepared by the UNIST research team is easy to synthesize with basic equipment and has low-temperature solution processability. This low-temperature solution processability enables roll-to-roll mass production techniques and is suitable for printed electronic devices.

“Our work is significant also because it anticipates the realization of electrically driven laser devices by utilizing carbon dot-supported silver nanoparticles (CD-Ag NPs) as plasmonic materials.” says said Prof. Byeong-Su Kim. “The material allows significant radiative emission and additional light absorption, leading to remarkably enhanced current efficiency.”

Surface Plasmon resonance is an electro-magnetic wave propagating along the surface of a thin metal layer and the collective oscillation of electrons in a solid or liquid stimulated by incident light. SPR is the basis of many standard tools for measuring adsorption of materials onto planar metal (typically gold and silver) surfaces or onto the surface of metal nanoparticles.

The team demonstrated efficient PLEDs and PSCs using surface Plasmon resonance enhancement with CD-Ag NPs. The PLEDs achieved a remarkably high current efficiency (from 11.65 to 27.16 cd A-1) and luminous efficiency (LE) (from 6.33 to 18.54 lm W-1).

PSCs produced in this way showed enhanced power conversion efficiency (PCE) (from 7.53 to 8.31 percent) and internal quantum efficiency (IQE) (from 91 to 99 percent at 460nm). The LE (18.54 lm W-1) and IQE (99 percent) are among the highest values reported to date in fluorescent PLEDs and PSCs, respectively.

“These significant improvements in device efficiency demonstrate that surface Plasmon resonance materials constitute a versatile and effective route for achieving high performance polymer LEDs and polymer solar cells,” said Prof. Jin Young Kim. “This approach shows promise as a route for the realization of electrically driven polymer lasers.”

The fellow researchers include Hyosung Choi, Seo-Jin Ko, Yuri Choi, Taehyo Kim, Boram Lee, and Prof. Myung Hoon Song from UNIST, and researchers from Chungnam National University, Pusan National University, and Gwangju Institute of Science and Technology.

This research was supported by a WCU (World Class University) program through the Korea Science and Engineering Foundation funded by the Ministry of Education, Science and Technology, the National Research Foundation of Korea Grant, the Korea Healthcare technology R&D Project, the Ministry of Health & Welfare, Korea and the International Cooperation of the Korea Institute of Energy Technology Evaluation and Planning (KETEP) grant funded by the Korean government Ministry of Knowledge Economy.

 

Steffen_SchulzeSteffen Schulze is the director of Marketing, mask Data Preparation and Platform Applications at Mentor Graphics, serving customers in mask and IC manufacturing.

Who knew that mask process correction (MPC) would again become necessary for the manufacturing of deep ultraviolet (DUV) photomasks? MPC can be called a seasoned technology; it has always been an integral part of the e-beam mask writers to cope with the e-beam proximity effects, which can extend up to 15um of the exposure point. In addition, the mask house has been compensating for process-induced biases. Residual errors were always absorbed by the models created to describe the wafer process. Range and general behavior proved to be sufficient to capture the effects and secure the accuracy requirements for the wafer lithography.

At the 40nm node, more complex techniques were considered to cope with significant proximity signatures induced by the dry etch process and the realization that forward scattering in e-beam exposure, which was not accounted for in the machine-based correction, had a significant impact especially in 2D configurations. A number of commercial tools were made available at the time but a broad adoption was thwarted by the introduction of new mask substrates and the associated etch process – OMOG blanks provided for a thinner masking layer and enabled an etch process with a fairly flat signature. The MPC suppliers moved on to the EUV technology domain where a new and thicker substrate with a more complex etch process showed stronger signatures again, along with new effects of different ranges.

So what is changing now? At the 10nm node we are still dependent on the 193nm lithography. And while the wafer resolution is tackled with pitch splitting, the accuracy requirements continue to get tighter – tolerances far below 1nm are required for the wafer model. Phase shift masks are considered with a stack that is higher and displays stronger signatures again. In addition, scatter bars of varying sizes but below 100nm at the mask fall again into the size range with significant linearity effects.

So no wonder that the mask and wafer lithography communities are turning to mask process correction technology again. Wafer models have expanded to a more comprehensive description of the 3D nature of the mask (stack height and width ratio are approaching 1). A recent study presented at SPIE (Sturtevant, et al http://dx.doi.org/10.1117/12.2013748) shows that systematic errors on the mask contribute more than 0.5nm RMS to the error budget.  Figure 1 shows the process biases present in an uncorrected mask for various feature types – dense and isolated lines and spaces. Figure 2 shows how strongly the variability in mask parameters – here stack slope and corner rounding – can influence the model accuracy for a matching wafer model.

Figure 1 copy
Figure 1. Mask CD bias (actual-target) 4X for four different pattern types and both horizontal and vertical orientations. Click to view full screen.
Figure 2 copy
Figure 2 .  Impact of changing the MoSi slope (left) and corner rounding (right) on CTR RMS error at nominal condition and through focus. Click to view full screen.

The authors showed that the proper representation of the mask to a wafer model can improve the modeling accuracy significantly. For example, even an approximation of the corner rounding by a 45deg bevel can have a significant impact. Likewise considering the residual linearity and proximity errors improves the modeling accuracy. Figure 3 shows the comparison of residual errors for a variety of test structure in the uncorrected stage and when simulated with the proper mask model. The latter one can largely compensate the observed errors.

Figure 3
Figure 3. Mask CD error (4X) versus target and residual mask process simulation error. Click to view full screen.

The methods to properly account for the effects during the simulation are anchored in mask processing technology. These results have opened the discussion as to not only describing the mask but also correcting it. The above mentioned study revealed a number of additional parameters that are generally assumed to be stable but fundamentally reveal a high sensitivity of the lithomodel to any variation –specifically the material properties and the edge slope or a substrate over-etch.  From these studies and observations one can conclude that mask process characterization and correction will be of increasing importance for meeting the tolerance requirements for wafer modeling and processing – initially by proper description of its residual errors for consideration in the wafer model but subsequently also by correction. The technology is available for quite some time and ready to be used – unless the materials and the process community come through again.

Read other Mentor Graphics blog posts:

Innovations in computational lithography for 20nm

Looking for an integrated tape-out flow

Dialog Semiconductor plc, a provider of highly integrated power management, audio, AC/DC and short-range wireless technologies today announced that Richard Beyer, appointed to the board in February this year, as an independent non-executive director, will succeed Gregorio Reyes as chairman of the board. Greg will continue to serve as a board member.

Beyer, 64, was the chairman and CEO of Freescale Semiconductor from March 2008 to June 2012, subsequently retiring from the board in April this year. Prior to this, he held successive positions as CEO and director of Intersil Corporation, Elantec Semiconductor and FVC.com. He has also held senior leadership positions at VLSI Technology and National Semiconductor Corporation and served as an officer in the US Marine Corps. In 2012, he was chairman of the Semiconductor Industry Association Board of Directors and served for three years as a member of the US Department of Commerce’s Manufacturing Council. He currently serves on the Board of Micron Technology Inc.

Dialog’s board said that Reyes has been an excellent Chairman, presiding in that position over the last six consecutive years of revenue growth and significant increase in shareholder return. He steps down as chairman on the high note of the positively received acquisition of iWatt Inc. earlier this month.

CEA-Leti today announced that a group of European and Japanese companies, research institutes, universities and cities will work together in the ClouT project to deliver ways for cities to leverage the Internet of Things (IoT) and cloud computing – to become smart cities.

ClouT, which stands for “cloud of things,” will develop infrastructure, services, tools and applications for municipalities and their various stakeholders – including citizens, service developers and application integrators – to create, deploy and manage user-centric applications that capitalize on the latest advances in IoT and cloud computing.

The IoT allows users to connect “everything” (sensors, objects, actuators, mobile phones, servers, etc.) and gather and share information in real-time from the physical environment. Cloud computing lets users process, store and access information with virtually unlimited processing and storage capacity. ClouT will integrate the latest advances in these domains and, with its user-centric approach, allow end users in cities to create their own cloud services and share them with other citizens.

Target applications include enhanced public transportation, increased citizen participation through the use of mobile devices to photograph and record situations of interest to city administrators, safety management, city-event monitoring and emergency management. The project, which is coordinated in Europe by Leti, includes nine industrial and research partners and four cities: Santander, Spain; Genoa, Italy; Fujisawa, Japan and Mitaka, Japan. The applications will be validated in those cities via field trials with citizens.

By combining EU and Japanese resources, the three-year, nearly 4 million-euro project is designed to create an on-going synergy for smart-city initiatives between Europe and Japan.

ClouT is jointly funded by the 7th Framework Programme of the European Commission and by the National Institute of Information and Communications Technology (NICT) of Japan.

 

Cree, Inc. announces that its 1200 V SiC MOSFETs are being incorporated into the latest advanced power supplies from Delta Elektronika BV. Delta Elektronika demonstrated a 21 percent decrease in overall power supply losses and a reduction in component count by up to 45 percent when compared to power supply products using traditional silicon technology.

Since 1959, Netherlands-based Delta Elektronika BV has produced power supplies for a range of industrial applications, such as specialized equipment used in factories, automation and industrial power conversion. Its power supplies typically provide high efficiency with low noise levels and are well known for their long operating lifespan.

“We are pleased to have Delta Elektronika BV as one of the volume adopters of our newest generation of SiC MOSFETs,” said Cengiz Balkas, general manager, Cree Power and RF. “Delta Elektronika BV has a half-century legacy of producing some of the most reliable, efficient and compact power supplies on the market. The industrial power supply market, which values efficiency, reliability and power density, is a key market for SiC MOSFET technology. Our new second-generation SiC MOSFET portfolio, which now includes a 160 m-Ohm MOSFET for the 5-10 kW market, is receiving strong market pull.”

Introduced in March 2013, Cree’s second-generation SiC MOSFETs have been well received throughout the power industry and are experiencing an increasing rate of adoption in several key applications, including a design-in at a major manufacturer’s next-generation, highly efficient PV inverters. With SiC, power supply manufacturers are able to reduce their component count to help improve reliability while maintaining or improving the power supply’s efficiency. Improving power density can also lead to reductions in the size, weight, volume and in some cases, even the cost of power supplies. SiC has been demonstrated to achieve more than twice the power density than typical silicon technology in standard power supply designs.

After a flat year in 2012, global purchasing of semiconductors by the world’s top electronic brands is set to return to growth in 2013, as Apple Inc. and Samsung Electronics contend to claim the title of biggest spender.

The total available market, or TAM, for semiconductor spending by major original equipment manufacturers (OEM) in 2013 will rise to $265.2 billion this year, up 4.2 percent from $254.4 billion in 2012, according to a Semiconductor Spend Analysis Market Tracker Report from information and analytics provider IHS (NYSE: IHS). Spending by year-end will be at its highest level in six years, with expenditures in 2014 forecast to make another modest jump to $279.4 billion.

This top OEM semiconductor spending TAM represents about 83 percent of the total semiconductor market of $318.8 billion, as valued by the IHS Application Market Forecast Tool (AMFT).

If internal chip consumption within companies is excluded, the served available market for semiconductor spending, or SAM, will equate to an amount slightly lower than the TAM, at $241.3 billion in 2013.

As IHS announced in 2012, Apple is set to maintain leadership in the OEM semiconductor spending SAM in 2013. However, when also accounting for consumption of internally produced chips, Samsung will take the lead in terms of TAM this year.

“Depending on the metric used, either Samsung or Apple will be the top chip spender for 2013,” said Myson Robles-Bruce, senior analyst for semiconductor spend & design activity at IHS. “Either way, the honor does not merely signify bragging rights but also carries attendant overtones of prestige and influence, with the incumbent leader often tacitly acknowledged by all others as the industry’s top semiconductor spender.”

Other OEMs that make an appearance in both TAM and SAM lists—rankings vary depending on the roster—include Hewlett-Packard, Lenovo, Sony, Dell, Cisco Systems, Panasonic, Toshiba and Asustek Computer.

Wireless is king, but computer platforms still matter

Not surprisingly, the greatest share of spending this year will be in wireless communications, where Samsung and Apple lord over other players. Wireless alone is forecast to gobble up 26 percent—approximately $62 billion—of total top OEM semiconductor SAM. Wireless is also expected to be the highest growth market in 2013 after an annual projected expansion of 12.8 percent.

Within the wireless segment, handsets continue to be the single largest market, with OEM chip spending in 2013 expected to reach $46.7 billion. Media tablets are next at $8.2 billion, exceeding wireless infrastructure for the first time after the latter falls this year to $7.1 billion.

After wireless, computer platforms representing PCs and similar computing devices collectively represent the next-largest segment, forecast to take up 23 percent of OEM chip spending. China, which became the world’s biggest market for PC shipments last year, continues to account for a hefty part of PC-related chip spending even as the overall global computer market has slowed.

However, it should be noted that if the computer platforms segment is combined with the computer peripherals market, it becomes the largest single semiconductor market, beating wireless.

Following wireless and the computer platforms segment are the other smaller markets that take up the rest of OEM chip spending. In decreasing size, these segments are consumer, computer peripherals, automotive, industrial and wired communications, with share portions for each ranging from 6 to 15 percent.

Among semiconductor components, OEM chip spending this year will be largest in logic integrated circuits (IC) at nearly $75 billion, followed by memory ICs at $44 billion. The rest of the categories being tracked include analog ICs, discrete chips, microcomponent ICs, optical semiconductors, and sensors and actuators.

North America-based manufacturers of semiconductor equipment posted $1.33 billion in orders worldwide in June 2013 (three-month average basis) and a book-to-bill ratio of 1.10, according to the June EMDS Book-to-Bill Report published today by SEMI.   A book-to-bill of 1.10 means that $110 worth of orders were received for every $100 of product billed for the month.

The three-month average of worldwide bookings in June 2013 was $1.33 billion. The bookings figure is 0.7 percent higher than the final May 2013 level of $1.32 billion, and is 6.6 percent lower than the June 2012 order level of $1.42 billion.

The three-month average of worldwide billings in June 2013 was $1.21 billion. The billings figure is 1.4 percent lower than the final May 2013 level of $1.22 billion, and is 21.4 percent lower than the June 2012 billings level of $1.54 billion.

“The SEMI book-to-bill ratio has been above parity for six consecutive months and bookings in the quarter ending in June are 20 percent above the quarter ending in March,” said Denny McGuirk, president and CEO of SEMI.  "As recently announced, we anticipate that total worldwide equipment spending will decline by low single-digits this year and rebound with a double-digit growth rate in 2014.”

The SEMI book-to-bill is a ratio of three-month moving averages of worldwide bookings and billings for North American-based semiconductor equipment manufacturers. Billings and bookings figures are in millions of U.S. dollars.

 

Billings 
(3-mo. avg)

Bookings
 (3-mo. avg)

Book-to-Bill

January 2013

968.0

1,076.0

1.11

February 2013

974.7

1,073.5

1.10

March 2013

991.0

1,103.3

1.11

April 2013

1,086.3

1,173.9

1.08

May 2013 (final)

1,223.4

1,321.3

1.08

June 2013 (prelim)

1,206.8

1,329.9

1.10

Source: SEMI, July 2013


The data contained in this release were compiled by David Powell, Inc., an independent financial services firm, without audit, from data submitted directly by the participants. SEMI and David Powell, Inc. assume no responsibility for the accuracy of the underlying data.

SEMI is the global industry association serving the nano- and micro-electronic manufacturing supply chains.. SEMI maintains offices in Bangalore, Beijing, Berlin, Brussels, Grenoble, Hsinchu, Moscow, San Jose, Seoul, Shanghai, Singapore, Tokyo, and Washington, D.C. For more information, visit www.semi.org.

Making a stellar debut, high-resolution liquid-crystal display (LCD) panels featuring resolutions of 300 pixels per inch (ppi) or more are appearing in media tablets for the first time this year, with shipments set to approach 13 million units.

Up from virtually zero in 2012, at least 12.6 million LCD tablet panels with 300-ppi-or-higher resolutions will ship in 2013, according to insights from the Display Materials & Systems Service at information and analytics provider IHS. Shipments will then more than double next year and continue to climb to 55.0 million units by 2017.

“Tablet makers want to differentiate their products, increase their market presence, boost demand and improve their profitability by offering high-performance displays,” said Sweta Dash, senior director for display research at IHS. “Display suppliers are supporting this trend with increased production of higher-pixel-density LCD panels that employ the latest technologies to pack more pixels into every inch of screen space. This will create a whole new class of displays with 300 ppi and higher resolution that will represent the new high end for the tablet business.”

Pixel proliferation

The new 300-ppi class will join existing 200-ppi categories to form a freshly expanded line of high-resolution displays. And while shipments of such panels will keep growing and increasingly rule the tablet space, lower-resolution panels of 100-150 and 151-200 ppi will see their markets decline or remain flat over the years.

Prior to 300 ppi, the highest resolution for tablets was in the 251- to 300-ppi range, where Apple’s 9.7-inch iPad 4 and the 9.0-inch Barnes & Noble nook HD+ belong. Panel shipments for this resolution segment are forecast this year to reach 67.2 million units, up 47 percent from 45.7 million in 2012.

Below that segment are tablet panels in the 200- to 251-ppi range, home to the 7.0-inch Amazon Kindle Fire HD and the 10.0-inch Google Nexus 10. Panel shipments here are projected this year at 22.8 million units, up 88 percent from 12.1 million.

SID and fancy displays

Examples of the new 300-ppi panel for tablets could be seen at the recent Society for Information Display (SID) conference in Vancouver, a prominent industry event where panel manufacturers discuss new technologies and advances in the field.

At the event in May, LG Display showed a 7-inch high-definition tablet panel of more than 300 ppi, while rival Samsung Electronics countered with a 10.1-inch 300-ppi tablet panel.

Taiwan’s Innolux also had its own offering—a 6-inch high-definition, low-temperature polysilicon panel at 368 ppi.

Some of the new high-resolution displays slated for release this year will make use of oxide thin film-transistor (TFT) technology, similar to what was glimpsed at SID. The technology is considered a next-generation solution for panels, due to the mechanism’s high transparency and low power consumption.

Notebook panels also to benefit

High-resolution displays will also be coming to LCD panels for notebook PCs, judging from the SID exhibits. Samsung unveiled a 13.3-inch notebook PC panel with 275 ppi—higher than the 227 ppi of the much lauded 13-inch Apple MacBook Pro with Retina Display. Meanwhile, LG Display presented a 14- inch notebook LCD panel featuring 221 ppi.

For the notebook business in particular, where sales have suffered as consumers defected to smartphones and tablets, high-resolution displays could be what mobile PC manufacturers need to entice consumers to replace their older laptops. The new displays can be deployed to make products stand out from the rest of the field, create new demand among consumers, and boost revenue and profitability, IHS believes.

In line with the theme of higher performance, glass companies were likewise at SID to demonstrate glass substrates, an important component of LCD panels, for enabling next-generation displays.

Both New York-based Corning and Japan’s Asahi Glass announced glass substrate products at the show, formulated for high-performance displays intended to improve quality and productivity.