Category Archives: Online Magazines

Boston University filed a lawsuit against Apple Inc. and several other big tech companies over an alleged patent infringement, a thin film semiconductor technology that they claim was developed by one of their professors.

The suit, which was filed on Tuesday in a federal district court in Boston, the school claims that Apple violated its patent on “highly insulating monocrystalline gallium nitride thin films.” BU says this technology is being used in products such as the iPhone, iPad and MacBook Air.

Boston University names Theodore Moustakas, a professor of electrical and computer engineering, as the inventor of the technology, and claims that the patent for the semiconductor film was issued in 1997.

The school is seeking financial compensation that will be determined by a jury, if the case goes to trial. However, the patent on Moustakas’ technology expires in 2015, leaving experts to speculate on what little impact a Boston University victory could have on Apple’s future.

Neither party has commented on the case.

Toshiba Corporation today announced that it will expand its No. 5 semiconductor fabrication facility (Fab 5) at Yokkaichi Operations in Mie, Japan, to secure manufacturing space for NAND flash memories fabricated with next generation process technology and for future 3D memories. Fab 5 second phase construction will start at the end of August this year and be completed in summer next year. Decisions on equipment investment and production will reflect market trends.

Yokkaichi Operations currently has three Fabs mass producing NAND flash memory, including Fab 5 phase 1. Fab 5’s construction was planned around two phases, the first of which went into operation in July 2011. After giving careful consideration to the balance of product supply and demand, and noting a recovery driven by growing demand for smartphones, tablets, SSD for enterprise servers and other new applications, Toshiba now anticipates further medium- to long-term market expansion and recognizes that the time is right to expand Fab 5.

In addition to securing capacity for future generations of NAND Flash memory fabricated with the company’s latest process technology, Toshiba will also use Fab 5 phase 2 for production of 3D memories that are expected to find growing application in coming years. The extension will allow the company to boost competitiveness and enhance its responsiveness to technology advances and market demands.

Fab 5 phase 2 will have an automated product transportation system and quake-absorbing structure and will be designed to minimize environmental loads. Deployment of LED lighting and up-to-date energy-saving production facilities, along with full and effective use of waste heat, are expected to cut CO2 emissions by 13 percent compared with Fab 4.

Going forward, Toshiba will expand its memory business and boost competitiveness by timely investments, leadership in advanced process technology and the development of new generation memories that answer market needs.

Following last week’s formal announcement from Governor Cuomo of the formation of the Facility 450 Consortium (F450C), ten leading nanoelectronics facility companies from around the world will collaborate at CNSE to lead the global effort to design and build the next-generation 450mm computer chip fabrication facilities. At the semiconductor industry’s annual SEMICON West tradeshow, taking place at the Moscone Center in San Francisco, CA on July 9-11, the F450C will host its first public panel discussion about facility and infrastructure solutions for the transition to 450mm wafer fabrication.

Who: Members of the Facility 450 Consortium (F450C)

What: Panel entitled: The 450mm Facility; F450C’s Parallel Pathway

When: 4-5 pm on Tuesday, July 9

Where: The Impress Lounge, located at the B Bar above Moscone’s North

Why: Beyond the manufacturing hurdles that 450mm wafer processing brings, next generation fabs present new challenges with respect to the design of the facilities, substrate handling, tool connection, chemical distribution, water and electrical systems and many other areas. Where the G450C provides leadership in the area of 450mm equipment and process technologies, the goal of the F450C is to develop facility and infrastructure solutions essential to the transition to 450mm wafer fabrication.

On the Agenda:

  • Allen Ware, M+W Group & F450C: An Introduction to the F450C
  • William Corbin, G450C: Design to Requirement at the Utility Level
  • Adrienne Pierce, Edwards Vacuum: The ŒGreen Pump Strategy
  • Lothar Till, Ovivo: Water Use at 450mm

To register for the event please RSVP to [email protected]

The Facilities 450mm Consortium (F450C) is a first-of-its-kind partnership at SUNY’s College of Nanoscale Science and Engineering (CNSE) that is leading the global effort to design and build next-generation 450mm computer chip fabrication facilities. The collaboration includes 10 of the world¹s leading nanoelectronics facility companies, including Air Liquide, CH2M HILL, CS Clean Systems, Ceres Technologies, Edwards, Haws Corporation, Mega Fluid Systems, M+W Group, Ovivo, and Swagelok. Members of F450C are working closely with the Global 450mm Consortium (G450C), as announced by New York Governor Andrew M. Cuomo, to identify viable solutions required for 450mm high-volume facility construction, with initial focus areas to include reducing tool installation cost and duration, and improving facility sustainability.

CEA-Leti announced today €1 million in funding from bpifrance to accelerate preclinical development of a liver-cancer detection system called LipImage 815.

The grant, awarded through bpifrance ’s Strategic Industrial Innovation (ISI) program, will accelerate the development of LipImage 815, including production and regulatory toxicity evaluation. It also supports the launch of NICE (Nano Innovation for Cancer), the first consortium of nanomedicine stakeholders in France focused on aspects of characterization and industrialization. The consortium has been accredited by the Medicen Paris Region, a competitive cluster for innovative therapies in Ile-de-France.

Developed by Leti, LipImage 815 is a fluorescent imaging agent based on Leti’s Lipidots platform that uses lipid nanoparticles to carry a fluorescent substance to targeted cells and improve the effectiveness of diagnosis. It will be used to test for early stages of liver cancer.

Consisting of five public and private partners and led by BioAlliance Pharma, the NICE consortium includes partners with deep expertise in the field of nanomedicine. Its mission is to build a platform to accelerate the development and industrialization of nanomedicine in France by capitalizing on the strong and complementary expertise of each partner.

In addition to Leti, the consortium includes:

  • BioAlliance Pharma, developer of Livatag, a doxorubicin nanoparticle currently in phase III clinical trial for treatment of primary liver cancer
  • Nanobiotix, developer of NBTXR3, a potentiator of radiation therapy in the local treatment of cancer
  • DBI, a company specialized in the production of nanomedicine pharmaceutical products
  • Institut Galien Paris Sud (University Paris Sud/CNRS), which has an academic-excellence team specialized in nanoparticles research

“By bringing together a highly experienced team of specialists in various fields of nanomedicine, this program can significantly accelerate the development of an effective new tool for diagnosing liver cancer,” said Laurent Malier, Leti CEO. “It also leverages Leti’s achievements in the Lipidots platform, and provides another avenue for us to bring our innovations to market.”

The Strategic Industrial Innovation program promotes the emergence of European champions.  It supports ambitious, innovative collaborative projects through to industrialization, driven by innovative medium-sized companies (less than 5000 employees) and small businesses (less than 250 employees).  These highly promising projects are aimed at the commercialization of products which result from technological breakthroughs and which not be possible without fostering measures from the public sector.  Funding is generally in the €3-10 million range, as grants-in aid and loans which are repayable if the project is a success.

Leti is an institute of CEA, a French research-and-technology organization with activities in energy, IT, healthcare, defence and security. Leti is focused on creating value and innovation through technology transfer to its industrial partners. It is specialized in nanotechnologies and their applications, from wireless devices and systems, to biology, healthcare and NEMS and MEMS photonics. are at the core of its activities. An anchor of the MINATEC campus, CEA-Leti operates 8,000-m² of state-of-the-art clean room space on 200mm and 300mm wafer platforms. It employs 1,700 scientists and engineers including 320 Ph.D. students and 200 assignees from partner companies. CEA-Leti owns more than 2,200 patent families.

 

BOE Technology Group announced that it has placed significant orders for advanced Gen 8.5 and Gen 5.5 display production equipment from Applied Materials for use in multiple facilities. BOE selected these systems because of their ability to produce faster, smaller thin film transistors for the next era of high definition televisions and high pixel density displays for future mobile devices. Applied Materials is providing a full suite of advanced deposition equipment including the leading-edge Applied  PiVot PVD  and PECVD systems, which are capable of supporting critical new technologies such as metal oxide and LTPS.

"BOE continues to execute on its manufacturing capacity and technology initiatives and appreciates the strong cooperative relationship with Applied Materials in developing and creating value in support of the world’s largest TV and mobile display market," said Mr. Liu Xiaodong, executive vice president, chief operation officer of BOE. "Over the past year we have achieved key high-volume Gen 8.5 production and yield milestones, which demonstrate our leadership in growing this strategic industry in China. We are pleased to work with Applied Materials to implement the new technologies needed to continue meeting the high quality, high performance screens consumers have come to expect and demand."

"Applied Materials is delighted to play an important role in BOE’s growth strategy and is committed to providing the leading-edge technologies to enable its continued success," said Ali Salehpour, group vice president, general manager, Applied Materials Energy and Environmental Solutions and Display Business Group. "There is a major shift taking place in the display industry toward adopting new materials, and BOE selecting Applied Materials equipment validates the technology differentiation and productivity gains we provide to our customers. Together, BOE and Applied are enabling consumers to experience displays with world-class color, clarity and brightness."

The Applied PiVot PVD and PECVD systems selected by BOE provide a high-performance, cost-effective path to manufacturing stunning high resolution amorphous silicon, metal oxide and LTPS displays.  These systems can significantly increase production and achieve the same economies of scale that enabled the cost of LCD TVs to fall by more than 95 percent over the past decade and brought large-area LCD televisions within the reach of billions of consumers around the globe.

Applied Materials, Inc. provides equipment, services and software to enable the manufacture of advanced semiconductor, flat panel display and solar photovoltaic products. Our technologies help make innovations like smartphones, flat screen TVs and solar panels more affordable and accessible to consumers and businesses around the world.

ROFIN, a manufacturer of industrial lasers and laser systems enters the semiconductor market with a turnkey solution for front-end-of-line (FEOL) processing. The new laser wafer processing system Waferlase 200/300/450, is a fully automated modular platform comprising a market-leading handling system for (ultra) thin semiconductor wafers and a choice of laser processing modules, depending on the type of application. The Waferlase 200/300/450 product family starts with solutions for IGBT laser annealing and debris-free wafer marking.

Leading ultra-thin wafer handling technology

ROFIN integrated top-notch wafer handling technology to provide precise, non-contact transportation of ultra-thin wafers, even with considerable warpage and bow. The system comes with two or more cassette ports for Open Cassette or FOUP wafer carrier systems. Integrated scanners detect the exact position of the wafer in its carrier. The comprehensive but easy-to-use system software controls slot allocation, wafer warpage measurement, wafer location as well as wafer ID detection, and would even change the pick-and-place sequence automatically in case of a wafer damage threat, e.g. due to extensive or opposite bowing of neighboring wafers. A high-end dual-arm robot takes care of wafer loading and unloading. The pre-aligner module centers and aligns the wafer. A “vacuum handshake” between end-effector and pre-aligner, including wafer safeguard, secures damage-free handling of the wafer back side. Thus, high-end technology and sophisticated software control integrated in ROFIN’s Waferlase 200/300/450 guarantees highest throughput at negligible wafer breakage rates.

IGBT laser annealing

The Insulated Gate Bipolar Transistor (IGBT) market is constantly growing because of significant advantages IGBTs offer compared to other transistor devices such as high voltage capability, low ON-resistance, ease of drive, fast switching speeds, robustness, etc.

One of the key factors contributing to this market growth is the increasing demand in automotive and industrial applications, including renewable energy, communications, medical, lighting and transportation.

IGBTs are manufactured on mechanically thinned wafers with a typical thickness of 100μm or less. In order to establish a field stop and/or emitter layer on the rear side of the wafer, deep-implanted doping elements (like phosphorous or boron) have to be activated through a high-temperature annealing process towards the end of the FEOL process chain. Very often, the sensitive devices on the wafer front side are protected by an attached tape. Due to low damage temperatures of the tape, the heat-sensitivity of the front side devices, as well as a non-uniform heat distribution in the processing chamber, conventional oven activation is characterized by low activation levels and rates. ROFIN’s laser annealing process has been developed to overcome these issues and to provide significantly higher process stability and yield at competitive costs/wafer levels. Laser annealing deep-activates the dopants and simultaneously prevents damage to the wafer front side and the protection tape. The laser allows for precise depth control of the field stop and/or emitter layer activation in the range of up to 2μm. With activation rates exceeding 90 percent, ROFIN’s IGBT laser annealing solution is far superior to conventional methods.

Wafer marking

ROFIN’s Waferlaser 200/300/450 systems produce traceable markings on transparent, semitransparent and opaque wafer materials. Two methods – hard and debris-free marking – are used which differ in terms of process, depth and location of the mark. Debris-free marking in clean-room environment is achieved solely by melting of the silicon wafer surface.

ROFIN’s new patent-pending marking technology allows the user to precisely control the marking depth ranging from less than 1μm to 7μm. The debris-free marking process uses a tailor-made IC–marking laser source with 532nm wavelength. This dedicated solution achieves high contrast with excellent performance at small character heights.

SEMI today announced that Ajit Manocha, CEO of GLOBALFOUNDRIES, has been selected to receive the “SEMI Outstanding EHS Achievement Award — Inspired by Akira Inoue.” The Environment, Health and Safety (EHS) Award is sponsored by SEMI and will be presented on July 9 at 9:00am during the SEMICON West 2013 Opening Keynote and Ceremonies in San Francisco.

“We are pleased to present this award to Ajit Manocha for his outstanding contribution and commitment to EHS issues," said Denny McGuirk, president and CEO of SEMI.  “Ajit joins a distinguished group of semiconductor executives who have been honored by our industry for notable EHS achievement and leadership.”

“Excellence in Environment, Health and Safety is not only a mandate that we set for ourselves, but a fundamental expectation of our customers and the communities where we operate,” Manocha said. “Corporate responsibility is fundamental to our culture and our value proposition to our customers, the communities in which we live and do business, and our full range of global stakeholders.”

Manocha heads GLOBALFOUNDRIES Executive Stewards Council (ESC), the leadership forum for strategic direction and accountability for risk management, corporate responsibility and sustainability.  Manocha’s leadership has resulted in significant EHS achievements at GLOBALFOUNDRIES. Those cited by the Award committee in the selection of Manocha include:

  • Zero-Incident Safety Culture — GLOBALFOUNDRIES safety goal is to continually reduce all injuries and Manocha continually challenged the EHS and project management teams to achieve zero incidents. For example, Manocha ensured that there was a strong focus on safety metrics in the executive project reviews of the new Fab 8 in Malta, New York. GLOBALFOUNDRIES’ Singapore Fabs all received “Silver Awards” for Health and Safety presented by the Workplace Safety and Health Council and supported by the Singapore Ministry of Manpower.
  • Commitment to Eco-Efficiency in Foundry Operations — In 2012, GLOBALFOUNDRIES set corporate environmental goals to reduce GHG emissions 40 percent by 2015, electricity consumption 35 percent by 2015 and water consumption 10 percent by 2015, all normalized to a manufacturing index and compared to 2010.  Fab 8 incorporates multiple energy efficiency measures, waste heat recovery, and “idle mode” for abatement systems and vacuum pumps. Fab 1 in Dresden is powered by two energy-efficient tri-generation power plants that provide electricity, heating and cooling to fab operations, GLOBALFOUNDRIES’ Singapore utilizes reclaimed NEWater for incoming supply and achieved an energy reduction of 50 GWh in 2012, with a 2013 goal of a further 57 GWh reduction.
  • WSC Commitment to Best Practices for Perfluoro-Compound (PFC) Reduction — At the 2012 annual CEO meeting of the World Semiconductor Council (WSC), Manocha led the discussion of EHS topics, urging his fellow CEOs to take action to protect the environment, conserve resources, and achieve the WSC’s PFC reduction goal. GLOBALFOUNDRIES’ newest U.S. fab, Fab 8, meets the WSC Best Practice commitment for PFC emission reduction, and Fab 1 has incorporated best practices for PFC reduction since 1999.
  • WSC Commitment to a “Conflict-Free Supply Chain” — At the 2013 WSC meeting, Manocha  championed a “Conflict-free Supply Chain” policy to address concerns related to sourcing tantalum, tungsten, tin and gold from “conflict regions” of the Democratic Republic of Congo and adjoining countries. The WSC subsequently adopted such a policy. For its part, GLOBALFOUNDRIES has already met customer requests for “Tantalum Conflict-free” products in 2012.

In addition to receiving the EHS Award at SEMICON West, Manocha will deliver the Opening Keynote for the event on July 9 at 9:00am at Moscone Center (Esplanade Hall, Keynote Stage) in San Francisco, Calif.  For more information about SEMICON West — including registration and keynote attendance —   visit http://www.semiconwest.org.

The “Outstanding EHS Achievement Award — Inspired by Akira Inoue” is sponsored by the EHS Division of SEMI. The award is named after the late Akira Inoue, past president of Tokyo Electron Limited and a strong advocate of EHS. Inoue also served on the SEMI Board of Directors. The award recognizes individuals in industry and academia who have made significant contributions by exercising leadership or demonstrating innovation in the development of processes, products or materials that reduce EHS impacts during semiconductor manufacturing.

Past recipients of the SEMI EHS Akira Inoue Award include: Richard Templeton (president and CEO, Texas Instruments), Atsutoshi Nishida (president and CEO, Toshiba), Dr. Jong-Kap Kim (chairman and CEO, Hynix Semiconductor), Dr. Morris Chang (chairman and CEO, TSMC) and other prominent industry leaders.

 

 

Since 2008, the majority of integrated circuit production has taken place on 300mm wafers.  In terms of surface area shipped (i.e., on a normalized 200mm-equivalent wafer basis), 300mm wafers represented 56 percent of worldwide installed capacity in December 2012.  Production using 300mm wafers is forecast to steadily increase and reach 70.4 percent in 2017, according to IC Insights’ Global Wafer Capacity 2013 report (see figure).

300mm wafers

For the most part, 300mm fabs are, and will continue to be, limited to production of high-volume, commodity-type devices like DRAMs and flash memories, and very recently image sensors and power management devices; complex logic and microcomponent ICs with large die sizes; and products manufactured by foundries, which can fill a 300mm fab by combining wafer orders from many sources.

The list of companies with the most 300mm wafer capacity includes DRAM and flash memory suppliers like Samsung, SK Hynix, Toshiba, Micron, Elpida, and Nanya; the industry’s biggest IC manufacturer and dominant MPU supplier Intel; and two of the world’s largest pure-play foundries TSMC and GlobalFoundries.  These companies offer the types of ICs that benefit most from using the largest wafer size available to best amortize the manufacturing cost per die.

It is interesting to point out that when (or if) the pending acquisition of Elpida by Micron goes through as expected, the merged company will have the industry’s second-largest share of 300mm wafer fabrication capacity, trailing only fellow memory chip manufacturer Samsung.

Meanwhile, the share of the industry’s monthly wafer capacity represented by 200mm wafers is expected to drop from 32 percent in December 2012 to 21 percent in December 2017, as seen in the figure. Fabs running 200mm wafers will continue to be profitable for many more years and be used to fabricate numerous types of ICs, such as specialty memories, image sensors, display drivers, microcontrollers, analog products, and MEMS-based devices.  Such devices are certainly practical in fully depreciated 200mm fabs that were formerly used in making devices now produced on 300mm wafers.

A significant trend with regard to the industry’s IC manufacturing base, and a perhaps worrisome one from the perspective of companies that supply equipment and materials to chip makers, is that as the industry moves IC fabrication onto larger wafers in bigger fabs, the group of IC manufacturers continues to shrink in number.  There are about 61 percent fewer companies that own and operate 300mm wafer fabs than 200mm fabs.  The distribution of worldwide 300mm wafer capacity among those manufacturers is very top-heavy.  Essentially, there are only about 15 companies that comprise the entire future total available market (TAM) for leading-edge IC fabrication equipment and materials, according to the Global Wafer Capacity 2013 report.  When 450mm wafer fabrication technology comes into existence, this manufacturer group is predicted to shrink even further to a maximum of just 10 companies, and a few of those are questionable.  Despite growing momentum, IC Insights expects that 450mm wafer capacity will account for only one-tenth of a percent of global IC capacity in December 2017.

Europe’s recently launched industrial strategy to reinforce micro- and nanoelectronics manufacturing is more than just a vision — it’s a major opportunity for equipment and material suppliers to participate to large-scale investment projects, increase their holding in key technologies and reach out to new customers and markets. Implementation is already underway: the first EU funding calls for projects will start at the latest in early 2014 and discussions are already underway on investment priorities.  The recent launch of five EU projects, worth over €700 Million and bringing together over 120 partners, around 30 percent of which are small and medium enterprises, is proof that Europe can put its “money where its mouth is.” So what should you be doing to join the 10/100/20 momentum?

10/100/20 in a nutshell

Dubbed the ‘10/100/20’ strategy, the EU initiative will see €10 billion worth of EU co-funded projects (public/private investment), coupled with €100 Euros investment by the industry with the goal of 20 percent of global chip manufacturing by 2020. The aim is to focus on Europe’s strengths, pool together EU, national and regional resources and invest in specific areas that can give Europe a competitive edge globally. EU investment will cover the entire semiconductor manufacturing supply chain, from research to design and device makers. Maintaining leadership in equipment and material supply is clearly stated as an objective of the EU’s strategy, as is the integration of small and medium enterprises (SMEs) in value chains and providing them access to state-of-the-art technologies and R&D&I facilities.

Why get involved, especially as a SME

A number of companies, and small and medium enterprises in particular, may shy away from EU projects, perceiving them to be too complex to access and placing too much of an administrative burden for little financial gain. But the true value of EU projects lies in the new network you have access to: a variety of companies across the supply chain, many of who will become your new customers, and access to state-of-the-art research facilities and technologies. Take the example of the five pilot lines recently launched with combined funding from the EU, national governments and partner companies under the ENIAC program:

The European 450 Equipment Demo Line (E450EDL) will support the equipment and materials industry in the 450mm wafer size transition. 43 partners from 11 European countries will develop and test lithography, front end equipment, metrology tools and wafer handling and automation equipment. The partners include the large European research centers and equipment and device manufacturers, as well as smaller companies. The demo line will provide a world-class research infrastructure to validate tools that remain at the manufacturers’ sites, thus giving suppliers access to state-of-the-art facilities and an opportunity to share the knowledge and financial burden of testing their products. The Lab4MEMS project will create the first European pilot line for innovative technologies on advanced piezoelectric and magnetic materials, including 3D packaging, offers SMEs and fabless companies a manufacturing route for their future projects that has been difficult to access so far.

Interested? So what’s next?

Now is the time to decide on the technology trends that you want your company to follow and start reaching out to your partners and customers. If you think your technology could give Europe a competitive edge and should be part of Europe’s investment strategy, then start talking about it, show its benefits and convince people that this is the way to go. In the case of EU projects, there is strength in numbers, so start talking to your customers and your suppliers, look at what others are doing, and see how you can fit into the technology and investment trends.

The EU pledge of €10 billion worth of public/private co-financed projects will be spent gradually in the form of regular EU funding calls, the first of which is expected by end 2013. The call will set the overall requirements for project ideas: what technologies the project should focus on, what parts of the value chain should be partners to the project, the estimated overall budget and duration of the project as well as the technical details for applying for EU funding.  By the time the call has been published, you should already have an idea of what it is you want to do, who you want to work with and how you can fit your idea into the investment priorities that will be announced.

How to get connected

If you are visiting SEMICON West in San Francisco, then mark your calendar for Wednesday, July 10. At 16:00/4:00pm there will be a presentation of the new 10/100/20 strategy for Europe at the TechXpot in South Hall. Join us to find out more about the new strategy, why it’s important and how to get involved.

Your next major opportunity to meet with the equipment and materials industry, learn about the latest technologies and discuss the EU strategy is SEMICON Europa 2013 (8-10 October, Dresden, Germany).  Our programs will cover each of the major projects, including 450mm wafer processing, power electronics, MEMS, FDSOI as well as advanced packaging including 3D and TSV technologies.  They will in one way or the other all address Europe’s 10/100/20 strategy. The SEMICON Europa Executive Summit will discuss implementation of the strategy and we are also organizing an EU funding workshop with hands-on advice about how to identify funding opportunities for your company and join EU projects.

For more information on SEMICON Europa, please visit: www.semiconeuropa.org. The event in Dresden will again be co-located with Plastic Electronics Europe. The conference and exhibition is the leading international technology-to-industry and industry-to-industry event focused on organic and large area electronics. It is the premium forum in its kind where professionals in the area and from around the world meet to present and to discuss progress of topics. For more information, please visit: www.plastic-electronics.org.

 

Developers have made major progress in the technology to manufacture printed or flexible circuits, sensors, batteries and displays. But frankly it’s been hard to build applications with much market pull without logic or memory as well, and those have been much harder to make. However, now printed memory and solutions for integrating conventional silicon die into flexible systems are edging into production, to potentially improve performance for a wider range of applications.  On the display side, easily integrated printed or flexible transparent conductive films for touch screens are starting to see some market traction.

Yole Développement projects the market for printed and flexible electronics will remain a modest ~$176 million this year, but will see 27 percent CAGR to ~$950 million by 2020, driven largely by printed layers integrated into large OLED displays.

Thinning patterned die makes flexible silicon on polymer

One interesting solution to add performance to flexible electronics could be an open platform for making flexible silicon die. American Semiconductor proposes drastically thinning conventional fabricated silicon wafers, and coating them with a combination of polymers. The resultant silicon-on-polymer approach protects and eases handling of the ultra-thin die, says CEO Doug Hackler, who will discuss the technology in a program on such hybrid solutions in the emerging market program series at SEMICON West in San Francisco in July. He reports user interest for large area distributed sensing systems that include ICs within structural composites in aircraft bodies to monitor stress, for bio sensors that conform to the body, for RF for wireless data transmission from printed sensors, and for drivers for flexible displays.

The company has qualified TowerJazz’s 130nm process to make SOI CMOS for its initial flexible standard microcontroller, and has worked with the foundry to establish design rules to make an open platform for other designers to create their own flexible chips. American Semiconductor thins these fabricated wafers by standard methods down to about ~40µm. “And then from <40µm it gets trickier and more proprietary,” says Hackler. But once these flexible silicon-on-polymer die are diced and released, they can be handled pretty much like standard chips. “The dicing and release are a little different, but once the die are on tape, then it appears feasible to do traditional pick and place,” he says, noting the company intends to use printed connections instead of bonding wire or solder bumps. After assembly on a flexible substrate, perhaps by a pick-and-place module integrated on a roll-to-roll printing tool, the devices would typically be laminated or overcoated for additional protection. The company plans to follow its flexible microcontroller with a standard analog/digital converter to take in sensor data, and an RF IC to send out the data. 

Innovative solutions for assembling silicon on flexible substrates move towards production

Packaging and assembling tiny thin die on flexible substrates remains a challenge, but multiple suppliers are making progress towards solutions that are starting to edge into commercial production. One approach particularly suitable for attaching sensors to the body is the spring-like stretchy wiring developed by MC10 for attaching thin silicon die to flexible substrates, for everything from wearable heart rate and fitness monitors to sensor membranes that can be implanted directly on organs inside the body. VP of R&D Kevin Dowling reports the company’s first commercial application is in a soft skullcap from Reebok that uses flexibly connected motion sensors to measure impacts to the head.

Tiny die size could also help with both cost and attachment of rigid die to conformable substrates, although handling and assembling them then becomes more of an issue. Terepac Corp. CTO Jayna Sheats notes that plenty of logic for simple controls could be very tiny and low cost — microprocessors with ~8000 transistors like the Z-80 generation currently used for many embedded control applications take up  <70µm2 of silicon with 90nm design rules, for millions on a wafer. But the die are too tiny to make the input/output connections or to handle with traditional pick and place for packaging and assembly. So Terepac proposes a photochemical assembly process instead, picking up an array of thinned and diced chips with a sticky printhead, positioning the chips over the substrate with a tool similar to a proximity aligner, and vaporizing the proprietary polymer/adhesive behind each selected chip with a combination of heat and UV so it falls into the desired position.  Chips can then be attached to the flexible substrate by conductive adhesive, electroplating, or printed connections. The company is working with equipment manufacturing partners including Rockwell International to construct manufacturing facilities for customers with products for the Internet of Things.

Jabil reports progress in low temperature attachment technologies for use with heat-sensitive flexible substrates. And Sandia National Lab reports it’s come up with a solution for the common researchers’ problem in this field of how to build prototypes of flexible systems when the necessary ultra thin chips only come in costly wafer-level volumes. Researchers there have figured out how to thin off-the-shelf single die for developing flexible systems.

Printed memory targets low-cost, high-volume applications          

Thin Film Electronics, meanwhile, is developing systems that use its simple, low cost printed memory. The company’s 20-bit memory can be produced in volume for under ~$0.05, targeted at applications like consumer packaging, with volumes of billions of units a year where roll-to-roll printing makes most sense, says Chandrasekhar Durisety, assistant director, North America, who will give an update on the company’s progress towards commercialization at the session. Thin Film is introducing a next generation of passive array memory, in 4×4 (16 bit), 5×5 (25 bit) or 6×6 (36-bit) options, a more conventional format with fewer pads at higher density for easier addressing than its initial 20-bit in-line architecture. 

The company is working with a global consumer product maker on using low-cost printed memory to make brand authentication cost effective for a wide range of lower-priced products. It’s also working with major flexible packaging supplier Bemis Company Inc. on sensor labels for food, healthcare and consumer products that can collect and wirelessly communicate sensor information at roughly the same low cost as current color-changing chemical indicators. The digital system under development — with Thin Film’s printed memory, an electrochromic display from Acreo, and printed logic technology from PARC — stores data when the temperature exceeds a certain range, to indicate more clearly than a color gradient can whether the product is usable or not. 

Thin Film aims to add electronics to applications that currently don’t use them, to add simple intelligence at prices far below those possible with silicon, such as low-cost brand authentication, temperature sensors on packaging, or simple electronics in toys.  “Silicon die could add significant capability to printed electronics. But with fabrication and assembly it would likely be more expensive than either silicon or printed electronics alone,” suggests Durisety.”  

Market starts to develop for printed/flexible ITO replacements

Another key potential market for printed/flexible electronics is next-generation transparent conductive film to replace brittle and expensive indium tin oxide in touch screens and displays, lighting, and photovoltaics.  Touch Display Research says the market for non-ITO transparent conductors will be about $206 million this year, and grow to some $4 billion by 2020.  “High demand for touchscreens for notebook and PC size displays has created a shortage of ITO touch sensors since the end of last year to drive more interest in these technologies, and the more flexible and potentially cheaper replacement technologies are getting more mature,” notes Jennifer Colegrove, president and analyst, who will speak at the FlexTech workshop on transparent conductors. She notes that Atmel, FUJIFILM, Unipixel and Cambrios are all in some phase of production.

There is, however, a confusing range of contending options for processes and materials for these films.  Applied Materials has interesting progress in its roll-to-roll deposition technology, while FUJIFILM Dimatix targets ink jet printing the materials, and NovaCentrix offers rapid thermal curing that doesn’t heat the substrate. Materials options range from nano metal wires at Cambrios Technology, Carestream and Sinovia, to embossed and metalized patterns from Unipixel, to carbon nanotubes at Brewer Science and graphene at Nanotech Biomachines. 

These and other speakers will talk about the challenges and solutions to move printed/flexible electronics into real markets at SEMICON West’s emerging technology programs, July 9-11 in San Francisco.

· Mon, July 8: Market Symposium, SF Marriott Marquis, Keynote: “New Directions in Flexible and Printed Electronics,” Dr. Ross Bringans, VP at PARC (1:00-5:30pm)

· Tue, July 9: Materials Growth Opportunities at Both Ends of the Spectrum (1:30-3:30pm)

· Wed, July 10: FlexTech Alliance Workshop: Emerging Materials and Processes for Transparent Conductors, SF Marriott Marquis (10:00am-5:00pm)

· Thur, July 11: Integrating Conventional Silicon in Flexible Electronics at the Extreme Electronics TechXPOT, South Hall (10:30am-1:10pm)

For more information, visit www.semiconwest.org/SessionsEvents/PlasticElectronics

Paula Doe is an analyst for advanced technologies for the global trade association SEMI.