Category Archives: Online Magazines

New flash memory chips are replacing the floating gate with thin layers of material that "trap the charge." The charge trap is a sandwich of materials such as silicon-oxide-nitride-oxide-silicon (SONOS), metal-oxide-nitride-oxide-silicon (MONOS) and tantalum-aluminum oxide-nitride-oxide-silicon (TANOS), all of which are substantially smaller than the floating gate.

At the International Reliability Physics Symposium (IRPS), being held April 14-18, 2013 at the Hyatt Regency Monterey Resort & Spa in Monterey, CA, researchers from Mila Polytechnic, Micron and Intel will present a paper titled "Resolving Discrete Emission Events: a New Perspective for Detrapping Investigation in NAND Flash Memories." The authors say their results provide important insights into the fundamental scaling challenges of aggressively-scaled NAND flash technologies, where the impact of single electrons and defects becomes increasingly important.

Charlie Slayman, IRPS Vice Technical Program Chair, said that researchers looked at the effects of individual discrete traps in the tunnel oxide for 30nm NAND flash (see figure).

flash memory
Example of ΔVT, i and dti extraction from a detrapping VT transient.

"Looking at the threshold voltage over time, you can actually see the threshold voltage change in discrete quantized steps. They’ve analyzed this and determined these are individual traps in the device that are trapping and detrapping. This will have an impact on future flash technologies where single electron and defects become increasingly important," Slayman said.

Researchers are developing a new type of semiconductor technology for future computers and electronics based on "two-dimensional nanocrystals" layered in sheets less than a nanometer thick that could replace today’s transistors.

The layered structure is made of a material called molybdenum disulfide, which belongs to a new class of semiconductors – metal di-chalogenides – emerging as potential candidates to replace today’s technology, CMOS.

New technologies will be needed to allow the semiconductor industry to continue advances in computer performance driven by the ability to create ever-smaller transistors. It is becoming increasingly difficult, however, to continue shrinking electronic devices made of conventional silicon-based semiconductors.

"We are going to reach the fundamental limits of silicon-based CMOS technology very soon, and that means novel materials must be found in order to continue scaling," said Saptarshi Das, who has completed a doctoral degree, working with Joerg Appenzeller, a professor of electrical and computer engineering and scientific director of nanoelectronics at Purdue’s Birck Nanotechnology Center. "I don’t think silicon can be replaced by a single material, but probably different materials will co-exist in a hybrid technology."

The nanocrystals are called two-dimensional because the materials can exist in the form of extremely thin sheets with a thickness of 0.7 nanometers, or roughly the width of three or four atoms. Findings show that the material performs best when formed into sheets of about 15 layers with a total thickness of 8-12 nanometers. The researchers also have developed a model to explain these experimental observations.

Findings are appearing this month as a cover story in the journal Rapid Research Letters. The paper was co-authored by Das and Appenzeller, who also have co-authored a paper to be presented during the annual Device Research Conference at the University of Notre Dame from June 23-26.

"Our model is generic and, therefore, is believed to be applicable to any two-dimensional layered system," Das said.

Molybdenum disulfide is promising in part because it possesses a bandgap, a trait that is needed to switch on and off, which is critical for digital transistors to store information in binary code.

Analyzing the material or integrating it into a circuit requires a metal contact. However, one factor limiting the ability to measure the electrical properties of a semiconductor is the electrical resistance in the contact. The researchers eliminated this contact resistance using a metal called scandium, allowing them to determine the true electronic properties of the layered device. Their results have been published in the January issue of the journal Nano Letters with doctoral students Hong-Yan Chen and Ashish Verma Penumatcha as the other co-authors.

Transistors contain critical components called gates, which enable the devices to switch on and off and to direct the flow of electrical current. In today’s chips, the length of these gates is about 14 nanometers, or billionths of a meter.

The semiconductor industry plans to reduce the gate length to 6 nanometers by 2020. However, further size reductions and boosts in speed are likely not possible using silicon, meaning new designs and materials will be needed to continue progress. The research was funded by the National Science Foundation.

At the International Reliability Physics Symposium (IRPS), being held April 14-18, 2013 at the Hyatt Regency Monterey Resort & Spa in Monterey, CA, imec will present new research focused on the stress induced breakdown between the tungsten trench local interconnects (M1, M2) and metal gate in a 28nm CMOS technology. Imec’s Thomas Kauerauf will present a paper titled “Reliability of MOL local interconnects.”

The researchers found that the breakdown voltage shows strong polarity dependence (see figure).

The breakdown voltage revealed significant polarity dependence. Here the VBD data with bias applied at IM1 or the gate is shown.

“This has profound implications for estimating the end-of-life, specifically in bipolar applications,” explained Giuseppe Larosa, IRPS Technical Program Chair. “Here, bipolar means the voltage between the gate and the drain can basically change polarity. That really depends on the situation where the gate can be high and the drain can be ground, or the gate can be ground and the drain can be high. When you’re switching, you are in that situation. The total end of life can be a mix between these two situations.”

The imec authors note that, due to overlay errors, the spacing between the gate and the contact varies, resulting in large VBD and tBD variability across the wafer. They have developed a methodology for an intrinsic TDDB lifetime extrapolation with uniformity correction.

New finFETs feature high-k dielectrics, which are better than conventional silicon nitride dielectrics in that they can be thinner, yet still enable good control of the transistor’s channel region from the gate. Although high-k materials have been in use for five years or more, new reliability concerns associated with their use in finFETs have arisen, particularly bias temperature instability (BTI) and time dependent dielectric breakdown (TDDB).   

"There are two aspects of high k dielectrics that people have to face," said Giuseppe Larosa, IRPS Technical Program Chair. "BTI is again a concern with continued scaling. The second new effect of using high-k oxides is the TDDB physics is really completely different than nitride oxides. There’s been a lot of controversy on how to describe the TDDB for high-k in recent years.”

At the International Reliability Physics Symposium (IRPS), being held April 14-18, 2013 at the Hyatt Regency Monterey Resort & Spa in Monterey, CA, GLOBALFOUNDRIES will present the first large-scale stochastic BTI (particularly PBTI) study in metal gate/high-k technology, confirming fundamental BTI area scaling trends derived from conventional SiO2 technologies, and IBM will report on TDDB in high-k, and how it will lead to more accurate models.

“Contrary to nitride oxides, high-k brings a higher sensitivity of the NFET devices to PBTI. This is mostly due to the face that the high-k material can be sensitive to electron trap activation or generation so producing PBTI effects that you will not see in standard nitride oxide technologies,” Larosa said. “While in nitride oxide, NBTI is the main BTI mechanism that drives PFET aging, in high-k materials it’s both NBTI for PMOS and PBTI for NMOS that is actually producing some BTI aging.”

In a paper titled “Challenges in the characterization and modeling of BTI induced variability in Metal Gate / High-k CMOS technologies,” GLOBALFOUNDRIES researchers show that PBTI in the NFET is similar to NBTI in the pFET, but with a different type of permutation (see figure).

“The actual distribution shows a slightly different trend than the NBTI distribution,” Larosa said.  But everything can be normalized and scaled exactly the same way.

In another paper, titled “A New Formulation of Breakdown Model for High-k/SiO2 Bilayer Dielectris,” researchers from IBM show that breakdown can happen slowly.

“Gate leakage is actually starting to progressively increase until you’re going to get a hard breakdown,” Larosa said. “The distribution in the case is really bimodal. You have completely different behavior between when the first breakdown takes place versus when the oxide breakdown is actually evolving into the hard breakdown. The challenge here has been how to simulate this. This works suggest that it can be done with a Monte Carlo simulation that is based on dual-layer percolation statistical model. Why is this important? Because without this model you cannot be confident in predicting end of life, and having this type of simulation can help in making that projection that can be relevant for product level of circuit level reliability.”

The first large-scale stochastic BTI study in metal-gate/high-k transistors shows that PBTI in the NFET is similar to NBTI in the pFET, but with a different type of permutation.

It’s well-known that transistors generate heat when they’re operating, and that can have a significant impact on the chip’s reliability and longterm longevity. A small increase of 10°C–15°C in the junction temperature may result in ∼ 2× reduction in the lifespan of the device.

In conventional bulk transistors, self-heating is controlled in that the heat moves away down into the bulk of the devices. In newer FinFETS, however, it could pose a serious problem because there’s nowhere for the heat to go. 

“In finFETs, because it’s a three-dimensional structure, this self-heating is a bottleneck in scaling down,” said Giuseppe Larosa, Technical Program Chair of the IRPS. “Self-heating become a key important issue. The International Reliability Physics Symposium (IRPS) is being held April 14-18, 2013 at the Hyatt Regency Monterey Resort & Spa in Monterey, CA.

At IRPS, Intel will present new research in a paper titled “Self-heat Reliability Considerations on Intel’s 22nm Tri-Gate Technology.” This work elaborates on various measurements to observe self-heating as well as the associated reliability implications, not only in the transistors, but the overlying metal lines. “The self-heating of the finFET can locally increase the temperature in the metal wires above, enhancing  electromigration effects,” Larosa said.

Self-heating effects are investigated at various locations in the tri-gate architecture and in long metal lines with multiple finFETs underneath.  FinFET local temperature rise was linear with power and independent of gate stack (predicted by thermal modeling).  A linear trend for metal lines local temperature rise is observed as function powered FinFETs segments.

Intel emphasized the importance of well-calibrated self-heat models for process optimization for cutting-edge performance and reliability. They showed that aging during switching events is affected by local self-heat and shows sensitivity to number of fins or gate lines (see figure). 

“To calibrate the self-heating, you have to make sure that you have a good understanding of the local temperature in the structure that is under investigation,” Larosa said. “The figure shows self-heating at the device level is affecting aging of a given FET. It’s a function of the number of fins and the number of active lines per transistor. “

Self-heat manifests as a sensitivity to the fin or gate count in switching aging degradation. Here, switching conditions are accelerated to enhance the sensitivity.

 

FinFETs offer several advantages compared to traditional planar transistors, but it’s not yet clear what kind of new reliability problems might arise as FinFETs are scaled to smaller dimensions. One concern is what impact bias temperature instability (BTI), particularly negative BTI (NBTI), might have on FinFETs.

In p-channel transistors, NBTI affects small feature size devices and is quite difficult to reduce or eliminate. As feature sizes become smaller, the effects of NBTI become more pronounced, resulting in increases in threshold voltage and decreases in drain current and transconductance in p-channel devices. NBTI results from a positive charge buildup in p-channel transistors. It occurs at low negative gate-to-source voltages and does not result in an increase in gate leakage current. Rather, it affects off-state drain-to-source leakage and reduces the drive current. Generally, this problem is worse than standard hot carrier degradation because it results in permanent interface traps being generated, reducing device lifetime.

At the International Reliability Physics Symposium (IRPS), being held April 14-18, 2013 at the Hyatt Regency Monterey Resort & Spa in Monterey, CA, Intel will present a paper titled “Intrinsic Transistor Reliability Improvements from 22nm Tri-Gate Technology” that shows that FinFETs have a similar total BTI budget at application condition but, while NMOS PBTI can be reduced to near-negligible levels, NBTI sensitivity seems to increase with scaling.

Giuseppe Larosa, IRPS Technical Program Chair said that “Intel’s data suggest that when you look at the total BTI budget, it seems to be even in the finFET world, going from 32 seems to be pretty much okay, but NBTI seems to be an issue because it’s increasing with finFET scaling.” What Intel did was to compare a 32nm planar technology to 22nm finFET technology. The figure shows that 32nm technology in red and the 22nm finFET technology in blue. “You can see that they can manage to really reduce the PBTI, but the NBTI is actually getting worse with scaling,” Larosa said. “NBTI is becoming one of the key challenging issues for finFETs.”

22nm BTI is comparable to 32nm. NMOS is significantly improved due to gate optimization and WF scaling.

OLED lighting developments are taking place worldwide, with a lot of the research focused on phosphorescent OLED materials, which have a theoretical luminous efficacy four times higher than fluorescent materials. Last month, Konica Minolta unveiled its new flexible OLED lighting panels at the Lighting Fair 2013 exhibition in Tokyo. The company has developed its own blue phosphorescent materials, enabling it to commercialize the world’s first OLED panels using only phosphorescent materials.

Dual approach in OLED lighting development

Interestingly, Konica Minolta is following two paths in its development of OLED lighting. Alongside its developments of an all phosphorescent OLED panel, for which the company achieved world record performance back in 2007, the company is employing its expertise in R2R processing and is looking to develop high performing, solution-processable materials that will enable not just optimum performance but also high productivity. To that end, the company showcased fully solution processed OLED lighting panels back in 2010.

What has always been a limitation with solution processed OLEDs though is their performance characteristics, as their external quantum efficiency and lifetime have always been inferior to those of vacuum deposited OLEDs.

Konica Minolta has made strides towards bridging that gap recently, showcasing last year high performing solution processed polymer OLEDs, with performance metrics very similar to those of vacuum deposited materials, as can be seen in the graph below.

flexible OLED lighting
Comparison of external quantum efficiency and lifetime of evaporated and solution processed OLEDs at Konica Minolta. Source: Konica Minolta

Barrier layer developments

As if for completion, purposes, Konica Minolta is employing its knowhow in simultaneous deposition of multilayer coatings, vacuum deposition and dry coating and surface modification in atmospheric pressures to develop barrier layers. The company will be presenting its advances in lighting and flexible barrier layers in the IDTechEx Printed Electronics Asia event in Tokyo in July 2013.

Alongside the developments of multilayer barriers, there’s increased activity in the development of flexible glass. Asahi Glass, alongside other companies such as Schott and Corning and NEG have demonstrated thin glass at thicknesses that allow it to be flexible. It’s important to point out though that Asahi Glass has come up with an easier way to handle the super-thin (0.1 mm) glass that is increasingly being considered for use in flexible displays. The technique uses an adsorption layer to temporarily attach the 0.1-mm-thick sheet to a 0.5-mm-thick sheet of carrier glass, which is much easier to handle during fabrication of devices.

flexible glass
Asahi Glass: Flexible glass 100microns thick, rolled in a coil.

It’s important to note though that Asahi Glass doesn’t just develop glass, but is also actively developing conductive copper nanoparticle inks, alongside other major companies such as Hitachi Chemical, Intrinsiq and many more.

Anapass, Inc, a display SoC solution provider listed on the KOSDAQ, today announced that it has entered into strategic collaboration and investment agreements with GCT Semiconductor, Inc., a designer and supplier of advanced 4G mobile semiconductor solutions, to develop and commercialize mobile application processors (AP) for use in smartphones. Anapass will collaborate with GCT to develop a next-generation mobile application processor that is mated with GCT’s leading edge 4G RF/modem SoC solution. As a result, Anapass and GCT will provide a total solution platform incorporating 4G, LTE, RF, modem and AP to the explosively growing smartphone market.

Through this strategic collaboration and investment agreement, Anapass said it is securing technology and engineering resources related to the 4G LTE RF/modem platform from GCT, which is necessary for Anapass to develop a competitive mobile application processor for 4G smartphones. Anapass is also getting access to GCT’s broad 4G ecosystem including the world leading wireless operators and OEM/ODMs with which GCT has been establishing close relationships for years. As part of the agreement, Anapass is making a $30M strategic investment while seeking technology, business and strategic benefit to aid and support its mobile application processor strategy.

Anapass is a display SoC solution provider that developed and commercialized its proprietary intra-panel interface technology for flat panel TV displays known as AiPi (Advanced Intra Panel Interface). Anapass has also been a panel controller supplier for Samsung’s flat panel TV display business and has been listed on the KOSDAQ since 2010. The company has been seeking new opportunities offering the best products and business models, so Anapass said in its official press release that it intends to enter the fast-growing smartphone market in order to achieve diversification and expansion of products, customers and markets.

GCT Semiconductor is a 4G RF/modem SoC solution provider that commercialized the world’s first single-chip LTE solution based upon collaboration with LG Electronics. The LTE solution has been adopted by wireless operators including Verizon, Sprint, Metro PCS, Vodafone, Yota, YTL, SK Telecom and LG Uplus. According to a recent market research report by Forward Concepts, GCT has been ranked third in the 2012 market share of FDD-LTE baseband shipments, behind Qualcomm and Samsung. GCT recently announced that it entered into a 3G/2G IP licensing agreement with LG Electronics to support backward compatibility for 4G smartphones, and is currently developing a multi-mode 4G/3G/2G RF/modem SoC solution.

In addition, Anapass says it will leverage its technical know-how and experience from the successful commercialization of its panel controller products for flat panel TV displays in developing a competitive mobile application processor. Anapass says it is expecting that this agreement will allow the companies to introduce a competitive total 4G solution including 4G, RF, modem and application processor to the explosively growing worldwide mid-range smartphone market and to succeed in its plans for diversification and expansion of products and customers.

The same material that formed the first primitive transistors more than 60 years ago can be modified in a new way to advance future electronics, according to a new study.

Chemists at Ohio State University have developed the technology for making a one-atom-thick sheet of germanium, and found that it conducts electrons more than ten times faster than silicon and five times faster than conventional germanium.

The material’s structure is closely related to that of graphene—a much-touted two-dimensional material comprised of single layers of carbon atoms. As such, graphene shows unique properties compared to its more common multilayered counterpart, graphite.  Graphene has yet to be used commercially, but experts have suggested that it could one day form faster computer chips, and maybe even function as a superconductor, so many labs are working to develop it.

 “Most people think of graphene as the electronic material of the future,” Goldberger said. “But silicon and germanium are still the materials of the present. Sixty years’ worth of brainpower has gone into developing techniques to make chips out of them. So we’ve been searching for unique forms of silicon and germanium with advantageous properties, to get the benefits of a new material but with less cost and using existing technology.”

In a paper published online in the journal ACS Nano, he and his colleagues describe how they were able to create a stable, single layer of germanium atoms. In this form, the crystalline material is called germanane.

Researchers have tried to create germanane before. This is the first time anyone has succeeded at growing sufficient quantities of it to measure the material’s properties in detail, and demonstrate that it is stable when exposed to air and water.

In nature, germanium tends to form multilayered crystals in which each atomic layer is bonded together; the single-atom layer is normally unstable. To get around this problem, Goldberger’s team created multi-layered germanium crystals with calcium atoms wedged between the layers. Then they dissolved away the calcium with water, and plugged the empty chemical bonds that were left behind with hydrogen. The result: they were able to peel off individual layers of germanane.

Studded with hydrogen atoms, germanane is even more chemically stable than traditional silicon. It won’t oxidize in air and water, as silicon does. That makes germanane easy to work with using conventional chip manufacturing techniques.

The primary thing that makes germanane desirable for optoelectronics is that it has what scientists call a “direct band gap,” meaning that light is easily absorbed or emitted. Materials such as conventional silicon and germanium have indirect band gaps, meaning that it is much more difficult for the material to absorb or emit light.

“When you try to use a material with an indirect band gap on a solar cell, you have to make it pretty thick if you want enough energy to pass through it to be useful. A material with a direct band gap can do the same job with a piece of material 100 times thinner,” Goldberger said.

The first-ever transistors were crafted from germanium in the late 1940s, and they were about the size of a thumbnail. Though transistors have grown microscopic since then—with millions of them packed into every computer chip—germanium still holds potential to advance electronics, the study showed.

According to the researchers’ calculations, electrons can move through germanane ten times faster through silicon, and five times faster than through conventional germanium. The speed measurement is called electron mobility.

With its high mobility, germanane could thus carry the increased load in future high-powered computer chips.

“Mobility is important, because faster computer chips can only be made with faster mobility materials,” Golberger said. “When you shrink transistors down to small scales, you need to use higher mobility materials or the transistors will just not work,” Goldberger explained.

Next, the team is going to explore how to tune the properties of germanane by changing the configuration of the atoms in the single layer.

Lead author of the paper was Ohio State undergraduate chemistry student Elizabeth Bianco, who recently won the first place award for this research at the nationwide nanotechnology competition NDConnect, hosted by the University of Notre Dame. Other co-authors included Sheneve Butler and Shishi Jiang of the Department of Chemistry and Biochemistry, and Oscar Restrepo and Wolfgang Windl of the Department of Materials Science and Engineering.

The research was supported in part by an allocation of computing time from the Ohio Supercomputing Center, with instrumentation provided by the Analytical Surface Facility in the Department of Chemistry and Biochemistry and the Ohio State University Undergraduate Instrumental Analysis Program. Funding was provided by the National Science Foundation, the Army Research Office, the Center for Emergent Materials at Ohio State, and the university’s Materials Research Seed Grant Program.

SPIE leaders said they were encouraged to see proposed increases in funds for scientific research and development and a greater emphasis on STEM education in President Obama’s 2014 budget proposal released last Wednesday. At the same time, they stressed the importance of making applied research high priority, and expressed concerns about some funding levels.

The White House proposal includes an 8.4 percent increase over the 2012 enacted level for the National Science Foundation (NSF). Funding would rise for the NSF to an annual $7.6 billion. The budget for the Department of Energy’s Office of Science would increase by 5.7 percent, to $5 billion.

All told, the President’s 2014 budget proposes $143 billion for federal research and development, providing a 1 percent increase over 2012 levels for all R&D, and an increase of 9 percent for non-defense R&D.

“While the budget continues this Adminstration’s unflinching support for science and recognition of the importance of photonics to our future economy and health, I have some concerns,” said Eugene Arthurs, CEO of SPIE, the international society for optics and photonics. “In these times of constraint, It is very encouraging to see proposed increases for NSF, DOE science, and NIST (National Institute of Standards and Technology), and the investment in the NOAA (National Oceanic and Atmospheric Administration) earth observations program is overdue. But it is disturbing to see both NASA and NIH R&D budgets reduced, in real terms.”

Arthurs said that the decrease for NIH is particularly troubling because health issues are changing with demographics and risks are expanding with global disease mobility. He cited recognition by NIH director Francis Collins of the potential for imaging coupled with the power and possible economies from more use of data tools as ways to address those challenges.

A strong proposal, Arthurs said, is the Brain Research through Advancing Innovative Neurotechnologies (BRAIN) initiative announced by the President. The initiative would be launched with approximately $100 million in funding for research supported by the NIH, Defense Advanced Research Projects Agency (DARPA), and NSF.

“The decrease in real terms, compared with 2012 budgets, for defense basic and applied research and advanced technology development is worrying,” Arthurs said. “We need to better understand the deep cuts in defense development when this is where our security has come from and also where for decades there has been much spillover into our tech industry.”

To remain competitive in the global economy, the nation would benefit from even stronger support of applied research, Arthurs said.

“Canada and the European Union are among regions that have established policies focusing priority on applied research, and for good reason,” he said. “Applied research is concerned with creating real value through solving specific problems ― creating new energy sources, finding new cures for disease, and strengthening the security and stability of communication systems. Its metrics are improvements in the functioning of society as a whole and in the quality of individual human lives, not those of laboratory animals, and in patents and new inventions that spark economic growth, not just journal citations.”

That focus on applications is reflected in work being done by the National Photonics Initiative (NPI) committee to raise awareness of the positive force of photonics on the economy and encourage policy that promotes its development. Born out of the National Academies report issued last year on “Optics and Photonics, Essential Technologies for Our Nation,” the NPI is being driven by five scientific societies: SPIE, the international society for optics and photonics; OSA; LIA; IEEE Photonics Society; and APS.

The President’s budget proposal also moves 90 STEM programs across 11 different agencies under the jurisdiction of the Department of Education. This "reorganization" aims to "improve the delivery, impact, and visibility of STEM efforts," the budget document said.