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memsstar Limited, a provider of etch and deposition equipment and technology solutions to manufacturers of semiconductors and MEMS, today announced the appointment of Tony McKie as its new chief executive officer (CEO). McKie is tasked with capitalising on the company’s experience and reputation in the semiconductor and MEMS markets to drive its growth.

"memsstar is poised to take advantage of the significant growth potential of the MEMS and remanufactured semiconductor equipment markets," said Peter Connock, chairman of the board of memsstar. "Both MEMS and remanufactured equipment are forecast to see continuing growth over the next few years. Tony, with his industry experience and in-depth knowledge of technology, is ideally suited to ensure we maximize our opportunities in these markets. We look to Tony to advance our MEMS technology beyond our present capabilities and drive our efforts to expand our remanufactured equipment and services business."

Europe remains a center for semiconductor technology development in emerging applications along with the cost-effective manufacture of legacy products, both of which benefit from production-ready remanufactured legacy semiconductor processing equipment — a market poorly supported by conventional suppliers. Under McKie’s guidance, memsstar will expand its portfolio of process capabilities and services to better supply the needs of its customers.

At the same time, single wafer dry release etch is seeing global adoption by the leading advanced MEMS manufacturers to overcome the process challenges associated with traditional wet etch and batch etch processes. memsstar’s proprietary sacrificial vapour release etch technology is market-proven and positioned to take advantage of emerging requirements for MEMS manufacturing.

"Tony has been a key resource as the company has developed," said Andrew Elder, non-executive director representing Albion Ventures. "His extensive knowledge of the industry, together with his vision for ongoing development and expansion, makes him the obvious choice to lead the company through its next stage of growth."

As one of memsstar’s founders, McKie was responsible for developing the memsstar range of technology products and managing business development activities for the single wafer release etch platforms. He brings an extensive background in semiconductor equipment manufacturing through prior management roles at Electrotech, Lam Research and Applied Materials.

Alliance Memory today extended its 128M and 256M lines of high-speed CMOS synchronous DRAMs (SDRAM) with new devices in a 54-ball 8 mm by 8mm by 1.2mm TFBGA package. These 8M x 16 and 16M x 16 SDRAMs feature fast access time from clock down to 4.5 ns at a 5-ns clock and clock rates of 143MHz.

The devices released today are optimized for medical, industrial, automotive, and telecom applications requiring high memory bandwidth, and are particularly well-suited to high-performance PC applications. The SDRAMs operate from a single +3.3-V (0.3 V) power supply and are lead (Pb)- and halogen-free.

The AS4C8M16S-7BCN and AS4C16M16S-7BCN provide programmable read or write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. An auto pre-charge function provides a self-timed row pre-charge initiated at the end of the burst sequence. Easy-to-use refresh functions include auto- or self-refresh while a programmable mode register allows the system to choose the most suitable modes to maximize performance.

Alliance Memory’s legacy ICs provide reliable drop-in, pin-for-pin-compatible replacements for a number of similar solutions. The AS4C8M16S-7BCN and AS4C16M16S-7BCN are the latest in the company’s full line of high-speed SDRAMs, which includes devices with densities of 16 Mb, 64 Mb, 128 Mb, 256 Mb, and 512 Mb in the 54-pin TSOP II, 54-ball TFBGA, 86-pin TSOP II, and 90-ball BGA packages.

The global semiconductor materials market decreased 2 percent in 2012 compared to 2011 while worldwide semiconductor revenues declined 3 percent. Revenues of $47.11 mark the first decline in the semiconductor materials market in three years.

Total wafer fabrication materials and packaging materials were $23.38 billion and $23.74 billion, respectively. Comparable revenues for these segments in 2011 were $24.22 billion for wafer fabrication materials and $23.62 billion for packaging materials. 2012 is the first time packaging materials revenues exceeded wafer fabrication materials revenues. A substantial decline in silicon revenue contributed to the year-over-year decrease to the total semiconductor materials market.

For the third year in a row, Taiwan is the largest consumer of semiconductor materials with record spending of $10.32 billion due to its large foundry and advanced packaging base. Materials markets in China and South Korea also experienced increases in 2012, benefiting from strength in packaging materials. The materials market in Japan contracted 7 percent, with markets also contracting in Europe, North America, and Rest of World. (The ROW region is defined as Singapore, Malaysia, Philippines, other areas of Southeast Asia and smaller global markets).

2011-2012 Semiconductor Materials Market by World Region
(Dollar in U.S. billions; Percentage Year-over-Year) 

Region 2011 2012 %Change
Taiwan 10.11 10.32 2%
Japan 9.21 8.53 -7%
Rest of World 8.21 8.09 -1%
South Korea 7.27 7.33 1%
China 4.87 5.07 4%
North America 4.86 4.74 -2%
Europe 3.31 3.03 -8%
Total 47.84 47.11 -2%

Source: SEMI April 2013

Note: Figures may not add due to rounding.

The Material Market Data Subscription (MMDS) from SEMI provides current revenue data along with seven years of historical data and a two-year forecast. A year subscription includes four quarterly updates for the material segments reports revenue for seven market regions (North America, Europe, ROW, Japan, Taiwan, South Korea, and China). The report also features detailed historical data for silicon shipments and revenues for photoresist, photoresist ancillaries, process gases and leadframes.

 

Controlling the shapes of nanometer-sized catalytic and electrocatalytic particles made from noble metals such as platinum and palladium may be more complicated than previously thought.

Using systematic experiments, researchers have investigated how surface diffusion – a process in which atoms move from one site to another on nanoscale surfaces – affects the final shape of the particles. The issue is important for a wide range of applications that use specific shapes to optimize the activity and selectivity of nanoparticles, including catalytic converters, fuel cell technology, chemical catalysis and plasmonics.

Results of the research could lead to a better understanding of how to manage the diffusion process by controlling the reaction temperature and deposition rate, or by introducing structural barriers designed to hinder the surface movement of atoms.

“We want to be able to design the synthesis to produce nanoparticles with the exact shape we want for each specific application,” said Younan Xia, a professor in the Wallace H. Coulter Department of Biomedical Engineering at Georgia Tech and Emory University. “Fundamentally, it is important to understand how these shapes are formed, to visualize how this happens on structures over a length scale of about 100 atoms.”

The research was reported April 8 in the early online edition of the journal Proceedings of the National Academy of Sciences (PNAS). The research was sponsored by the National Science Foundation (NSF).

Controlling the shape of nanoparticles is important in catalysis and other applications that require the use of expensive noble metals such as platinum and palladium. For example, optimizing the shape of platinum nanoparticles can substantially enhance their catalytic activity, reducing demand for the precious material, noted Xia, who is a Georgia Research Alliance (GRA) eminent scholar in nanomedicine. Xia also holds joint appointments in the School of Chemistry and Biochemistry and the School of Chemical and Biomolecular Engineering at Georgia Tech

“Controlling the shape is very important to tuning the activity of catalysts and in minimizing the loading of the catalysts,” he said. “Shape control is also very important in plasmonic applications, where the shape controls where optical absorption and scattering peaks are positioned. Shape is also important to determining where the electrical charges will be concentrated on nanoparticles.”

Though the importance of particle shape at the nanoscale has been well known, researchers hadn’t before understood the importance of surface diffusion in creating the final particle shape. Adding atoms to the corners of platinum cubes, for instance, can create particles with protruding “arms” that increase the catalytic activity. Convex surfaces on cubic particles may also provide better performance. But those advantageous shapes must be created and maintained.

Natural energetic preferences related to the arrangement of atoms on the tiny structures favor a spherical shape that is not ideal for most catalysts, fuel cells and other applications. 

In their research, Xia and his collaborators varied the temperature of the process used to deposit atoms onto metallic nanocrystals that acted as seeds for the nanoparticles. They also varied the rates at which atoms were deposited onto the surfaces, which were determined by the injection rate at which a chemical precursor material was introduced. The diffusion rate is determined by the temperature, with higher temperatures allowing the atoms to move around faster on the nanoparticle surfaces. In the research, bromide ions were used to limit the movement of the added atoms from one portion of the particle to another.

Using transmission electron microscopy, the researchers observed the structures that were formed under different conditions. Ultimately, they found that the ratio of the deposition rate to the diffusion rate determines the final shape. When the ratio is greater than one, the adsorbed atoms tend to stay where they are placed. If the ratio is less than one, they tend to move.

“Unless the atomic reaction is at absolute zero, you will always have some diffusion,” said Xia, who holds the Brock Family Chair in the Department of Biomedical Engineering. “But if you can add atoms to the surface in the places that you want them faster than they can diffuse, you can control the final destination for the atoms.”

Xia believes the research may also lead to improved techniques for preserving the unique shapes of nanoparticles even at high operating temperatures.

“Fundamentally, it is very useful for people to know how these shapes are formed,” he said. “Most of these structures had been observed before, but people did not understand why they formed under certain conditions. To do that, we need to be able to visualize what happens on these tiny structures.”

Xia’s research team also studied the impact of diffusion on bi-metallic particles composed of both palladium and platinum. The combination can enhance certain properties, and because palladium is currently less expensive than platinum, using a core of palladium covered by a thin layer of platinum provides the catalytic activity of platinum while reducing cost.

In that instance, surface diffusion can be helpful in covering the palladium surface with a single monolayer of the platinum. Only the surface platinum atoms will be able to provide the catalytic properties, while the palladium core only serves as a support.

The research is part of a long-term study of catalytic nanoparticles being conducted by Xia’s research group. Other aspects of the team’s work addresses biomedical uses of nanoparticles in such areas as cancer therapy.

“We are very excited by this result because it is generic and can apply to understand and control diffusion on the surfaces of many systems,” Xia added. “Ultimately we want to see how we can take advantage of this diffusion to improve the catalytic and optical properties of these nanoparticles.”

The research team also included Xiaohu Xia, Shuifen Xie, Maochang Liu and Hsin-Chieh Peng at Georgia Tech; and Ning Lu, Jinguo Wang and Professor Moon J. Kim at the University of Texas at Dallas.

 CITATION: Xia, Xiaoho, et al., “On the role of surface diffusion in determining the shape or morphology of noble-metal nanocrystals,” (Proceedings of the National Academy of Science, 2013). http://www.pnas.org/content/early/2013/04/05/1222109110

Silex Microsystems, the world’s largest pure-play MEMS foundry, and BroadPak, a provider of ultra-high performance 2.5D silicon interposer and 3D integration technologies, today announced the immediate availability of their jointly developed silicon interposer solution in high-volume manufacturing. Leveraging the advanced interposer co-design methodology and system integration expertise of BroadPak with the proven interposer manufacturing capabilities of Silex, this new solution delivers a cost-effective, ultra-high performance, reliable and high-yield silicon interposer that will enable a broader market to realize the benefits of 2.5D packaging. 

 While market analyst firm Yole Dévelopement expects the market for interposers to grow by 88 percent annually through 2017, Silex and BroadPak believe their partnership can accelerate this market adoption by overcoming the cost, engineering, reliability and supply chain bottlenecks.  3D-IC designs are widely recognized as the next step towards meeting the growing performance requirements such as increased bandwidth, reduced latency, and lower power.  2.5D silicon interposers, which are double-sided die used to stack chips side-by-side, have emerged as the most effective way to accelerate the adoption of 3D-IC, but these solutions are costly and complex, which presents significant design, integration, reliability and supply chain challenges. Recognizing these bottlenecks, Silex and BroadPak believe their new 2.5D silicon interposer product solves these hurdles that have prevented many companies from participating in this space.

“This partnership is a critical step in enabling companies to benefit from silicon interposers because most companies don’t have the integration techniques and methodologies to even start a 2.5D IC design and the current solutions have been too costly and high-risk to implement,” said Peter Himes, Vice President of Marketing and Strategic Alliances for Silex Microsystems.  “The combined Silex/BroadPak solution opens up this market to a very large portion of customers that have been unable to compete in this space due to overwhelming cost, engineering and integration challenges.”

“BroadPak and Silex have created a technical solution and the supply chain infrastructure that the industry has been waiting for,” said Farhang Yazdani, President and CEO of BroadPak. “To date, silicon interposer technology has been limited to a very small number of companies. We are now enabling the mass adoption of silicon interposer by lowering the cost and providing the co-design, heterogeneous integration and the required supply chain infrastructure in a complete package.”

 The Silex/Broadpak finished product consists of a robust interposer for 2.5D packaging, which has been designed and characterized for thermal-stress and signal integrity performance by BroadPak and also optimized for manufacturing by Silex. The unique challenges of 2.5D/3D-IC packaging require special engineering expertise to deliver cost effective solutions to meet the reliability, warpage and signal/power integrity requirements of the packaged components as well as an optimized and robust manufacturing process.

In an effort that will accelerate commercialization of extreme ultraviolet (EUV) lithography technology and the development of next-generation transistors, SEMATECH announced today that Intermolecular, Inc. has joined SEMATECH’s Lithography and Front End Processes (FEP) programs. The companies have agreed to co-develop new methods to reduce overall cost of ownership (CoO) for Extreme UltraViolet (EUV) lithography, and to co-explore new materials, processes, and integration schemes for advanced logic integrated circuit technologies. 

“There are technology gaps the industry needs to address to enable cost-effective insertion of EUV lithography at the 22nm half-pitch,” said Stefan Wurm, SEMATECH’s director of lithography. “SEMATECH is pleased to welcome Intermolecular as a partner. We will work together to accelerate the investigation and qualification of chemical formulations needed to establish a production-worthy EUV lithography technology.”

Intermolecular’s High Productivity Combinatorial platform provides disruptive research and development (R&D) capability that allows for prototyping and characterization of atomic-scale devices at rates 10-100 times faster than can be achieved with conventional approaches. Such methodologies and technologies will be used in both of the program collaborations.

“As semiconductor dimensions are scaled down further, contact resistance remains a critical issue,” said Tony Chiang, Chief Technology Officer, Intermolecular. “Our unique capabilities to accelerate R&D across leading-edge semiconductor processes and devices complement SEMATECH’s expertise in advanced CMOS test structures and process flows. We are pleased to join in this pre-competitive collaboration intended to accelerate the transfer of new technologies into industry.”

Intermolecular’s mission is to improve R&D efficiency in the semiconductor and clean energy industries through collaborations that use its HPC platform.

Plessey today announced that samples of its Gallium Nitride (GaN) on silicon LED products are today available. These entry level products are the first LEDs manufactured on 6-inch GaN on silicon substrates to be commercially available anywhere in the world. Plessey is using its proprietary large diameter GaN on silicon process technology to manufacture the LEDs onits 6-inch MAGIC (Manufactured on GaN I/C) line at its Plymouth, England facility. The use of Plessey’s MAGIC GaN line using standard semiconductor manufacturing processing provides yield entitlements of greater than 95% and fast processing times providing a significant cost advantage over sapphire and silicon carbide based solutions for LEDs of similar quality.

The release of the availability of Plessey’s GaN on silicon LEDs was coincident with a visit to the Plessey Plymouth facility by the Rt. Hon. Dr. Vince Cable, MP, Secretary of State for Business Innovation and Skills and President of the Board of Trade. Business Secretary Vince Cable commented, “The government is supporting innovative companies like Plessey who are growing, creating jobs and exporting their products all over the world. That’s why we selected Plessey’s £3.25 million Regional Growth Fund bid for Government support, which will create 100 new, high tech and highly skilled jobs in the region.”

Michael LeGoff, CEO Plessey said, “We are very pleased to welcome Secretary of State Vince Cable today. The department of Business Innovation and Skills has been very supportive of our efforts to date and with the launch of our first range of LEDs today we are now looking towards aggressive growth in the solid state lighting markets.”

“Today is a significant step for us,” said Barry Dennington, Plessey’s COO. “From acquiring our first MOCVD reactor in August 2012 to having our first product in April 2013 is excellent progress. These entry level products will be used in indicating and accent lighting applications. We will continue to make progress in output efficiency and are on plan to release further improvements in light output throughout this year and into next. The operating and unit costs are on plan and we are seeing a number of routes to enhance our cost advantage over competing technologies.”

LEDs and the associated solid state lighting solutions are due to become the dominant form of lighting in all forms in within the next five years. Solid state lighting is an energy efficient eco-friendly technology that will save billions of tons of carbon emissions when fully implemented. There are also no recycling issues that fluorescent lighting poses with mercury content.

Cadence Design Systems, Inc. today announced an ongoing multi-year agreement with TSMC to develop the design infrastructure for 16-nanometer FinFET technology, targeting advanced node designs for mobile, networking, servers and FPGA applications. The deep collaboration, beginning earlier in the design process than usual, will effectively address the design challenges specific to FinFETs — from design analysis through signoff — and will deliver the infrastructure necessary to enable ultra low-power, high-performance chips.

FinFETs help deliver the power, performance, and area (PPA) advantages that are needed to develop highly differentiated SoC designs at 16 nanometers and smaller process technologies. Unlike a planar FET, the FinFET employs a vertical fin-like structure protruding from the substrate with the gate wrapping around the sides and top of the fin, thereby producing transistors with low leakage currents and fast switching performance. This extended Cadence-TSMC collaboration will produce the design infrastructure that chip designers need for accurate electrical characteristics and parasitic models required for advanced FinFET designs for mobile and enterprise applications.

"The FinFET device requires greater accuracy, from analysis through signoff, and that is why TSMC is teaming with Cadence on this project," said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. "This collaboration will enable designers to use the new process technology with confidence earlier than ever before, allowing our mutual customers to meet their power, performance and time-to-market goals."

"Producing the design infrastructure necessary for these types of complex, groundbreaking processes requires close collaboration between foundries and EDA technology innovators," said Chi-Ping Hsu, senior vice president, Silicon Realization Group at Cadence. "In joining with TSMC, a leader in FinFET technology, Cadence brings unique technology innovations and expertise that will provide designers with the FinFET design capabilities they need to bring high-performance, power-efficient products to market."

STMicroelectronics has introduced the world’s smallest TVS diode for protecting sensitive electronics in consumer products and handhelds.

As the first such device to be offered in the industry’s smallest standard surface-mount outline of 0.45 x 0.2mm, the ESDAVLC6-1BV2 is one size smaller than today’s 0.6 x 0.3mm devices.

The value of the space saving to designers can be seen by comparing with other chip sizes used in smartphones and tablets.

"A complete motion-sensing IC for features such as indoor navigation and advanced user interface, such as ST’s LSM303D, measures just 3 x 3mm, while some power chips are as small as 2 x 2mm," explains Eric Paris, product marketing director, ASD & IPAD Division, STMicroelectronics. "Trimming 0.2mm or 0.1mm from each TVS can simplify placing components and routing connections, especially if the design contains several such devices."

The ESDAVLC6-1BV2 TVS diode fully satisfies the protection requirements specified in the international standard IEC 61000-4-2. Although other types of electrostatic-discharge (ESD) protectors, such as varistors, are available in the same size, these generally do not protect as effectively. ST’s new ESDAVLC6-1BV2 has a clamping voltage half that of the nearest competing varistor in the same size package, offering greater safety for the internal components. Although useful in many applications, varistors also age, providing progressively less protection with each ESD event clamped.

David DiPaola is Managing Director for DiPaola Consulting a company focused on engineering and management solutions for electromechanical systems, sensors and MEMS products.  A 17-year veteran of the field, he has brought many products from concept to production in high volume with outstanding quality.  His work in design and process development spans multiple industries including automotive, medical, industrial and consumer electronics.  He employs a problem solving-based approach working side-by-side with customers from startups to multi-billion dollar companies.  David also serves as Senior Technical Staff to The Richard Desich SMART Commercialization Center for Microsystems, is an authorized external researcher at The Center for Nanoscale Science and Technology at NIST and is a Senior Member of IEEE. Previously, he has held engineering management and technical staff positions at Texas Instruments and Sensata Technologies, authored numerous technical papers, is a respected lecturer and holds 5 patents.  To learn more, please visit www.dceams.com.   

The fourth article of the MEMS new product development blog is Part 2 of the critical design and process steps that lead to successful prototypes.  In the last article, the discussion focused on definition of the customer specification, product research, a solid model and engineering analysis to validate the design direction.  The continuation of this article reviews tolerance stacks, DFMEA, manufacturing assessment and process mapping.       

A tolerance stack is the process of evaluating potential interferences based on the interaction of components’ tolerances.  On a basic level, a cylinder may not fit in a round hole under all circumstances if the cylinder’s outside diameter is on the high size and the inside diameter of the hole is on the lower size causing an interference when there is an overlap of their tolerances.  This situation can become complex when multiple components are involved because it results in the number of variables reaching double digits.  A simple approach to tolerance stacks is using a purely linear or worst case approach where full tolerances are added to determine potential for interference.  However, experience from producing millions of sensors shows this approach is overly conservative and a non optimal design practice.  If tolerances of the assembly follow a normal distribution, are statistically independent, are bilateral and are small relative to the dimension, a more realistic approach is a modified root sum of the squares (MRSS) tolerance stack technique.  In this approach the root sum of the squares of the tolerances are multiplied by a safety factor to determine the maximum or minimum geometry for a set of interrelated components.  The safety factor accounts for cases where RSS assumptions are not fully true.  This approach is only recommended when 4 or more tolerances are at play.  If only 2 tolerances are present as in the first example above, it is recommended to perform a linear tolerance stack.  In some cases, linear tolerances need to be added to a MRSS calculation (MRSS calculation + linear tolerances = result).  Pin position inside a clearance slot for anti-rotation is linear tolerance that is added to a MRSS calculation.  Reasoning for this is the pin can be any location in the slot at any given time and does not follow a normal statistical distribution. 

An example of a MRSS tolerance stack is provided below to review this concept in more detail.    Let’s determine if the wirebond coming off of the sense element will interfere with the metal housing.  A modified RSS tolerance stack shows line to line contact and only a small adjustment in the design is needed to resolve the issue.  The linear tolerance stack shows a significant interference what requires a larger adjustment.  Dimensions and tolerances are illustrative only.

Figure 1: MEMS Sensor Package (mm)

Figure 2

Modified Root Sum Square Versus Linear Tolerance Stack Approaches

 0.17 > SF*(((T1^2) + (T2^2) + (T3^2) + (T4^2) + (T5^2))^(0.5))        

MRSS Approach

0.17 > 1.2*((0.01^2 + 0.05^2 + 0.025^2 + 0.10^2 + 0.08^2)^0.5) = 0.17

0.17 > T1 + T2 + T3 + T4 + T5       

Linear Approach

0.17 > 0.01 + 0.05 + 0.025 + 0.1 + 0.08 = 0.27

An excellent text on this subject is Dimensioning and Tolerancing Handbook, by Paul J. Drake, Jr. and published by McGraw-Hill.

DFMEA, design failure mode and effects analysis. is another tool that is extremely effective to identify troublesome areas of the design that need to be addressed to prevent failures in validation and the field.  Simply put this is a systematic approach to identify potential failure modes and their effects and finding solutions to mitigate the risk of a potential failure.  A Risk Priority Number (RPN) is then established based on rating and multiplying severity, occurrence and detection of the failure mode (severity*occurrence*detection = RPN).  The input to the tool is the design feature’s function, the reverse of the design function, the effect of the desired function not being achieved, and the cause of the desired function not being achieved.  There is also an opportunity to add design controls prevention and detection.  The outputs are the corrective actions taken to mitigate risk of a potential failure. Figure 3 shows an brief example of this approach for a MEMS microphone.

Figure 3: Design Failure Mode and Effects Analysis

Further information on DFMEA can be found at Six Sigma Academy or AIAG.  Corrective action section left out of illustration for clarity.

 It is also extremely important that the manufacturing process be considered from the first day of the design process.  Complete overlap of design and process development are the true embodiment of concurrent design.  The following illustration depicts this well:

Figure 4: Concurrent Design

Hence before a MEMS design is started, discussions should be initiated with the foundry, component fabrication suppliers and the process engineers responsible for the package assembly.  These meetings are excellent times to review new capabilities, initial ideas and explore new concepts.   Considering the design from a process perspective simultaneously with other design requirements leads to highly manufacturable products that are often lowest cost.    In essence, the design engineer is performing a constant manufacturing assessment with each step in the design phase.  This methodology also encourages process short loops in the design phase to develop new manufacturing steps.  This expedites the prototype process with upfront learning and provides feedback to the design team for necessary changes.  The additional benefit of this approach is the boarder team is on board when prototyping begins as they had a say in shaping the design.   

Another tool to thoroughly understand the process in the design phase is process mapping.  Using this methodology, process inputs, outputs, flow, steps, variables, boundaries, relationships and decision points are identified and documented.  The level of detail is adjustable and to start there can be a broad overview with more detailed added as the design progresses.  This quickly provides a pictorial view of the process complexity, the variables effecting the design function, gaps, unintended relationships and non value added steps.  It can also be used as a starting point for setting up the sample line in a logical order to assemble prototypes, estimating cycle time and establishing rework loops.  To further clarify this method, a partial process map for a deep reactive ion etch process is provided:

Figure 5: Partial Process Map of Deep Reactive Ion Etch Process

This process map is not all inclusive but illustrative of the process flow, critical parameters, inputs and a decision point.  The personal protection equipment, tools used and relationships in the process are omitted for brevity.  With this level of process detail available to the design team, the complexity of feature fabrication can be evaluated, anticipated variation from process parameters can be analyzed and much more possibly prompting design changes. 

 Knowledge of and attention to detail in these eight critical, yet often overlooked steps are essential in the design of highly manufacturable, low cost and robust products.  These methodologies create a strong foundation upon which additional skills are built to provide a balanced design approach.  In next month’s blog, the design review process and a checklist will be discussed to help engineers prepare for this important peer review process.