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Solid State Technology is pleased to announce that Dr. An Steegen, Senior Vice President of Process Technology at imec, will be presenting on CMOS scaling by 10nm at The ConFab 2013. In her presentation, Steegen will explain the paradigm shift underway in the semiconductor industry, where chip scaling is possible with the right materials and new design architectures to enable tomorrow’s smart systems.

“To answer the industry’s need for extreme computation and storage capabilities, bound by (ultra) low-power or heat dissipation constraints, we have to push the limits of transistor scaling,” Steegen writes in her abstract. “To reach ultra-small dimensions beyond 10nm, advanced patterning processes, new materials with high electron mobility – such as germanium, IIIV materials or graphene – and new device architectures – such as FinFETs and TunnelFETs – with heterojunctions will be required, as well as a reduction in process complexity and variability control New memory concepts are also on the rise, including resistance based memories, such as resistive RAM, phase-change RAM or spin-torque transfer magneto resistive RAM and vertical Flash memory. These advanced memory technologies further reduce cost and maximize density. Introduction of the third dimension will allow for even more functionality, compute power and memory on a chip.”

Steegen holds a Ph.D. in Material Science and Electrical Engineering from the Catholic University of Leuven, KU Leuven, in collaboration with the Interuniversity Microelectronics Center, imec, in Belgium. Throughout the years, Steegen has published more than 30 technical papers and she holds many patents in the field of semiconductor development. She joined IBM Semiconductor R&D in Fishkill, NY, in 2001, where she was the director of the bulk CMOS technology development division until 2010. In that position, she served as the host executive in charge of IBM’s logic International Semiconductor Development Alliance and was responsible for establishing strong collaborative partnerships in innovation and manufacturing as measured by power/performance, defect density and cost/complexity.

For more information on speakers or to register, visit The ConFab section of our website.

Roger Grace, President of Roger Grace Associates, a MEMS marketing organization, will debut the results of his annual “Barriers to the Successful Commercialization of MEMS: The 2012 MEMS Commercialization Report Card” at the annual Smart Systems Integration Conference and Exhibition to take place at Amsterdam, The Netherlands on March 13/14, 2013.  The Report Card market research project, which provides letter “grades” to the 14 critical success factors for MEMS commercialization, was developed by Roger Grace Associates based on significant research he conducted on the topic of technology commercialization.  Begun in 1998 and reporting yearly on the state of the MEMS industry’s commercialization efforts worldwide, it is universally considered to be a truly unique, objective and accurate assessment tool by MEMS community leaders to monitor the status of the progress of the commercialization of MEMS on a year-by-year basis and to develop strategies to exploit opportunities.

“The 2012 Report Card market study demonstrated yet another successful year for the MEMS community to participate in having their voices heard on their opinions of the current state of commercialization efforts of the MEMS industry,” Grace said. “Over 65 MEMS industry leaders participated in the study.  They represented a true sample of MEMS industry suppliers, users and infrastructure organizations worldwide equating to over 1300 years of aggregate experience in the MEMS industry.  Not only did the participants provide letter grades to the 14 topics but additionally contributed valuable comments as to their opinions and rationale for the grades which uncovered many interesting issues.”

The overall grade of the 2012 MEMS Commercialization Report Card maintained its B- level from its 2011 level with changes in a number of grades from their 2011 levels.  Among the most significant changes was “Design for Manufacturing and Test,” which went from B+ in 2011 to B- in 2012 and represented the second consecutive year of the decline.  The “Market Research” grade declined from B in 2011 to B- in 2012 and also representing a second consecutive year decline.  Increased grades included “Profitability,” which rose from C- in 2011 to C in 2012, thus coming back from its low of D in 2010. ”Cluster Development” increased from C in 2011 to C+ in 2012.  One of the most striking results was the continuing low grade of D+ for “Venture Capital Attraction” for the third consecutive year and at reporting period low of D in 2009.

“Based on the results of the study, it is apparent that the MEMS industry has a  great deal of room for improvement, especially in the business areas of ‘Profitability,’ ‘Venture Capital Attraction’ and “Creation of Wealth,’” Grace commented. “I would have expected to see much more promising grades in these areas since we are now very strongly coming out of the Crisis of 2008 and especially since several market studies have pegged the growth of the MEMS market in the high teens for 2012.  However, the results did not support this.  I believe that these 14 critical success factor topics are the “vital signs” of the MEMS industry.  Their respective grades reflect the true “health” of the MEMS industry based on the select group people who I have interviewed, their experience and knowledge of the industry and their representation of the various sectors of the MEMS ecosystem worldwide.”

The 2012 MEMS Commercialization Report Card will be available on the Roger Grace Associates website beginning on March 13. The final study results, including “verbatim” comments from the participants is scheduled for publication on April 15 and will also be available on the Roger Grace Associates website.  Mr. Grace will present the findings of the 2012 MEMS Commercialization Report Card at a webinar sponsored by the MEMS Industry Group on April 2, 2013 at 11:30 a.m.

Roger Grace Associates, headquartered in Naples Florida, was founded in 1982.  It provides strategic marketing services to the MEMS and sensors community worldwide including strategic marketing communications, branding and positioning, market research, product launching  and  due diligence.  Its list of clients represents the “who’s who” of MEMS organizations from Fortune 500 companies to startups and government agencies.

 

The new Galaxy S4 from Samsung Electronics joins a growing trend of premium smartphones featuring enhanced active-matrix organic light-emitting diode (AMOLED) panels, spurring the market for these high-quality displays to more than double by 2017.

AMOLED display shipments for mobile handset applications are expected to grow to 447.7 million units in 2017, up from 195.1 million units in 2013, according to insights from the IHS iSuppli Emerging Displays Service at information and analytics provider HIS. Within the mobile handset display market, the market share for AMOLED displays is forecast to grow from 7.9% in 2013 to 15.2 percent in 2017, as presented in the figure below. AMOLED’s market share for 4-inch or larger handset displays employed in smartphones is set to increase to 24.4% in 2017, up from 23.0% in 2013.

AMOLED display shipments

“Because of their use in marquee products like the Galaxy S4, high-quality AMOLEDs are growing in popularity and gaining share at the expense of liquid crystal display (LCD) screens,” said Vinita Jakhanwal, director for mobile & emerging displays and technology at IHS. “These attractive AMOLEDs are part of a growing trend of large-sized, high-resolution displays used in mobile devices. With the S4 representing the first time that a full high-definition (HD) AMOLED has been used in mobile handsets, Samsung continues to raise the profile of this display technology.”

AMOLED on display in the S4

For its new premium smartphone, Samsung Display—the AMOLED display supplier for Samsung Electronics—increased the AMOLED pixel format to 1920 by 1080 Full High Definition (Full HD), up from 1280 x 720 WXGA present in the Galaxy S III. Part of Samsung’s popular Galaxy line, the S4 joins several high-end smartphone models from other manufacturers also featuring 1920 by 1080 resolution but distinguished by an important difference. The other handsets use thin-film transistor LCD (TFT-LCD) displays, while the Galaxy S4 is the first Full HD smartphone utilizing an AMOLED display.

Among the handsets with 1920 by 1080 TFT-LCD panels are the 4.8-inch HTC One, the 5.0-inch Sony Xperia Z, the 5.0-inch ZTE Grand S, the 5.0-inch OPPO Find, the 5.5-inch LG Optimus G Pro and the 5.5-inch Lenovo Ideaphone K900.

Samsung tackles technical issues

The high-resolution mobile handset display market is currently dominated by Low-Temperature Polysilicon (LTPS) TFT-LCDs, which accounts for the entire Full HD mobile handset display market.

Reaching the high-resolution point with true pixel densities greater than 300 pixels per inch (ppi) has been a challenge for AMOLED displays, as it is difficult to achieve dense pixel arrangements using the conventional Fine Metal Mask process while still securing enough display brightness and not compromising power consumption.

Samsung Display, however, was able to enhance AMOLED display performance by implementing two new technologies in addition to its existing Fine Metal Mask process. The maker succeeded in increasing the lighting area in AMOLED panels with its new structure of Pentile matrix, and it used phosphorescent material for the green subpixels, allowing better light management and lower energy consumption.

As a result, the AMOLED display was able to achieve a denser pixel arrangement, boosting its pixel density to greater than 400 ppi and resulting in 1920 x 1080 Full HD display in the Galaxy S4. This compares to 1280 x 720 WXGA in the Galaxy S III, 800 x 480 WVGA in the Galaxy S2 and 1280 x 800 WXGA in the Galaxy Note. The higher pixel density provides sharper and more defined images, while being able to display more content on a smaller display area.

Samsung also implemented the Floating Touch system in Galaxy S4, allowing users to interact with the touch screen by letting their fingers hover a few inches away from the display. By combining mutual capacitance, the on-surface normal touch sensing and self-capacitance, the Floating Touch in the Galaxy S4 expands the user experience of the display. It also detects touch inputs from gloved hands, a feature that was first introduced through Nokia’s Lumia 920 in 2012.

Galaxy S4 will be the first Full HD AMOLED display offering in the market. However, material lifetime, color balance and limited supplier base still need to be addressed for a larger market presence of OLEDs and stronger competitiveness against LTPS TFT-LCDs.

DNA nanotechnology

The fundamental unit in Hao Yan’s new nanostructures rely on modifying a 4-arm DNA junction. The relaxed DNA geometry found in a 4-arm junction (B) can be rotated 150 degrees clockwise or 30 degrees counterclockwise (C) to form the right angles needed to make a DNA Gridiron (D and E).

Photo by: Biodesign Institute

In a new discovery that represents a major step in solving a critical design challenge, Arizona State University Professor Hao Yan has led a research team to produce a wide variety of 2-D and 3-D structures that push the boundaries of the burgeoning field of DNA nanotechnology.

The field of DNA nanotechnology utilizes nature’s design rules and the chemical properties of DNA to self-assemble into an increasingly complex menagerie of molecules for biomedical and electronic applications. Some of the Yan lab’s accomplishments include building Trojan horse-like structures to improve drug delivery to cancerous cells, electrically conductive gold nanowires, single molecule sensors and programmable molecular robots.

With their bio-inspired architectural works, the group continues to explore the geometrical and physical limits of building at the molecular level.

"People in this field are very interested in making wire frame or mesh structures," said Yan. "We needed to come up with new design principles that allow us to build with more complexity in three dimensions."

In their latest twist to the technology, Yan’s team made new 2-D and 3-D objects that look like wire-frame art of spheres as well as molecular tweezers, scissors, a screw, hand fan, and even a spider web.

The Yan lab, which includes ASU Biodesign Institute colleagues Dongran Han, Suchetan Pal, Shuoxing Jiang, Jeanette Nangreave and assistant professor Yan Liu, published their results in the March 22 issue of Science.

The twist in their ‘bottom up,’ molecular Lego design strategy focuses on a DNA structure called a Holliday junction.

In nature, this cross-shaped, double-stacked DNA structure is like the 4-way traffic stop of genetics – where 2 separate DNA helices temporality meet to exchange genetic information. The Holliday junction is the crossroads responsible for the diversity of life on Earth, and ensures that children are given a unique shuffling of traits from a mother and father’s DNA.

In nature, the Holliday junction twists the double-stacked strands of DNA at an angle of about 60-degrees, which is perfect for swapping genes but sometimes frustrating for DNA nanotechnology scientists, because it limits the design rules of their structures.

"In principal, you can use the scaffold to connect multiple layers horizontally," [which many research teams have utilized since the development of DNA origami by Cal Tech’s Paul Rothemund in 2006]. However, when you go in the vertical direction, the polarity of DNA prevents you from making multiple layers," said Yan. "What we needed to do is rotate the angle and force it to connect."

Making the new structures that Yan envisioned required re-engineering the Holliday junction by flipping and rotating around the junction point about half a clock face, or 150 degrees. Such a feat has not been considered in existing designs.

"The initial idea was the hardest part," said Yan. "Your mind doesn’t always see the possibilities so you forget about it. We had to break the conceptual barrier that this could happen."

In the new study, by varying the length of the DNA between each Holliday junction, they could force the geometry at the Holliday junctions into an unconventional rearrangement, making the junctions more flexible to build for the first time in the vertical dimension. Yan calls the backyard barbeque grill-shaped structure a DNA Gridiron.

"We were amazed that it worked!" said Yan. "Once we saw that it actually worked, it was relatively easy to implement new designs. Now it seems easy in hindsight. If your mindset is limited by the conventional rules, it’s really hard to take the next step. Once you take that step, it becomes so obvious."

The DNA Gridiron designs are programmed into a viral DNA, where a spaghetti-shaped single strand of DNA is spit out and folded together with the help of small ‘staple’ strands of DNA that help mold the final DNA structure. In a test tube, the mixture is heated, then rapidly cooled, and everything self-assembles and molds into the final shape once cooled. Next, using sophisticated AFM and TEM imaging technology, they are able to examine the shapes and sizes of the final products and determine that they had formed correctly.

This approach has allowed them to build multilayered, 3-D structures and curved objects for new applications.

"Most of our research team is now devoted toward finding new applications for this basic toolkit we are making," said Yan. "There is still a long way to go and a lot of new ideas to explore. We just need to keep talking to biologists, physicists and engineers to understand and meet their needs."

Yan’s research is funded by several grants from the National Science Foundation, Office of Naval Research, Army Research Office grant and an Army Research Office MURI award, and an ASU Presidential Strategic Initiative Fund. Hao Yan and Yan Liu are part of the Center for Bio-Inspired Solar Fuel Production, an Energy Frontier Research Center funded by the U.S. Department of Energy, Office of Science, Office of Basic Energy Sciences.

Hao Yan is the Milton Glick Chair in the Department of Chemistry and Biochemistry and researcher at ASU’s Biodesign Institute.

Volunteers sponsored by SPIE, the international society for optics and photonics, were in Washington, D.C., last week to thank Congressional representatives for recent support for photonics R&D and to urge future support for in several key areas vital to economic growth and scientific progress. They were among more than 250 scientists, engineers, and business leaders visiting Capitol Hill March 12-13 for a Congressional Visits Day (CVD) sponsored by the Science-Engineering-Technology (SET) Work Group.

  • SPIE volunteers focused primarily on three messages identified by the SPIE Engineering, Science, and Technology Policy (ESTeP):
  • Support for a National Photonics Initiative (NPI) being forwarded by a coalition of professional societies including SPIE, LIA (Laser Institute of America), IEEE Photonics Society, OSA (The Optical Society), and the American Physical Society.
  • Overhaul of export controls.
  • Eliminating restrictions on government-employee travel to scientific conferences.

Members and staff were generally in agreement that now is a critical time for the U.S. to be prioritizing investments in science and innovation and that while control of spending is important, funding for R&D and for STEM education are important ways to grow the economy.

"I appreciate the preparations by SPIE to support those of us working in photonics to succinctly bring our message to our representatives in Congress,” said Jim McNally, director of operations at Applied Technology Associates. “The background materials and coaching tips provided really help us to clearly and concisely articulate the critical priorities to support our nation’s competiveness and innovation edge. We were able to have very productive discussions emphasizing the urgency for a National Photonics Initiative."

Ben Franta, a student at Harvard University, called the event “an eye-opening experience.”

“In the same way that being a scientist or engineer is very different from what most other people imagine it to be, our government operates in a way that’s different from what we might expect by watching or reading the news,” he said.

Franta said the CVD program was “a valuable opportunity to engage with our lawmakers in a way that can lead to real results. To me, the fact that SPIE makes such great use of this opportunity — both to communicate with Congress and to educate students like me — shows a forward-looking approach to promoting technologies in optics and photonics in this country and throughout the world."

An evening reception provided an informal opportunity for CVD participants to talk with Congressional members and staff, and included an exhibition in which company representatives demonstrated products based on discoveries and innovations resulting from federal R&D funding. SPIE co-sponsored a booth highlighting the recent National Academies report, “Optics and Photonics: Essential Technologies for our Nation,” and raising awareness of efforts to create the NPI.

At the reception, the SET George E. Brown Award was presented to Representatives Mike Honda (D-California) and Richard Hanna (R-New York), to recognize their outstanding efforts to advance and promote science, engineering, and technology on Capitol Hill.

More than 50 percent of all industrial innovation and growth in the United States since World War II can be attributed to advances pioneered through scientific research, with publicly funded R&D the vital foundation for today’s scientific and technological progress.

Technology transfer from academic research adds billions of dollars to the economy each year and supports hundreds of thousands of jobs.

SPIE is the international society for optics and photonics, a not-for-profit organization founded in 1955 to advance light-based technologies. The Society serves nearly 225,000 constituents from approximately 150 countries, offering conferences, continuing education, books, journals, and a digital library in support of interdisciplinary information exchange, professional networking, and patent precedent. SPIE provided over $3.2 million in support of education and outreach programs in 2012.

MagnaChip Semiconductor Corporation, a Korea-based designer and manufacturer of analog and mixed-signal semiconductor products, and Sidense Corp., a developer of logic non-volatile memory one-time programmable (OTP) memory IP cores today announced that Sidense’s SLP 1T-OTP macros have been fully qualified for MagnaChip’s 180nm 1.8/3.3/18V high-voltage CMOS and mixed-signal process. Semiconductor devices fabricated in these processes are used in applications such as LED lighting controllers, display controllers and power-management ICs (PMICs) for mobile and other high-volume applications.

"Leading semiconductor device manufacturers are already using Sidense 1T-OTP macros for LED energy management solutions fabricated using MagnaChip’s leading process technology," said Tom Schild, Sidense’s Vice President of Worldwide Sales and Marketing. "By offering our very dense and low-power SLP memory macros in MagnaChip’s HV process, customers have a proven platform in which they can take full advantage of the benefits of 1T-OTP memory and its cost-effectiveness, reliability and security advantages over eFuse, mask ROM and other NVM technologies."

SLP macros are available in a comprehensive range of off-the-shelf configurations ranging from 128 bits for trim and configuration applications up to 256 Kbits per macro for code storage and multiple NVM uses. Benefits of Sidense’s SLP OTP include small footprints to minimize cost, low power consumption, field-programmability, available configurations with word widths up to 128 bits and fast read access to allow executing code from OTP for many applications.

Headquartered in South Korea, MagnaChip Semiconductor is a Korea-based designer and manufacturer of analog and mixed-signal semiconductor products for high volume consumer applications.

Sidense Corp. provides secure, very dense and reliable non-volatile, one-time programmable (OTP) memory IP for use in standard-logic CMOS processes with no additional masks or process steps required. Sidense SiPROM, SLP and ULP memory products, embedded in more than 250 customer designs, are available from 180nm down to 28nm and are scalable to 20nm and below.

The Institute of Microelectronics (IME), a research institute of the Agency for Science, Technology and Research (A*STAR) in Singapore, has launched the Copper (Cu) Wire Bonding Consortium II. The consortium which rides on the successes of Phase I launched in 2010 aims to improve the reliability of semiconductor devices by tackling copper wire bonding issues related to corrosion and stress. Members of this consortium span across the semiconductor supply chain including Atotech S.E.A., GLOBALFOUNDRIES, Heraeus Materials and Infineon Technologies.

Copper, which offers favorable cost, performance, quality and reliability benefits over gold, has become one of the preferred materials for wire bonding interconnects in microelectronics. Today, however, the industry still faces many technical challenges in developing copper as the best choice for chip-to-package interconnection. One of the key technical issues is related to copper’s hardness relative to gold, which requires bonding parameters to be very well controlled in order to eliminate the risk of damaging bond pads and underlying structures. Another daunting challenge of using copper is its reactivity with oxygen in the surrounding air which causes corrosion-related problems. These two issues can affect the reliability and quality of semiconductor devices.

Against this background, the IME Cu Wire Bonding Consortium II will conduct a study on corrosion and the mechanisms on the effect of various packaging materials. To understand the effects of copper wire hardness when bonding on different materials, the consortium will carry out modeling and characterization of copper wire bonding stress using stress sensors developed under the scope of Phase I of the Cu Wire Consortium to provide an improved technique of measuring wire bonding stress. The outcome of this work will enable semiconductor manufacturers as well as test and packaging houses to develop solutions to improve product reliability, especially those targeted at high reliability applications.

"IME has been dominant in the R&D of advanced packaging technologies and remains focused on developing solutions to help the industry reduce manufacturing costs,” said Prof. Dim-Lee Kwong, Executive Director of IME. “We are excited to begin a new phase of the Cu Wire Bonding Consortium to enable the development of robust, high reliability and low cost interconnection solutions."

“GLOBALFOUNDRIES is pleased to be in this consortium as the first phase of our partnership has successfully resulted in optimizing 0.7 mil in copper wire bonding on our 40nm product and passed the JEDEC reliability test,” said Mr. K. C. Ang, Senior Vice President and General Manager for GLOBALFOUNDRIES Singapore. “The success has brought us to the next phase of collaboration where the process will be tested on our advanced 28nm product. We see this industry collaboration truly augmenting the value proposition we have on offering quality and cost effective wafer manufacturing to our customers.”

“Infineon has been part of the Copper Wire Bonding Consortium since it first launched in 2010,” said Mr. Guenter Mayer, Senior Director, Package Technology and Innovation, Infineon Technologies Asia Pacific. “Today, our interest lies in copper wire bond interconnect performance and reliability in semiconductors that can meet the stringent quality requirements of Automotive and Industrial applications.”

“Being a member of the consortium enables Heraeus to work with strong industry partners and research institutes in order to have more in-depth understanding of wire bond reliability. The consortium members are of various backgrounds, such as wafer manufacturers, mold compound manufacturers and end users. The wafer manufacturers design pad structures that cater for the harder copper wire which created challenges on 1st bond mechanical stress during bonding and package reliability due to corrosion. Other partners are mold compound manufacturers and end users who can equally contribute to materials and assessment on best combination of package design, materials and application solution,” said Mr. Bernd Stenger, Executive Vice President, Contact Materials Division, Heraeus Materials Technology.

Advances in petawatt photonics, laser systems, optical sensing, holography, metamaterials, nonlinear and quantum optics, and related topics will be presented by leading experts at SPIE Optics + Optoelectronics in Prague next month. The weeklong conference will also feature sessions for industry and presentation of three prestigious awards from the International Commission for Optics (ICO).

More than 600 technical papers on the latest developments in optics and optoelectronic devices, technologies, and their integration will be presented at SPIE Optics + Optoelectronics 2013 next month. The international symposium will be held at the Clarion Congress Hotel in the historic city of Prague, Czech Republic, April 15-18, 2013.

Conferences will cover recent advances in petawatt photonics, high-power and high-repetition rate systems, diode-pumped laser systems, and FELs, along with the latest research in optical sensing, holography, x-ray optics, metamaterials, nonlinear and quantum optics.

Attendees will be able to learn first-hand about new developments in ground-breaking intense laser-matter interaction research, inspired by what will be the future site of one of the world’s most advanced laser facilities, ELI Beamlines. The facility, expected to be open to users by January 2016, will serve researchers in laser science as well as other fields including material sciences, engineering, medicine, biology, chemistry, and others with its multifunctional and user-friendly design.

A two-day exhibition running April 16-17 will connect researchers with more than twenty suppliers and project partners from around the world who provide optical instruments and systems to address an ever-increasing number of industrial and research applications, in areas such as imaging and vision, defence, telecommunications, space, transportation, industrial process control, and laser fusion.

A special technical session on the prospects for inertial fusion energy (IFE) will feature invited speakers from the HiPER and LIFE laser energy projects.

ICO, the International Commission for Optics, will present three of its annual awards during the event, with talks by award winners:

Industry-focused sessions include:

  • A one-day Laser Energy Workshop emphasising engagement with industry as an important element of the Laser Energy roadmap, both in a facility delivery context and also as assurance that arising technological advances are exploited for shorter-term economic impact, along with discussion of the key enabling technologies and the underlying physics of laser-driven fusion and progress to “first ignition” at NIF.
  • A one-day National Science Foundation (NSF) Workshop on “US-Czech frontiers in photonics,” covering non-linear optics, EUV-soft x-rays, microstructured and specialty fibers, optical sensors, optical manipulators, metamaterials, and THz and Mid IR photonics.
  • An afternoon workshop for ELI prospective users, bringing together researchers who are developing and building the ELI Beamlines facility with members of the community of prospective users of proposed beamlines and end-stations. Several roundtable discussions will be held to identify and specify the most promising user experiments.
  • Symposium General Chairs are Jiří Homola of the Institute of Photonics and Electronics of the Academy of Sciences of the Czech Republic (IPE/ASCR), Chris Edwards of the UK Central Laser Facility, Science and Technology Facilities Council, Mike Dunne of Lawrence Livermore National Lab, and Ivo Rendina of the Instituto per la Microelettronica e Microsistemi. Miroslav Miler (IPE/ASCR) is Honorary Chair.

Accepted conference proceedings papers will be published in the SPIE Digital Library as soon as approved after the meeting, and in print volumes and digital collections.

SPIE is an international society for optics and photonics, a not-for-profit organization founded in 1955 to advance light-based technologies.

The Semiconductor Machinery Manufacturing industry has been highly volatile during the past five years.

“Demand from the industry is determined by conditions in the downstream semiconductor manufacturing, which is characterized by rapid technological change,” said IBISWorld industry analyst Andrew Krabeepetcharat.

Industry performance also derives from downstream demand for electronic products that use semiconductors. Revenue is expected to decline at an average annual rate of 0.5% to $1.7 billion during the five years to 2013, largely due to a decline in demand from downstream manufacturing.

Revenue declined quickly in 2009 as semiconductor manufacturers postponed machinery purchases in the midst of the recession.

“Downstream demand for products that use semiconductors also experienced weaker demand during the period,” said Krabeepetcharat.

Industry revenue fell 33.3% in 2009 but bounced back 32.7% in 2010. Despite a quick recovery, growth quickly slowed and came to a small decline through 2013, with revenue falling 0.9% from the previous year. Over the five years to 2018, industry revenue is projected to grow slowly.

The Semiconductor Machinery Manufacturing industry has a moderate level of concentration. IBISWorld estimates that the four largest industry operators will account for less than 15.0% of industry revenue in 2013, down from about up from about 44.0% in 2008. Several firms left the industry in 2009 with the number of firms falling 10.7% during the year, contributing to the increase in market share concentration. During the five years to 2013, the number of industry firms is projected to decline at an average annual rate of 3.0% to 24 companies. Over the next five years, the number of industry firms is expected to decline at an average annual rate of 2.6% to 21 firms as major companies acquire smaller competitors and other firms move operations overseas.

Exports account for a large share of revenue, accounting for about 54.1% in 2013. International trade of industry products fell heavily during the economic downturn as global demand fell and semiconductor manufacturers delayed capital investments. During the past five years, the value of exports is expected to increase at an average annual rate of 2.1% to $923.5 million. Imports also declined during the economic downturn, increasing at an average annual rate of 1.0% to $243.0 million in 2013.

ChipStart LLC, a provider of semiconductor intellectual property (SIP), and DELTA Microelectronics, a provider of ASIC services for the semiconductor industry, announced a new joint venture this week. The relationship will involve the sale, marketing and global representation of DELTA’s design services, including its production and test capabilities through ChipStart’s extensive sales channel.

“We are extremely pleased to be in a position to take advantage of DELTA’s intimate knowledge of the mobile payment, RFID and sensor markets and to be able to offer their extensive portfolio of solutions,” said Howard Pakosh, President and Chief Executive Officer of ChipStart. “By officially recognizing this partnership, we are continuing to grow our capabilities and services giving our customers the tools necessary to develop next generation technologies.”

“DELTA Microelectronics is happy to team with ChipStart. Their portfolio is complementary to DELTA’s, so we expect that our customers can gain significant synergies from this cooperation,” said DELTA’s Vice-President of Sales and Marketing, Gert Jørgensen.

ChipStart will promote DELTA Microelectronics’ ASIC Design Services to system houses and semiconductor communities throughout North America, with the specific focus on chips used in the areas of mobile payment systems, RFID, optical systems and sensor systems.

ChipStart is a semiconductor intellectual property solution company based in Palo Alto, California. ChipStart provides sales, marketing, and support engagement solutions for companies that commerce third party semiconductor intellectual property, high quality pre-verified subsystem solutions, and support design services for ASIC and fabless semiconductor companies. ChipStart products are used as critical components of communications, consumer and computing products including switches, routers, modems, cellular phones, set-top boxes, HDTVs, DVD players and PCs.