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North America-based manufacturers of semiconductor equipment posted $1.07 billion in orders worldwide in February 2013 (three-month average basis) and a book-to-bill ratio of 1.10, according to the February Book-to-Bill Report published today by SEMI.  A book-to-bill of 1.10 means that $110 worth of orders were received for every $100 of product billed for the month.

The three-month average of worldwide billings in February 2013 was $975.3 million. The billings figure is 0.8 percent higher than the final January 2013 level of $968.0 million, and is 26.3 percent lower than the February 2012 billings level of $1.32 billion.

book-to-bill ratio semiconductor industry Feb 2013

“Three-month average bookings and billings posted by North American semiconductor equipment providers remain above parity and consistent with prior month levels," said Denny McGuirk, president and CEO of SEMI. "We expect modest investment by semiconductor makers in the first half of the year with foundry and advanced packaging technology among the near-term spending drivers.”

The SEMI book-to-bill is a ratio of three-month moving averages of worldwide bookings and billings for North American-based semiconductor equipment manufacturers. Billings and bookings figures are in millions of U.S. dollars.

The data was compiled by David Powell, Inc., an independent financial services firm, without audit, from data submitted directly by the participants. SEMI and David Powell, Inc. assume no responsibility for the accuracy of the underlying data.

The data is contained in a monthly Book-to-Bill Report published by SEMI. The report tracks billings and bookings worldwide of North American-headquartered manufacturers of equipment used to manufacture semiconductor devices, not billings and bookings of the chips themselves. The Book-to-Bill report is one of three reports included with the Equipment Market Data Subscription (EMDS).

SEMI is the global industry association serving the nano- and micro-electronic manufacturing supply chains. SEMI maintains offices in Bangalore, Beijing, Berlin, Brussels, Grenoble, Hsinchu, Moscow, San Jose, Seoul, Shanghai, Singapore, Tokyo, and Washington, D.C.

 

David DiPaola is Managing Director for DiPaola Consulting a company focused on engineering and management solutions for electromechanical systems, sensors and MEMS products.  A 16 year veteran of the field, he has brought many products from concept to production in high volume with outstanding quality.  His work in design and process development spans multiple industries including automotive, medical, industrial and consumer electronics.  Previously, he has held engineering management and technical staff positions at Texas Instruments and Sensata Technologies, authored numerous technical papers and holds five patents.  To learn more, please visit www.dceams.com.   

 

In the third article of the MEMS new product development blog, critical design and process steps that lead to successful prototypes will be discussed.  These items include definition of the customer specification, product research, a solid model, engineering analysis to validate design direction, tolerance stacks, DFMEA, manufacturing assessment and process map.  With the modeling and analysis tools available and short loops for both design validation and process development, it is possible and should be expected to have functional prototypes on the first iteration.     

Read David’s first installment of the MEMS new product development blog.

Thorough review of the customer specification and an understanding of the application are two of the most critical steps in developing a prototype.  Without this knowledge, its a guess on whether the design will be successful meeting the performance objectives with next to zero quality problems.  The issues often encountered are the customer specification is poorly defined, it does not exist or there are gaps between customer targets and supplier performance.  It is the responsibility of the lead engineer to work with the customer to resolve these issues in the beginning stages of the prototype design to ensure a functional prototype is achieved and is representative of a product that can be optimized for production.   Furthermore, this specification creates an agreement between the supplier and customer on expectations and scope.  Should either of these change during the project, the deliverables, cost and schedule can be revisited.  Expectations and scope include package envelope, application description, initial and performance over life specifications, environmental, mechanical and electrical validation parameters, schedule and quantities for prototype and production.  In this process the supplier and customer review each item of the specification and mark it as acceptable as written or needs modification to be met given current knowledge.  There can also be area of further research and development before an agreement on the topic can be reached.  This entire process is documented and signed by both parties as a formal contract.  Then as more is learned about both the product design and application, modifications to the agreement can (and likely will) occur with consent of both parties. 

Product research is another area of significant importance to the prototype process. This research has several branches including technology to be used, existing intellectual property, materials, design approaches, analysis techniques, manufacturing processes to support proposed design direction and standard components available to name a few.  Product research will also involve reaching out to experts in different fields that will play a role in the product design.  This is the initial data collection phase of learning from previous works through reading patents, journal articles, conference proceedings and text books and building a team of qualified professionals.  This process is sometimes chaotic and over whelming while wading through mounds of information in search of a viable design path.  However, this only lasts for a short period as trends start to form, innovation is birthed and a path is forged. 

Parametric, 3D modeling is no longer a luxury but a must have in the design and prototype process.  It is essential for visualizing the design, documenting it and analyzing function, geometric properties and potential interferences.  However, use of the solid model should not stop there.  The documented geometry can be imported through a live link or other means to various other tools such as CNC machining, finite element analysis, tolerance stack analysis, motion visualization, fabric pattern generation prior to stitching, mold flow analysis, electrical simulations, equipment interactions, process development and much more.  The solid model should be considered a starting point for a much larger analytical model that is used to describe the fabrication, function and performance of the product and its components.  Once the solid model is complete, it is also extremely helpful to make stereolithography (SLA) or 3D printed components that can be felt, observed and often times used for preliminary product testing.  For a trivial cost, SLA’s can provide a wealth of information prior to prototype and help sell the design to colleagues and customers. 

As highlighted in the previous paragraph, engineering analysis is the process used to validate the design and process direction theoretically.  The analysis can take the form of a manual hand calculation of deflection to the sophistication of finite element analysis predicting the strain in the diaphragm of a MEMS pressure sensor due to deformation of the surrounding package under thermal conditions.  The key to successful analysis is not only proper engineering judgment on parameters and attention to detail in model creation but validation of the analysis through experimentation or other theoretical means.  For example, the FEA results of a MEMS diaphragm under large deflection can be compared to other theoretical calculations of a round plate under large deflection that has been validated with experiment.  Correlation of the results suggest your model is in the ballpark and can be used to evaluate other parameters such as stress and strain.  In this analysis phase, the global model is often comprised of several smaller models using different analytical means that are then tied back together for a prediction of performance.  With many live links between several pieces of analytical software and the power of today’s computers, this process is becoming more efficient with better overall accuracy. 

To better illustrate the points above, a case study of a MEMS SOI piezoresistive pressure sensor will be reviewed.  This pressure sensor was designed for operating pressures of 1000 – 7000 KPa. Due to the pressure range used, the surface area of the sensor that was bonded to the mating package substrate needed to be maximized while minimizing the overall foot print to increase the number of sensors per wafer.  Hence a deep reactive ion etch was used to obtain near vertical sidewalls.  A thicker silicon handle wafer was used to provide additional strain isolation from the sensor package while staying within a standard silicon size range for lower cost.  The silicon reference cap provided a stable pressure reference on one side of the sensor diaphragm.  Its geometry was optimized for handling, processing and dicing.

A solid model was created of the design including the wirebond pads, aluminum traces, interconnects, oxide layers and piezoresistors on the silicon membrane wafer.  In addition, the cap and handle wafers were modeled.  Although not shown here for proprietary reasons, each layer of the membrane was modeled as though it was fabricated in the foundry.  This enabled the development of a process map and flow.  Finite element analysis of the diaphragm under proof pressure loads showed that the yield strength of the aluminum traces could be exceeded when in close proximity to the strain gages.  This can cause errors in sensor output.  Hence doped transition regions were added to keep the aluminum out of this high stress region.  A comprehensive model of the piezoresistive Wheatstone bridge was created to select resistor geometry and predict the performance of the sensor under varying pressure and thermal conditions.  Strain induced in the gages from applied operating pressure and resulting deflection of the diaphragm was modeled using finite element analysis.  A model was also created to determine approximate energy levels needed to dope both the piezoresistors and transition regions.  This information was critical in discussions with the foundry in order to design a product that was optimized for manufacture as doping levels and geometry were correlated.   Furthermore short process loops were developed at the NIST Nanofab to optimize etch geometry and validate burst strength. 

It is important to note that the design of the sense element was designed with constant feedback from the foundry and their preferences for manufacturing.  In addition, the sense element and packaging were designed concurrently as there was significant interactions that needed to be addressed.  Design of the sense element and packaging in series would have resulted in a non optimized design with higher cost.  In the end, a full MEMS sensor specification was developed and provided to the foundry for a production quote and schedule.  Through working directly with the foundry, optimizing die size and designing a sensor for optimum manufacture, over 60% improvement in cost was achieved over going to a full service MEMS design and fabrication facility.                        

 Read David’s previous installment of the MEMS new product development blog.

Figure 1
MEMS SOI Sense Element
Figure 2
DRIE Hole Fabricated at NIST Nanofab

 

Due to the length of these topics, stay tuned for next months blog for Part 2 of this article.  In that segment other critical steps including tolerance stacks, DFMEA, manufacturing assessment and process maps will be reviewed.

Next generation memories are the emerging non-volatile memory technologies, which are expected to replace existing memories. Not all existing memories will be replaced, however. Next generation memories majorly targets the non-volatile memories such as NAND and NOR. High write and read latency, scalability, high endurance etc. makes emerging memories the best replacement for traditional non-volatile memories. Out of these memories, only MRAM and FeRAM have reasonable market share, and they are quite commercialized in the market. PCRAM has very marginal market and memristor is set to enter the market by the end of 2013   

The major drivers for the next generation memory market are faster switching time, high endurance and power efficient. In addition, the huge application base of traditional memories will also become the driver for this market. Since these memories are not completely established, there are still flaws in processes which causes drawbacks like instability and low write endurance rate in some of the memories. As mentioned, these memories are the replacement for flash memories in near future. The flash market has already tapped the huge market and hence it makes the way for next generation memories.   

The major issue for next generation memories is its design cost. Not all the processes are intact yet, hence it increases the cost of the process and design. However, early adoption of these memories will be the game changing strategy for memory market. Most of the next generation memories are also called as “Universal memory,” which performs both the function volatile and non-volatile. So the early adoption of such memories will be the crucial for the companies.   

The companies currently involved in next generation memory market are Samsung (South Korea), SK Hynix (South Korea), Micron (U.S.), Elpida (Japan), Toshiba (Japan), Powerchip (Taiwan), Winbond (Taiwan), Fujitsu (Japan), Nanya (Taiwan), Rambus (U.S.), Everspin Technology (U.S.), IDT Incorporated (U.S.), HP (U.S.).  

Crystal IS, Inc., a manufacturer of proprietary, high-performance ultraviolet light emitting diodes (UVC LEDs) for monitoring, purification, and disinfection applications, has announced today that they achieved more than 65mW in optical output at 260nm from a single UVC LED operated in a continuous mode. The details of this breakthrough were recently published in Applied Physics Express.

"This achievement is a technological milestone in the continued development of brighter, more efficient and reliable UVC LEDs. By employing die thinning and encapsulation techniques, we were able to increase the photon extraction efficiency to over 15%, “said Leo Schowalter, founder and CTO.  "By fabricating our LEDs on our home grown aluminum nitride substrates, we continue to set the pace of what is possible for the combination of highest efficiencies and longest lifetimes in the 250-280nm wavelength range, far surpassing diodes fabricated on sapphire."

“This R&D accomplishment represents a more than six-fold increase in performance from just one year ago,” said Larry Felton, CEO. “Our progress in business operations continues on a like pace, readying us and our LEDs for commercial success.”

UVC refers to ultraviolet light with wavelengths between 200 – 280 nanometers (nm). Light in the UVC wavelength can be used for disinfecting water, sterilizing surfaces, destroying harmful micro-organisms in food products and in air, and for spectroscopy applications. Yole Développement estimates the UVC lamp market to be nearly $200 Million in 2012, with lamps being replaced increasingly by UV LEDs.

"Our products will address some of the most pressing health concerns of our time,” said Therese Jordan, Senior Vice President of Business Development. “We are seeing demand in both water and air for the disinfection and quality monitoring aspects of UVC. Similarly, spectroscopic instruments are also taking advantage of the high light output available in a UVC LED. Unlike UV lamps, UVC LEDs are mercury-free, compact, rugged and robust, lending themselves to an array of designs and hold the promise of long life and environmentally friendly end-of-life disposal.”

Engineering samples of UVC LEDs are available from Crystal IS.

UVC LED from Crystal IS

PPG Industries has been recognized by the U.S. Department of Energy (DOE) for “significant achievements” in advancing organic light-emitting diode (OLED) lighting technology. Dennis O’Shaughnessy, Ph.D., PPG associate director for flat glass research and development, accepted the award on behalf of the PPG team during the 2013 Solid-State Lighting (SSL) R&D (Research and Development) Workshop in Long Beach, Calif.

PPG’s advances are the result of a two-year project initiated with the DOE in 2010 to promote the commercialization and mass production of OLED lighting. The PPG team led by Abhinav Bhandari, Ph.D., project engineer, has demonstrated a float glass-based integrated substrate with scalable light-extraction technologies and transparent conductive films for OLED lighting applications.

The results indicate significant cost and performance advantages over conventional indium tin oxide (ITO)-coated display-grade glass substrates. PPG’s light-extraction technologies are compatible with the conventional float glass manufacturing process and result in significant enhancement of device efficiencies, according to O’Shaughnessy.

Dick Beuke, PPG vice president, flat glass, said the new glass substrate is one of several major initiatives PPG is advancing to reduce energy use in the U.S.

“At PPG, we are proud to be developing glass technologies to make OLED lighting more viable for mass use,” he said. “This research enhances and complements the work our scientists are doing in architectural glass and coatings to make homes and buildings more energy efficient, and in solar technology to help that industry achieve grid parity.”

Mehran Arbab, Ph.D., PPG director, glass science and technology, said, “OLED lights have the potential to emit four times as much light per watt as incandescent bulbs. Widespread commercial use of this technology could significantly reduce energy use in homes, buildings and workplaces.”

PPG was the only company honored in the OLED lighting area at the three-day workshop, which brought together nearly 300 researchers, manufacturers and industry insiders who are promoting and monitoring the latest developments in SSL technology. The DOE supports SSL R&D efforts to accelerate market introduction of high-efficiency, high-performance SSL products. Its mission for the SSL R&D portfolio is to “create a new, U.S.-led market for high efficiency, general illumination products through the advancement of semiconductor technologies, to save energy, reduce costs and enhance the quality of the lighted environment.”

Researchers sponsored by Semiconductor Research Corporation (SRC), a university-research consortium for semiconductors and related technologies, today announced development of a modeling process designed to simulate atomic-level etching with chemicals that are effective alternatives to widely used perfluorocarbon (PFC) gases. The novel approach under way at the University of California, Los Angeles (UCLA) will identify and evaluate green plasma chemistries for processing emerging memory/logic devices and through-silicon-via (TSV)-enabled technologies for the semiconductor industry.

In order to continue the advancement of transistor and memory cell performance, the research will focus on several promising new materials that have been introduced for future generations of integrated circuits (ICs). To exploit this opportunity, the industry requires new and effective etch processes with which to pattern the next-generation fabrics.

The aim of the UCLA research effort within the SRC-funded Engineering Research Center for Environmentally Benign Semiconductor Manufacturing (ERC) is to identify environmentally friendly chemistry for patterning materials in IC fabrication and verify their performance to be equal to, or greater than, current state-of-art plasma chemistries.

The unique performance characteristics required for advanced devices and technologies dictates the use of certain materials and corresponding aggressive etch chemistries. Next-generation processes will benefit from chemicals that are more benign, less hazardous and more efficiently utilized.

The advanced modeling approach developed by UCLA will predict emissions from plasma processes and assess the effectiveness of non-PFC etch chemistries compared to those using PFC gases. While historically PFC gases have been an enabling component of semiconductor manufacturing, the industry continues to aggressively pursue and implement PFC replacement and abatement strategies. The UCLA research will greatly assist and accelerate this industry effort.

“The industry can’t afford to conduct thousands of hands-on experiments to measure, one at a time, the chemical reactions that etch at a molecular scale,” said Dr. Jane Chang, lead researcher for the SRC-funded activity at UCLA. “With modeling, we can conduct those evaluations in a relatively short time. In terms of months rather than years, we expect to identify the conditions for a benign etch chemistry that will help to facilitate the industry’s technology roadmaps.”

Peeling Layers at the Atomic Level

Chemical vapor deposition and plasma etch have been extensively used as part of an integrated process flow to realize chip manufacturing over the last several decades. 

In this era of nanotechnology, atomic layer deposition has become a viable approach to synthesize functional materials for chip manufacturing. However, its counterpart, atomic layer etch, has not been fully developed.

The UCLA program is designed to reverse engineer the atomic layer deposition process, providing guidance for simulation of the atomic-layer etch. Such capability is projected by industry scientists to become increasingly important in order to achieve the patterning of complex and multi-layer thin-film structures.

For example, new composite or hybrid materials required for emerging memory and logic devices pose significant etch challenges that must be addressed by aggressive, yet highly selective, etch chemistries. Conversely, PFC replacement etches for TSVs, which enable 3D device integration, face a different set of challenges such as high aspect ratio and multiple interfaces. Both types of etching present difficult challenges, but also significant opportunities to enable higher density, performance and functional diversification in future ICs.

By screening potential surface reactions and applying thermodynamic and kinetics assessment to measure reaction, researchers are taking a unique approach to remove specific surface elements and design chemistries that will work better than PFCs. As a result, the model prediction provides a design of experiments that can be much more efficient and shorten the timeframe for discovery and confirmation of alternative chemicals.

“Atom by atom, this is the fastest and most affordable way to discover the best approaches for etching down to silicon and metal layers with a variety of chemicals for chipmaking,” said Farhang Shadman, Director of the SRC-funded ERC based at the University of Arizona.

Next Steps

According to the World Semiconductor Council, semiconductor manufacturers in the European Union, Japan, Korea, Taiwan and the United States voluntarily lowered PFC emissions by more than 30% between 1995 and 2010, surpassing the WSC goal to reduce emissions by 10%. UCLA predicts that its modeling approach will lead to further reductions in PFC emissions from semiconductor manufacturing, supporting the industry’s ongoing commitment to environmental protection.

An additional potential benefit of the UCLA atomic scale etch model is an improvement in throughput for chip production by identifying and confirming higher etch-rate processes.

“Needless to say, accelerating the pace of PFC replacement is an important priority for the semiconductor industry, and SRC member companies are working closely with Dr. Chang’s UCLA research team to provide both guidance and support in developing and verifying these new models,” said Bob Havemann, director of Nanomanufacturing Sciences at SRC. “This project provides an outstanding example of the vital ongoing research at the ERC, which is focused on developing ESH-preferable processes for current and future semiconductor manufacturing.”

Zvi Or-Bach, President & CEO of MonolithIC 3D Inc. and Benjamin S. Louie of Zeno Semiconductor blog about dimensional scaling as it relates to EUV and future per transistor device cost.

At the IEEE International Solid-State Circuit Conference, the issue of dimensional scaling as it relates to EUV and future per transistor device cost was an important topic in the plenary session. One important, and perhaps overlooked, aspect of the industry’s scaling issue relates to the future of the SRAM bit-cell within this framework of dimensional scaling. We would like to shine some light on this impending issue.

As widely reported in the industry and articulated by ASML’s Executive VP & CTO Martin van den Brink at ISSCC 2013, there is substantial evidence that without EUV the cost of logic transistors is most likely going up with scaling. One slide he used to illustrate this is below:

Source: ASML

The above slide arrived after Martin had presented another non-encouraging slide, showing the same view from three companies: a Broadcom chart of increasing cost per gate correlated with dimensional scaling, together with the now famous Nvidia chart of no more crossover of transistor cost below 28nm, and third a GlobalFoundries chart showing some limited value for EUV.

 

 

 

We may attribute Martin statements to ASML interest in promoting EUV, but since ASML has already received significant EUV participation from INTEL, Samsung and TSMC, it might indicate further bumps are on the road to bringing EUV to market. We don’t know if EUV will ever become real, but we do know very well that it is been delayed, and delayed again, and delayed again. It was made public recently that EUV has probably already missed the 10nm process node -“10nm will be optical,” said Ajit Manocha, chief executive of GlobalFoundries.

An even more interesting slide was presented by van den Brink:

This chart brings up an important aspect of dimensional scaling that has not been discussed much before – the scaling of the SRAM bit-cell.  According to this chart, the SRAM bit-cell size might not be reduced from the 20nm to 10 nm node, and might even get larger at 7nm as it may need more than 8 transistors. (Sound familiar? Fabs are doing the same with BEOL metallization scaling…little or none).

Modern logic devices demand a significant amount of embedded SRAM. In fact, more than 50% of the typical logic device area is allocated for these SRAM as illustrated by the following chart of Semico (June, 2010).

The dominant embedded SRAM bit-cell architecture has been the 6 transistor cell (6T). And for many years this very cell has been hand-crafted using special design rules independently developed by foundries for every new technology node. It makes sense: the SRAM cell is a unique structure that does not obey normal logic design rules as it drives output against output anytime a write cycle is being performed. In many cases it is the SRAM cell that is the most sensitive portion of the logic device to process parameter variations and this sensitivity greatly impacts end device yield.

It well known that scaling the SRAM bit-cell has become harder and harder. Some vendors have already moved away from the 6T bit-cell in preference to the 8T (eight transistors) bit-cell.  ISSCC 2013 had a significant number of papers that were presented using 8T SRAM.  The few papers who kept the 6T SRAM embedded in their logic devices were forced to add read/write support circuits and additional overhead to enable the 6T bit-cell to function reliably.

Since SRAM bit scaling is now not able to keep up with logic scaling, the overall end device cost scaling could be even more disappointing than the transistor or gate cost illustrations above. 

Of course, well aware of this trend, IBM has been promoting their embedded DRAM solution for years. In the recent Common Platform Forum Dr. Gary Patton, VP, IBM Semiconductor R& D Center, was very pleased to share that in their 32nm product line the use of the embedded DRAM has given IBM the equivalent of a process node scaling benefit. Yet, as of now, most other vendors have not adopted eDRAM due to the process complexity and cost it adds to the logic process. It fair to assume that the appetite for eDRAM will not grow with dimensional scaling as the DRAM capacitor will be very hard to scale, the extra power for supporting DRAM will not be available and the cost of advance process development to add in extra complexity will be too high.

Accordingly we can learn from the recent ISSCC that dimensional scaling is facing the cost challenges we were aware of before in addition to new challenges that we might not have been aware of: the cost and the active/passive power handicaps due to the incompatibility of the 6T SRAM  bit-cell with scaling.

As we have suggested before, now that monolithic 3D is practical, we could advance and maintain Moore’s Law by augmenting dimensional scaling with 3D IC scaling. We could enjoy depreciated equipment charges for more years and much lower R&D engineering outlays that would bring down production and development costs, and also enjoy improvements to power and performance.

Another exciting option is to replace the 6T SRAM bit-cell with the 1T bi-stable floating body memory cell invented by Zeno Semiconductor.  The Zeno bit-cell provides two stable states, analogous to an SRAM while only consuming ~20% area of a traditional 6T SRAM and requires considerably less power.  The area and power savings over a traditional 6T SRAM improve further with scaling.  Most excitingly the Zeno bit-cell is compatible with existing logic processes. 

About the authors

Zvi Or-Bach is a well-known serial entrepreneur. He founded eASIC in 1999 and served as the company’s CEO for six years. eASIC was funded by leading investors Vinod Khosla and KPCB in three successive rounds. Or-Bach also founded Chip Express in 1989 (recently acquired by Gigoptix) and served as the company’s President and CEO for almost 10 years. In 2009 he founded and incorporated MonolithIC 3D Inc., a company that developed and patented a technology breakthrough for practical monolithic 3D-ICs.

Benjamin S. Louie has more than 16 years of experience in memory design including NOR Flash, NAND Flash and MRAM.  Most recently he led design efforts at Magsil, an MRAM IP company.  Prior to Magsil, Ben worked as a Design Manger at Micron Technology where he led the design development of Micron’s NAND program. 

Samsung Electronics catapulted to the top of the optoelectronics supplier ranking in 2012 from 12th place in 2011 after it gained full ownership of Samsung LED, a 50-50 joint venture in light-emitting diodes that was created in 2009 between Samsung Electronics and affiliate Samsung Electro-Mechanics.  In April 2012, the venture was absorbed into Samsung Electronics to strengthen and expand the use of high-brightness LEDs in displays, LCD TVs, and new solid-state lighting products. This transfer increased Samsung’s optoelectronics sales by 223% to $2.5 billion in 2012 compared to $780 million in 2011, according to the new 2013 edition of IC Insights’ O-S-D Report—A Market Analysis and Forecast for Optoelectronics, Sensors/Actuators, and Discretes.

The LED operation added $1.5 billion to Samsung’s total revenues in 2012, based on the O-S-D supplier rankings in the new 350-page report, which becomes available in March 2013.  The rest of Samsung’s optoelectronics sales come from CMOS image sensors, which generated $975 million in 2012—a 25% increase from 2011.  The 2013 O-S-D Report shows Samsung as the second-largest supplier of CMOS image sensors in 2012, positioned between top-ranked OmniVision and third-place Sony.  The 2013 O-S-D Report provides top 10 supplier rankings for the individual optoelectronics, sensors/actuators, and discrete semiconductor markets in addition to an overall top 30 list of companies selling O-S-D products in 2012.

Samsung’s huge increase in optoelectronics sales vaulted it to first place in IC Insights’ top 30 O-S-D ranking for 2012 from 20th in 2011. High-brightness white LED and blue-laser pioneer Nichia in Japan moved up to second place in the O-S-D ranking from fourth place in 2011 with an 11% increase in optoelectronics sales in 2012.  In the 2012 O-S-D ranking, Toshiba and ST fell to third and fourth, respectively, due to steep sales declines in CMOS image sensors and double-digit drops in discretes.  Toshiba and ST had been the No. 1 and No. 2 suppliers in the O-S-D marketplace since the middle of the last decade.

top five O-S-D suppliers 2012

Suppliers of high-brightness LEDs generally moved higher in the overall O-S-D ranking in 2012 due to strong sales growth in lamp devices used for solid-state lighting systems.  In addition to Samsung and Nichia moving up to the No. 1 and 2 positions in O-S-D, six other LED makers climbed higher in the top 30 ranking (Sharp, Osram, Philips, LG Innotek, Seoul Semiconductor, and Toyoda Gosei). U.S.-based Cree, which makes LEDs and radio-frequency/microwave power transistors, was unchanged in the top 30 O-S-D ranking at 17th place in 2012.

Among the significant changes in the O-S-D supplier rankings was ST climbing to first place in the sensors/actuators market in 2012 from fourth in 2011.  ST’s sensor sales grew 19% in 2012 to $791 million.  Hewlett-Packard fell to fourth place in sensors/actuators last year from the top spot in 2011 due to a 10% decline in sales of HP’s inkjet-printer actuators in 2012.  In discrete semiconductors, Toshiba held on to its top position despite a 12% decline in discretes sales in 2012.

Most electronic systems that power our digital life are inflexible and flat. Rigid electronic designs work for our computers and phones but not for our bodies. Humans are soft and curved. Electronic systems capable of bending, twisting, and stretching have great potential for applications in which conventional, stiff semiconductor microelectronics would not suffice. One promising area for conformable electronics is in biomedical applications such as wearable and implantable electronic systems. Design for Reliability of Multi-Layer Thin Film Stretchable Interconnects, to be presented at the Electronic Components and Technology Conference on May 28 – 31, 2013, discusses the use of stretchable interconnects (Figure 1) and the future shape of conformable electronics.

multiple layers of stretchable interconnects
Figure 1. Multiple layers of stretchable interconnects crossing at the strain relief structure described below.

Previous stretchable interconnect designs are composed of only a single metal layer. Due to the nature of this single metal layer design, these stretchable electronic systems have large, sparse layouts. However, as the system gets more complex, single metal layer interconnects become impractical. Multi-layered stretchable interconnects allow for smaller, more intricate, and more practical systems and can be produced through conventional bottom-up micro-fabrication processes. When multiple meandering interconnects intersect, however, the junctions of the interconnects are subject to the specific orientation of each structure, complicating the design, risking the integrity of the small junction areas, and resulting in complex mechanics during stretching.

A circular structure to relieve strain at the junctions between multiple metal interconnect layers is proposed in the paper. In the proposed strain relief structure design (Figure 2), meandering horseshoe patterned metal interconnects contain circular rings that are stacked to allow the interconnects to overlap one another.  While the proposed strain relief structure is a universal design that can be applied to any number of systems with multiple interconnecting layers, structures composed of two metal layers are examined in this study.

strain relief structure design
Figure 2. Strain relief structure design with two layered intersecting interconnects.

A comprehensive investigation into the deformation behavior and failure mechanisms of the structures was carried out through both numerical and experimental analysis. Numerical analysis indicates that elongations of up to 20% cause no plastic strain in the structure, allowing it to operate indefinitely. Simulations show that the crests of the horseshoe interconnects are the regions with the greatest strain and that the structure will ultimately fail at one of these crests (Figure 3).

simulated strain distribution
Figure 3. Right: Structure imaged during testing. Left: Simulated strain distribution.

Results of electromechanical testing show that the strain relief structure can stretch up to 285% of its initial length prior to failure. Initial results from fatigue life testing of the structures has demonstrated that they are able to withstand more than one million cycles of 100% elongation at a 200% per second strain rate. Fatigue life testing also verified the numerical simulations, indicating that the strain relief structure effectively dissipates strain from the interconnect junctions to the crests of the horseshoes. Both the simulation and experimental results show that this multi-layer strain relief structure for stretchable electronic systems is a durable and highly promising design with significant implications for the future of conformable electronics.

Fujitsu Semiconductor America today announced two new FRAM products featuring 1 Mbit and 2 Mbits of memory. The MB85RS1MT and MB85RS2MT, the largest-capacity, serial-interface FRAM products offered by Fujitsu, will be available in sample quantities at the end of March.

The MB85RS1MT and MB85RS2MT FRAMs offer features that are ideal for smart meters, industrial machinery and medical devices, including high endurance, higher writing speed, larger density and low power consumption. The new FRAMs can support 10 trillion writing cycles, an endurance roughly 10 times greater than previous ferroelectric memories from Fujitsu and superior to other nonvolatile memories by at least a million times. Memory devices using FRAM consume 92 percent less power during writing compared to identical-capacity EEPROMs, and feature a writing speed 920 times faster.

As a single-chip solution, the new FRAM products substantially reduce component costs, mounted area, and power consumption compared to other system memory solutions that use EEPROM or SRAM and a battery for data retention. The new FRAM devices, by eliminating the need for a battery and additional memory components, simplify the design process, save board space, and reduce maintenance costs.

FRAM is a high-speed random access memory that is non-volatile, allowing data to be retained when the power is switched off. Its speed and durability enable FRAM to safely store more data than alternative solutions in the event of a sudden power failure. The dependability of FRAM for data retention has made it the choice of global customers for factory automation equipment, measurement devices, banking terminals, and medical devices since its introduction by Fujitsu in 1999.

"The larger 1 Mbit and 2 Mbit densities of the MB85RS1MT and MB85RS2MT, combined with FRAM’s higher endurance, faster writing speed and lower power, make the new devices optimal for real-time, continuous data-logging applications," said Tong Swan Pang, senior marketing manager at Fujitsu Semiconductor America. "FRAM is also ideal for sensitive medical devices such as hearing aids, where its faster writing speed eliminates undesirable noise."

The MB85RS1MT (1 Mbit) and MB85RS2MT (2 Mbit) will also be available as bare die for use in tiny medical and consumer devices.