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Research and Markets has announced the addition of Jain PharmaBiotech’s new report Nanobiotechnology Applications, Markets and Companies to their offering.

Photo by cenews via Creative Commons

Nanotechnology is the creation and utilization of materials, devices, and systems through the control of matter on the nanometer-length scale. Nanobiotechnology, an integration of physical sciences, molecular engineering, biology, chemistry and biotechnology holds considerable promise of advances in pharmaceuticals and healthcare. The report starts with an introduction to various techniques and materials that are relevant to nanobiotechnology. It includes some of the physical forms of energy such as nanolasers. Some of the technologies are scaling down such as microfluidics to nanofluidic biochips and others are constructions from bottom up. Application in life sciences research, particularly at the cell level sets the stage for role of nanobiotechnology in healthcare in subsequent chapters.

Some of the earliest applications are in molecular diagnostics. Nanoparticles, particularly quantum dots, are playing important roles. In vitro diagnostics, does not have any of the safety concerns associated with the fate of nanoparticles introduced into the human body. Numerous nanodevices and nanosystems for sequencing single molecules of DNA are feasible. Various nanodiagnostics that have been reviewed will improve the sensitivity and extend the present limits of molecular diagnostics.

An increasing use of nanobiotechnology by the pharmaceutical and biotechnology industries is anticipated. Nanotechnology will be applied at all stages of drug development – from formulations for optimal delivery to diagnostic applications in clinical trials. Many of the assays based on nanobiotechnology will enable high-throughput screening. Some of nanostructures such as fullerenes are themselves drug candidates as they allow precise grafting of active chemical groups in three-dimensional orientations. The most important pharmaceutical applications are in drug delivery. Apart from offering a solution to solubility problems, nanobiotechnology provides and intracellular delivery possibilities. Skin penetration is improved in transdermal drug delivery. A particularly effective application is as nonviral gene therapy vectors. Nanotechnology has the potential to provide controlled release devices with autonomous operation guided by the needs.

Nanomedicine is now within the realm of reality starting with nanodiagnostics and drug delivery facilitated by nanobiotechnology. Miniature devices such as nanorobots could carry out integrated diagnosis and therapy by refined and minimally invasive procedures, nanosurgery, as an alternative to crude surgery. Applications of nanobiotechnology are described according to various therapeutic systems. Nanotechnology will markedly improve the implants and tissue engineering approaches as well. Other applications such as for management of biological warfare injuries and poisoning are included. Contribution of nanobiotechnology to nutrition and public health such as supply of purified water are also included.

There is some concern about the safety of nanoparticles introduced in the human body and released into the environment. Research is underway to address these issues. As yet there are no FDA directives to regulate nanobiotechnology but as products are ready to enter market, these are expected to be in place.

Future nanobiotechnology markets are calculated on the basis of the background markets in the areas of application and the share of this market by new technologies and state of development at any given year in the future. This is based on a comprehensive and thorough review of the current status of nanobiotechnology, research work in progress and anticipated progress. There is definite indication of large growth of the market, but it will be uneven and cannot be plotted as a steady growth curve. Marketing estimates are given according to areas of application, technologies and geographical distribution starting with 2012. The largest expansion is expected between the years 2017 and 2022.

ultra-low power processorAt this week’s International Solid State Circuits Conference (ISSCC 2013), imec and Holst Centre presented an ultra-low power processor that operates reliably at near-threshold voltages. The processor delivers clock speeds up to 1MHz at voltages down to 0.4 V. In tests based on a Fast Fourier Transform use case, it consumed only 79 µW – a fraction of the power consumption at standard voltages.

“Energy-efficient data processing will be vital for a wide range of emerging applications from Body Area Networks to building automation and equipment monitoring. Reducing active power consumption and standby leakage are thus increasingly important considerations for digital design,” said Harmke de Groot, Program Director at Holst Centre/imec. “Yet much of the industry’s research is still aimed at improving performance rather than increasing battery lifetime by higher energy efficiency.  At Holst Centre, we focus on low power and low voltage to enable battery-powered and energy scavenging smart devices.”

The new energy-efficient processor platform is customized for biomedical applications such as ECG and EEG monitoring. This was realized by creating an interface architecture around a general-purpose processor core to enable ultra-low voltage operation and automatic scaling of performance to improve energy efficiency, plus in-situ monitoring to guarantee reliability and high yield.

One of the key developments was the ability to reduce the operating voltage while delivering enough performance to meet application needs, and maintaining that performance over a range of operating voltages and temperatures. That was achieved by forward biasing the transistors within the processor, allowing it to operate at voltages just above the threshold for the CMOS process used.  The operating voltage can be adjusted between the processor’s nominal voltage of 1.1 V and a minimum voltage of 0.4 V depending on the current performance requirements.

Natural variations in manufacturing processes can lead to voltage fluctuations when a processor is being used. At near-threshold voltages, these fluctuations can be enough to stop the processer working. To avoid this and ensure reliability, the team connected “canary flip-flops” to the most timing-critical parts of the processor. These are designed to fail before the processor’s circuits do and can be monitored – allowing the operating voltage to be scaled up before noise affects the processor. In addition, automatic bias control eliminates the usual voltage drop across the power switches that control the processor, further enhancing energy efficiency and reliability under near-threshold conditions.

To reduce energy consumption even further, the interface can control the state of individual components on the chip separately, for example turning off the processor core or reducing the voltage in the memory when these components are not required. The software interface can also dynamically switch the processor between various performance modes, optimizing the number of active functional units in the core to suit the algorithm being performed. Unused functional units are switched off to reduce power consumption.

ultra-low power multi-standard 2.3/2.4GHz short range radioImec and Holst Centre presented at ISSCC an ultra-low power multi-standard 2.3/2.4GHz short range radio. The 1.9nJ/b radio is compliant with three wireless standards: Bluetooth Low Energy, ZigBee and Medical Body Area Networks. A proprietary 2Mbps mode is also implemented to support data-streaming applications like hearing aids. The radio is three to five times more power-efficient than current Bluetooth Low Energy solutions.

“From health care to smart buildings, adding sensors to our environment will support and enhance our day-to-day life.  Applications are numerous and restricted mainly by our imagination… and by the power consumption of the mostly battery-operated sensor devices,” said Harmke De Groot, program director of Ultra Low Power Circuits at Holst Centre/imec.  “The radio often consumes between 50-85% of the overall power consumption of a sensor system. And for autonomous devices, with only a small battery and thus limited battery energy, the power consumption of commercially available short-range radios is rather high (>15mW DC power).”

Imec and Holst Centre developed an ultra-low power multi-standard radio with sensitivity. The radio significantly reduces the power consumption of the overall sensor system compared to off-the-shelf radios. As a result, the autonomy of the device is increased, or more functionality can be added to the sensor device, increasing its quality, functionality and/or performance. Or, the battery size can be reduced, resulting in a smaller device, which in case of wearable systems, adds to the comfort of the user.

The 2.4GHz radio is implemented in 90nm CMOS technology. Using a highly energy efficient architecture and optimizing the most power hungry building blocks, resulted in a 2.4GHz radio with world-class energy efficiency while supporting the most common standards for mobile sensor networks. Imec and Holst Centre’s energy-efficient radio architecture has a suitable LO frequency plan and several efficiency-enhancement techniques for the critical RF circuits. As a result, the radio achieves a DC power of only 3.8mW at 1.2V supply for the receiver and 4.6mW for the transmitter. This is 3 to 5 times more power-efficient than the current state-of-the-art Bluetooth Low Energy solutions. The measured RX noise figure is 6dB, resulting in an excellent sensitivity in each standard (-100/-98/-96.5dBm for Zigbee/BLE/MBAN). With a measured IIP3 of -19dBm at the maximum front-end gain, the RX can accommodate the BLE intermodulation test level to -40dBm (spec. >-50dBm).

These results were presented at the 2013 IEEE International Solid-State Circuits Conference (ISSCC) in San Francisco.

ion gunThe Hiden IG20 high-brightness gas ion gun is further enhanced by the introduction of a new beam optic and ion source configuration to enable both increased beam brightness and beam contrast, together with a significant reduction in ultimate spot size.

With a raster scanning area of 4x4mm, the IG20 is equally suited to depth profiling and to surface imaging applications and is the preferred gas ion gun for secondary ion and secondary neutral mass spectrometry, for Auger and for XPS. Parameter selection and gun operation are fully under PC control, and the gun is operable with both oxygen and with inert gas primary sources.

Two interchangeable ion sources are available for operation with the same beam optic configuration. One is optimized for general analysis with maximum brightness and a beam current of 800nA; one is optimized for high dynamic range depth profiling applications with minimised beam scatter and supporting a beam current of 200nA within a beam diameter of just 80 micron.

The IG20 ion gun is differentially pumped and includes full raster scanning, incorporation of a neutrals dump, DN-35-CF (2.75 inch diameter) Conflat-type mounting flange and simple replacement of the ion source yttria-coated iridium twin-filament. Companion products include the IG-5C metal ion gun with caesium source and a choice of quadrupole SIMS detectors.

Tim Turner, the Reliability Center Business Development Manager at the College of Nanoscale Science and Engineering (CNSE), Albany, NY, blogs about the potential of resistive memory and the reliability challenges the must be overcome.

Resistive Memory, RRAM or Memristors is a hot topic right now.  RRAM has the potential for single digit nano parameters (speed as fast as 1 ns, area per bit as small as 5 square nm) and is non-volatile.

The technology is based on the formation of a small conductive filament inside an insulator.  The filament is formed the first time using a high voltage.  After that, set or reset transformation (conductive to non-conductive or visa versa) is accomplished by moving one or a few atoms an atomic scale distance.  This can be done with a low voltage (less than a volt).    This small movement gives a repeatable set or reset that can withstand many cycles.

Conduction in the filament appears to be due to oxygen vacancies existing in a percolation path through the insulator.  A small electric field in the reverse direction causes the migration of these oxygen vacancies in a mechanism similar to electromigration of Al or Cu atoms in a metal line.  Momentum exchange between electrons and the vacancies appears to be the driving force.  The vacancies do not have to move far to open the small filament.  An oxygen vacancy moves an atomic scale distance and the tiny filament opens, allowing an insulator to exist between points in the filament.  Forcing a forward voltage can move the oxygen vacancy back into the area where the filament is conductive.  This small movement can give a 100X change in the conduction through the dielectric.  This is the state change that can be interpreted as the digital signal stored on the memory cell.

The material set used for RRAM is CMOS compatible.  RRAM cells have been made out of Cu/HfOx [1], Al/AlOx/Pt, TiN/AlOx/Pt or even Al/AlOx/CNT (Carbon Nano Tubes)[2].  Most of the work reported to date has been on arrays where the cell is similar to a DRAM, using one transistor and one capacitor [3].  The RRAM cell starts with a capacitor, then forms the filament in the capacitor dielectric.  The advantage  this technology has is the smaller size of the capacitor.  There is no need for deep trenches in the silicon or for thick vertical stacks.   The technology is also non-volatile, so there is no need to refresh the charge every few milliseconds.

In polycrystalline materials, the filaments appear to form along grain boundaries between crystals [7].  For amorphous material there are no grain boundaries, but the material is reported to be able to withstand more cycles before failure [1].

RRAM might also be produced with a simple single resistor cross-point array (no transistor per cell required).  Figure 1 shows an array where the each cell is addressed by a row and a column.  The conduction in the row/column pair determines if the cell is set or reset (conductive or insulating).  This arrangement has the distinct advantage of allowing the memory array to be printed on top of a logic circuit.  Active circuits are required only for the address circuitry, allowing a large memory array to be added with little additional silicon area. 

Figure 1: Cross-point RRAM cell

That is the good news.  Now for the bad news.  What are the technology challenges that prevent you from enjoying this technology today?

The first issue is one of measurement noise.  With atomic spacing causing the difference between a set and a reset state, there is some uncertainty in the answer.  Sometimes, a bit will not program.  Nimal Ramaswamy of Micron [3] reported that random bits in a large array failed any given write operation.  There was an average number of failures for each write of a large array, but different bits failed each time.  Every bit apparently has the same probability of failure. 

Random Telegraph Noise (RTN) is another issue.  The state of the bit will most likely be read by forcing voltage and measuring current.  RTN is caused by trap states in the gate dielectric of a transistor that might address the bit.  These traps randomly fill or emit, changing the conduction of the channel.  The noise generated by this increases as the transistors are scaled.  Originally, this was thought to be just the larger impact of a single trap on a smaller area gate [4], but Realov and Shepard [5] showed that shorter L transistors show a greater noise than longer transistors with the same total area (below 40nm).  Thus, this is a problem that will increase as the technology is scaled.  There is also a chance that RTN will be generated by the movement of oxygen vacancies in the filament itself.

Degraeve et. Al. [6] reported a highly voltage sensitive disturb in the reset state.  Their RRAM cell could withstand 100 thousand disturb pulses (100ns) at -0.5 volts, but at -0.6 volts the cell could only withstand a little over 100 pulses.  They also showed that the sensitivity to disturb could be reduced significantly by balancing and optimizing the set and reset pulses.

Figure 2: Disturb in Reset State

Optimization of the Set and reset pulses also has a strong impact on the set/reset cycling endurance of the cell.  Degraeve was able to show up to 10 G set/reset pulses after optimization. 

Wu et. Al [2] showed the impact of scaling on a cross-point array.  According to their model, scaling the technology from 22nm to 5 nm resulted in an increase for the parasitic word and bit line resistance from under 10 ohms to almost 100,000 ohms as the lines width and thickness are reduced.  Adding to the significance of this is the variation in resistance between the closest cell in the array and the furthest call in the array.  This variation could be over 4 orders of magnitude while the difference between the set and reset resistance is only 2 orders of magnitude.  This issue could restrict the size of sub arrays, compromising the potential area savings using this technology.

As the metal lines are scaled to obtain higher memory densities, the filament that generates the conduction in the cell does not scale.  That means the set and reset pulse currents remain about the same as the array is scaled.  This results in an electromigration issue in the scaled metal lines.

Figure 3: Oxygen Vacancy Filament Determines Set or Reset State of RRAM Memory Cell

RRAM is certainly an appealing technology with its ability to scale the cell to tiny dimensions, good speed, CMOS compatible material set and the possibility of mounting the technology above a logic array.  Unfortunately, the devil is in the details and the list of advantages is balanced by a list of problems that must be overcome before this technology can carve out a space as a memory solution.

References:
1] Jihan Capulong, Benjamin Briggs, Seann Bishop, Michael Hovish, Richard Matyi, Nathaniel Cady, College of Nanoscale Science and Engineering, “Effect of Crystallinity on Endurance and Switching Behavior of HfOx based Resistive Memory Devices”, Proceedings of the International Integrated Reliability Workshop 2012
2] Yi Wu, Jiale Liang, Shimeng Yu, Ximeng Guan and H. S. Philip Wong, Stanford University, “Resistive Switching Random Access Memory – Materials, Device, Interconnects and Scaling Considerations”, Proceedings of the International Integrated Reliability Workshop, 2012
3] Nirmal Ramaswamy, Micron, “Challenges in Engineering RRAM Technology for High Density Applications”, Proceedings of the International Integrated Reliability Workshop, 2012
4] K.K. Hong, P.K Ko, Chemming Hu and Yiu Cheng,  Random Telegraph Noise of Deep Sub-Micrometer MOSFETs, 1990 IEEE 1741-3106/90/0200-0090 http://www.eecs.berkeley.edu/~hu/PUBLICATIONS/Hu_papers/Hu_JNL/HuC_JNL_167.pdf
5] Simeon Realov and Kenneth L. Shepard, “Random telegraph noise in 45nm CMOS: Analysis Using an on-Chip Test and Measurement System,  IEDM10-624, 978-1-4244-7419-6/10/$26.00 ©2010 IEEE, http://bioee.ee.columbia.edu/downloads/2010/S28P02.PDF
6] R. Degraeve, A. Fantini, S. Clima, B. Guvoreanu, L. Goux, Y. Y. Chen, D. J. Wouters, Ph. Rousset, G. S. Kar, G. Pourtois, S. Cosemans, J. A. kittl, G. Groeseneken, M. Jurczak, l. Altimime, IMEC, “Reliability of Low Current Filamentary HfO2 RRAM Discussed in the Framework of the Hourglass set/reset Model”, Proceedings of the Integrated Reliability Workshop, 2012.
7] Gennadi Bersuker, SEMATECH, “Origin of Conductive Filaments and Resistive Switching in HfO2 based RRAMS” Proceedings of the International Integrated Reliablity Workshop, 2012, 1.2-1

BioMEM for cardiac resynchronization therapyImec demonstrated a low-power (20µW), intra-cardiac signal processing chip for the detection of ventricular fibrillation at this week’s International Solid State Circuits Conference (ISSCC 2013) in San Francisco with Olympus. An important step toward next-generation cardiac resynchronization therapy solutions, the new chip delivers innovative signal processing functionalities and consumes only 20µW when all channels are active, enabling the miniaturization of implantable devices.

Robust and accurate heart rate (HR) monitoring of the right and left ventricles and right atrium is essential for implantable devices for cardiac resynchronization therapy. And accurate motion sensor and thoracic impedance measurements to analyze intra-thoracic fluid are critical for improving clinical research and analysis of the intra-cardiac rhythm. Moreover, extreme low-power consumption is required to further reduce the size of cardiac implants and improve the patient’s quality of life.

Imec’s low-power integrated circuit features three power-efficient, intra-cardiac signal readout channels (or in short: ECG channels). Each of the three ECG channels is equipped with a precision ECG signal readout circuit with very low-power consumption and an analog signal processor to extract the features of the ECG signal for detection of ventricular fibrillation. The feature extractor achieves only 2ms latency to facilitate responsive cardiac resynchronization therapy.

Additionally, the chip includes unique features that improve the functionality of cardiac resynchronization therapy devices. First, the low-power accelerometer readout channel enables rate adaptive pacing. Secondly, to handle intra-thoracic fluid analysis, the chip includes a 16-level digital sinusoidal current generator and provides 82db wide dynamic range bio-impedance measurement, in the range of 0.1Ω－4.4kΩ with 35mΩ resolution, and achieves best-in-class accuracy (>97%).

Click here to view slideshow of more highlights from ISSCC 2013.

Imec, in collaboration with Panasonic Corporation, has presented at the IEEE International Solid-State Circuits Conference (ISSCC 2013) a 60GHz radio transceiver chipset with low power consumption that delivers high data rates over short distances. Imec drastically boosted the link budget of the system by introducing beamforming into the radio architecture. This multi-Gbit 60GHz chipset paves the way toward small size, low-power, low-cost, high-data rate solutions for battery-operated consumer devices, such as smart phones and tablets.

“Exchange of gigabytes of data between mobile devices requires a viable 60GHz technology that balances cost, size and power consumption,” said Liesbet Van der Perre, program director of green radios at imec. “Imec’s prototype transceiver chipset enables multi-gigabit wireless connectivity for ‘true mobile’ devices thanks to its very low power consumption. More demanding applications such as high-definition video streaming and gaming with low latency, proximity computing and wireless docking can also be built on our technology.” 

The prototype chipset consists of a receiver and a transmitter chip, and these are based on a direct conversion architecture combined with an on-chip phased-array architecture. This makes it suited for implementation in 40nm low-power digital CMOS technology targeting low-cost, mass market production. The receiver and transmitter chips are implemented for 4 antenna paths, but they are easily extendible to more antenna paths thanks to the beamforming at analog baseband, rather than at RF. The chip size is kept low through the use of lumped components even at 60GHz, and very compact mm-wave CMOS layout techniques. The transmitter chip consumes 584mW and the receiver chip 400mW at 1.1V power supply. The chipset is integrated with a 4 antenna array in a compact module and demonstrated in a wireless link. With QPSK modulation, a data rate of 2.31Gbps is obtained, and with QAM16 modulation, a data rate of 4.62Gbps is achieved. No bit errors were found when transmitting packets of 32,768 symbols over a distance of 3.6m with QPSK modulation and 0.7m with QAM16 modulation. Thanks to the beamforming a 3dB scan angle range around 120º is achieved with 11dBi antenna gain.

The imec receiver and transmitter chips are designed for the IEEE802.11ad  standard. The receiver and transmitter chipset has been tested with a IEEE 802.11ad PHY/MAC baseband chip developed by Panasonic, demonstrating the complete system for IEEE 802.11 applications. The beamforming functionality is also verified in these system tests.

AMOLED screens unveiled at CESAlthough active-matrix organic light-emitting-diode (AMOLED) televisions headlined last month’s Consumer Electronics Show (CES), shipments of these high-end panels will remain limited in the coming years, according to the Displaybank at information and analytics provider IHS (NYSE: IHS).

Shipments of AMOLED TV panels are expected to climb to 1.7 million units in 2015, up from 1,600 in 2013. While the jump in shipments is large, the total number of AMOLED panels by that time remains negligible compared to the vast number of liquid crystal display (LCD) panels being shipped.

Worldwide Forecast of AMOLED TV Panel Shipment (Millions of Units)

CES featured AMOLED TVs from leading manufacturers such as Samsung Electronics, LG Electronics, Panasonic and Sony, generating major excitement at the event, according to Displaybank.

“But despite ongoing efforts among these companies to achieve mass production and lower cost via various technology options, it is unlikely that most of the AMOLED TV prototypes announced at CES will be available in the market this year. The limited availability and high pricing of AMOLED TVs will restrict their shipments during the next few years.”

The only AMOLED TV likely to ship this year will be LG’s 55-inch flat Full HD model, the 55EM9700.

AMOLED bonanza at CES

Staking competing claims to be the first and largest in the world, 56-inch 4K AMOLED TV prototypes were each shown by Panasonic and Sony at the Las Vegas event. The sets boasted four times—hence, 4K—the resolution of current 1080p televisions. For the 4K OLED samples, both manufacturers used oxide thin-film-transistor (TFT) backplanes, which present lower manufacturing costs than low-temperature polysilicon (LTPS) backplanes.

Panasonic used the printing method on its 4K AMOLED TV, a simpler printing technology, making OLED production adaptable for a wider range of display sizes. In contrast, Sony used evaporation technology to deposit organic material in its top-emitting White OLED structure with a color filter. The panel was provided by AUO of Taiwan, which at the show also introduced its own 32-inch oxide TFT backplane with White OLED structure TV. Sony’s emission technology optimizes the OLED structure, which helps achieve better light management, enhances color purity and achieves higher contrast at lower power consumption levels.

Using different technological approaches, Sony and Panasonic were both able to make ultra-high-definition (UHD) 56-inch displays that reached 79 pixels per inch—twice the density of 55-inch full high-definition (FHD) displays used in the OLED TVs from LG and Samsung. For their part, Samsung and LG showed off 55-inch 3-D, FHD sets with AMOLED technology, coinciding with news that LG’s FHD TV will be available on the market by the first quarter this year. LG’s AMOLED TV utilized oxide TFT backplanes and the White OLED evaporation method, as it did in a prototype presented last year, eliminating the need for fine metal mask technology in OLED production.

White OLED provides an easier way to mass-produce OLED panels

Samsung, in contrast, used the LTPS TFT backplane and the RGB OLED evaporation method in its AMOLED TV prototype, similar likewise to what it did last year. Mainly applied in small- and medium-sized displays, sets with LTPS TFT backplanes and RGB OLED evaporation exhibit improved OLED performance, it is generally agreed. But with low yields and high costs, Samsung may find it difficult to launch AMOLED TVs in 2013 using these technologies.

Both Samsung and LG also unveiled their own curved 55-inch AMOLED TV prototypes at CES, with the sets boasting a 4-meter radius of curvature and Full HD resolution. Meanwhile, the success of Samsung and LG in implementing a large-sized curved OLED was thought to be a meaningful achievement in the display industry. However, both still face challenges with mass production, and market availability of curved OLED TVs is not a near-term possibility.

Yield improvement and cost reduction remain barriers

Also at CES, LG announced that its 55-inch Full-HD AMOLED TV will be available in the international market within a couple of months at a price of $12,000. LG has already started receiving preorders in its native South Korea, and the company claims it will start mass-producing the world’s first 55-inch OLED TV soon. While OLED TV makers all hope to become the acknowledged industry and technology leaders in their space, more improvements in technology, material and manufacturing appear to be needed in order to bring AMOLED TVs to the market.

In addition to technical and large-volume manufacturing challenges, OLED TVs also already face an uphill task of competing on prices with lower-priced, higher-resolution 4K LCD and even Full-HD LCD TVs. By the time AMOLED TV production achieves efficiencies in large-scale production, LCD TVs would have had an opportunity to become even more competitive in price and performance.

With still many challenges to be addressed despite many prototypes at CES, consumers are likely to wait a few more years before they buy their AMOLED TVs, Displaybank believes.

Leti to coordinate European supply chain in silicon photonicsCEA-Leti today announced that it will coordinate a four-year project aimed at building a European-based supply chain in silicon photonics and speeding industrialization of the technology.

The PLAT4M (Photonic Libraries And Technology for Manufacturing) project will focus on bringing the existing silicon photonics research platform to a level that enables seamless transition to industry, suitable for different application fields and levels of production volume.

PLAT4M, which is funded by a European Commission grant of 10.2 million euros, includes 15 leading European research and development institutes and CMOS companies, key industrial and research organizations in design and packaging, as well as end users in different application fields to build the complete supply chain.

“Silicon with its mature integration platform has brought electronic circuits to mass-market applications – our vision is that silicon photonics will follow this evolution,” said Laurent Fulbert, Integrated Photonics Program Manager at CEA-Leti, coordinator of PLAT4M. “Upgrading existing platforms to become compatible with industrialization is now essential and this requires streamlining and stabilizing the design and process flows by taking into account design robustness, process variability and integration constraints. The PLAT4M partners bring a combination of expertise to the challenge of building a complete supply chain for commercializing silicon photonics in Europe.”

A surge in output of silicon photonics research in recent years has significantly boosted the potential for commercial exploitation of the technology. However, most of this R&D has been devoted to developing elementary building blocks, rather than fabricating complete photonic integrated circuits, which are needed to support large potential markets.

 The PLAT4M consortium will make technologies and tools mature by building a coherent design flow, demonstrating manufacturability of elementary devices and process integration and developing a packaging toolkit. The project will validate the complete supply chain through application-driven test vehicles representing various application fields, such as telecom and datacom, gas sensing and light detection and ranging (LiDAR) and vibrometry. It also will focus on preparing the next-generation platform by setting up a roadmap for performance evolution and assessing scalability to high-volume production.

The supply chain will be based on technology platforms of Leti, imec and STMicroelectronics, supported by a unified design environment.

 The multiple benefits of PLAT4M for the European photonic industry will include:

  • Preparing the supply chain for silicon photonics technology, from chip-level technology to packaged circuits
  • Making integration technologies accessible to a broad circle of users in a fabless model
  • Contributing to the development of a design environment that facilitates photonics/electronics convergence
  • Moving the emphasis from the component to the architecture, and thus concentrate efforts on new products or new functionalities rather than the technology level
  • Aggregating competencies in photonics/electronics design and fabrication, and
  • Retaining the key added value in components in Europe through optoelectronic integration, with little added value in offshore assembly

PLAT4M Consortium Members

The consortium consists of technology providers, research institutes, end users and SMEs with excellent track records in advanced photonics technologies. At the design and process level, CEA and imec have been the most prominent European players in silicon photonics for a decade. Together with University of Paris-Sud, III-V Lab and TNO, they have demonstrated numerous scientific and technological breakthroughs.

For building a complete design flow, Mentor Graphics, PhoeniX BV and Si2 are world leaders in EDA tools and will work together to develop a common reference platform.

STMicroelectronics (France and Italy) brings its experience in microelectronics, and it has been engaged for the past year in the development of silicon photonics at the industrial level. Tyndall-UCC and Aifotec are renowned experts in the field of optoelectronic packaging and will work together on the implementation of packaging technologies developed within PLAT4M in a manufacturing environment.

End-users like Polytec, Thales Research & Technology and NXP will drive the demonstrators development and assess the use of silicon photonics in their applications fields.

SEMATECH today announced that Poongsan, a producer of annealing furnaces, has joined its Front End Processes (FEP) program, and will work with SEMATECH to explore high-pressure anneal (HPA) techniques for silicon and non-silicon channel materials to improve device performance and reliability for next-generation technologies.

Today, the solid-state device community is investigating non-silicon, high-mobility materials to increase carrier mobility within the device channels and improve overall transistor performance. High-mobility channels such as germanium and III-V compounds have the potential to operate at high speeds with low operating power and may be used in mainstream semiconductor CMOS technologies in the future. However, numerous manufacturing challenges associated with high-mobility channels such as processes, tools, device test structures and environment, safety, and health issues need to be addressed before these materials-based solutions are brought to manufacturing.

Since 2006, Poongsan and SEMATECH have partnered in tool and process development projects that have successfully demonstrated the technical merits of a high pressure annealing furnace. 

“Working with SEMATECH, we have demonstrated that high-pressure anneals are both effective and manufacturing-worthy approaches to high-k/Si interface defect passivation. From this work, we have gone on to develop and ship production-worthy annealing furnace tools to world-wide customers,” said Dr. Bob Wu, director of sales and marketing of Poongsan. “We look forward to continuing our strategic partnership with SEMATECH as we work toward developing emerging technologies and improving products.”

As a member of SEMATECH’s FEP program, located at the College of Nanoscale Science and Engineering (CNSE) of the University at Albany, Poongsan will collaborate with SEMATECH’s engineers and leverage SEMATECH’s activities in advanced test structures, advanced materials and device electrical characterization to improve processing technologies to increase mobility and reduce interfacial defects. Specifically, SEMATECH and Poongsan will collaborate on passivation of silicon and non-silicon gate stacks and other interfaces.

“To achieve better device performance and help shape the next generations of nanoelectronics, it’s necessary to partner to share know-how in materials, processing, equipment development and device technologies,” said Paul Kirsch, SEMATECH’s director of Front End Processes. “Poongsan’s proven expertise in high-pressure annealing processes will complement our own device and process expertise. We will work together on the technical and manufacturing gaps to address the continued scaling needs of today’s aggressive chip manufacturing market.”

The goal of SEMATECH’s FEP program is to provide novel leading-edge materials, processes, structural modules and electrical and physical characterization methods to support the continued scaling of logic and memory applications.