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Yole Développement announced its Emerging Non-Volatile Memories report. Yole Développement’s report provides an analysis of the emerging nonvolatile memories (NVM) five applications fields that will fuel market growth and a description and forecasts of the four emerging NVM (MRAM, PCM, RRAM, FeRAM) technologies. It also analyzes the competitive landscape for both standard memories (DRAM and NAND) and emerging NVM with expected dynamic for the future.

Higher-density NVM chips will spawn many new applications and increase the business ten-fold in just five years

This Yole Développement report describes why and how emerging NVM (FRAM, MRAM/STTMRAM, PCM, RRAM) will be increasingly used in various markets: industrial and transportation, enterprise storage, smart card, mobiles phones and mass storage.

Until recently, only FRAM, PCM and MRAM were industrially produced and available in low-density chips to only a few players. Thus the market was quite limited and considerably smaller than the volatile DRAM and non-volatile Flash NAND dominant memory markets (which enjoyed combined revenues of $50B +in 2012).

However, in the next five years the scalability and chip density of those memories will be greatly improved and will spark many new applications, with the following NVM market drivers explained in detail in this report:

  • With the adoption of STT MRAM and PCM Cache memory, enterprise storage will be the largest NVM market. NVM will greatly improve the input/output performance of enterprise storage systems whose requirements will intensify with the growing need for web-based data supported by cloud servers.
  • Mobile phones will increase its adoption of PCM as a substitute to flash NOR memory in MCP packages thanks to 1GB chips made available by Micron in 2012. Higher-density chips, expected in 2015, will allow access to smart phone applications that are quickly replacing entry-level phones. STTMRAM is expected to replace SRAM in SoC applications thanks to lower power consumption and better scalability.
  • Smart card MCU (microcontrollers) will likely adopt MRAM/STTMRAM and PCM as a substitute to embedded flash. Indeed, flash memory cell-size reduction is limited for the future. NVM could reduce the cell size by 50% and thus be more cost-competitive. Additional features like increased security, lower power consumption and higher endurance are also appealing NVM attributes.
  • Mass storage markets served by flash NAND could begin using 3D RRAM in 2017-2018, when 3D NAND will slow down its scalability as predicted by all of the main memory players. When this happens, a massive RRAM ramp-up will commence in the next decade that will replace NAND, if sufficient 3D RRAM cost-competiveness and chip density are available. Overall, the global emerging non-volatile memory market will grow from $209M in 2012 to $2B in 2018, equating to an impressive growth of + 46 %/year. Nevertheless, this is a forecast based on a conservative scenario, and the report also provides a best-case scenario for an even broader adoption of NVM.

MRAM/STTMRAM and PCM will lead the NVM market, reaching a combined $1.6B by 2018

Market adoption of memory is strongly dependent on its scalability. This Yole Développement report provides a precise memory roadmap in terms of technological nodes, cell size and chip density for each NVM (FRAM, MRAM/STTMRAM, PCM, RRAM). A market forecast is provided for each technology by application, units, revenues and also # of wafers. A comprehensive review of the latest technical developments of every main player is presented in order to understand the technology’s status and the main technical challenges.

“By 2018, MRAM/STTMRAM and PCM will surely be the top two NVM on the market. Combined, they will represent a $1.6B business by 2018, and their sales will almost double each year, with double-density chips launched every two years,” explains Yann de Charentenay, Senior Technology and Market Analyst at Yole Développement.

FeRAM will grow at a steadier growth rate (+10%/ year) and will focus on industrial & transportation applications because of the low-density available. RRAM revenues won’t really surge until 2018, with the availability of high-density chips of several 10’s of Gb that could replace NAND technology.

Giant memory manufacturers and start-up companies compete on technology development

The memory supply chain has been highly concentrated in the last 10 years, supporting a huge price/Gb decrease (-20 to 40 %/year for NAND and DRAM). Five players (Samsung, Micron, SK Hynix, Toshiba and SanDisk) hold 90 % of DRAM and NAND sales. These leading players will have a key role in the competitive landscape of emerging NVM. This report identifies and positions the key emerging NVM players based on the technology developed, market presence (new entrant or established memory player), and targeted markets. The supply chain dynamic is analyzed in order to understand who today’s key market players are in each application and technology, and to illustrate how the competitive landscape will evolve.

Intersil restructuring to cut 18% of workforceIntersil Corporation (NASDAQ: ISIL) today announced restructuring initiatives designed to prioritize the company’s sales and development efforts, strengthen financial performance and improve cash flow.

The restructuring plan includes a reduction of approximately 18% of Intersil’s worldwide workforce and a reduction of approximately $30 million in annual operating expenses, according to the SEC filing. Currently, Intersil employs approximately 1,700 employees, according to their company website. The estimated 18% reduction would involve around 300 jobs. Intersil has not released a statement about where the workforce reduction would come from within the company.

The restructuring plans will be substantially completed during the first quarter of 2013 and are expected to reduce annual operating expenses by approximately $30 million. A restructuring charge of approximately $15 million for severance-related benefits is expected during the first quarter of 2013.

"Today’s market requires us to sharpen our focus on core strengths and markets where we can offer superior value to our customers," said Jim Diller, Interim President and Chief Executive Officer, of the restructuring initiatives. "Today, we are announcing plans designed to ensure that Intersil remains well-positioned and appropriately structured for sustainable, long-term growth and profitability."

This is not the first time that Intersil, which specializes in the design and manufacture of high-performance analog, mixed-signal and power management semiconductors, has had to cut workforce in an effort to improve cash flow, though it is a more substantial reduction than their most recent restructuring efforts. Intersil reduced their workforce by 9% in 2008, in response to the economic conditions of the day, and then again in May 2012, with a workforce reduction of 11%.

Intersil has locations in California, Florida, China, Malaysia, Japan, Germany and the United Kingdom.

Infineon Technologies AG (FSE: IFX / OTCQX: IFNNY) has achieved a breakthrough in the manufacturing of power semiconductors on 300-millimeter thin wafers. In February, the company received the first customer go-aheads for products of the CoolMOS family produced by the 300-millimeter line at their site in Villach, Austria. The production process based on the new technology has completed qualification from start to finish and customers have given the go-ahead.

"Infineon put its faith in this manufacturing technology very early on and continued to invest even in economically difficult times. The qualification of our entire 300-millimeter line represents a veritable leap ahead of the competition," says Dr. Reinhard Ploss, CEO of Infineon Technologies AG. "300-millimeter thin-wafer manufacturing for power semiconductors will enable us, with the corresponding demand, to seize the opportunities that the market offers."

Infineon is the first and only company worldwide to produce power semiconductors on 300-millimeter thin wafers. Thanks to their larger diameter compared to standard 200-millimeter wafers, two-and-a-half times as many chips can be made from each one. Power semiconductors from Infineon feature low energy loss and compact design. Although not much thicker than a sheet of paper, the chips have electrically active structures on the front and back.

The next step is for the present manufacturing concept for CoolMOS products, qualified from start to finish, with the front-end site Villach and assembly of the thin chips at the back-end site Malacca, Malaysia, to be expanded to the front-end site Dresden. Here the focus is on high-volume production in a fully automated 300-millimeter line. The basis for the processes required and the manufacturing technology is currently being developed in research projects in Dresden. The technology transfer to Dresden is running on schedule and qualification of the first CoolMOS products will be completed in March. Shortly, in Villach more power semiconductor technologies will be transferred to the 300-millimeter line and produced. The development of the next power technology generation will focus on 300 instead of 200-millimeter technology.

"Our ability to innovate is the basis of our success – good ideas are turned into reality,” says Ploss. “In both Austria and in Saxony, we have the necessary conditions for this: technological know-how, well-educated and highly motivated specialists and exemplary support from government policy."

Last year, the independent research institute IMS Research (an IHS company) named Infineon as a market leader in power semiconductors. Infineon develops semiconductor and system solutions addressing three central challenges to modern society: energy efficiency, mobility, and security. In the 2012 fiscal year, ending September 30, the Company reported sales of Euro 3.9 billion with close to 26,700 employees worldwide.

Lithography scientists, engineers, and developers — long accustomed to working years ahead in order to meet industry needs — face keen challenges, with meeting user expectations, enabling new capabilities, and controlling costs at the top of the list. SPIE Advanced Lithography, the annual forum for discussions on meeting the challenges in developing state-of-the-art lithographic tools, resists, metrology, materials characterization, and design and process integration, will bring the community together in San Jose, California, to address those issues. The event will run February 24-28 at the San Jose Convention Center and San Jose Marriott Hotel.

Symposium chair Harry Levinson of GLOBALFOUNDRIES said organizers anticipate interest in several topics in particular, including:

  • Designing with multi-patterning and directed self-assembly (DSA): beyond SEMs toward real chips
  • Line edge roughness: clearly a concern of many and the focus of a session in the conference on Advanced Etch Technology for Nanopatterning.
  • Resist limits: secondary electrons, tradeoffs among resolution, line-edge roughness and exposure speed.

However, Levinson noted, “To be honest, the real buzz usually comes from something unexpected, which is probably one of the best reasons for attending Advanced Lithography!”

With the presence of leaders from companies such as Intel, Samsung, ASML, Taiwan Semiconductor Manufacturing Corp., and other companies that have announced large investment strategies in new technology, “unexpected” topics might include R&D toward photonics integrated circuits versus silicon photonics, retooling for 450mm wafers, or power-source issues in EUV (extreme ultraviolet) tools.

In addition to featured speakers and more than 560 technical talks, the event will include panel discussions on disruptive and emerging technologies, full- and half-day short courses on lithography topics, interactive poster paper receptions, and a 60-company exhibition showcasing many of the industry’s top semiconductor suppliers, integrators, and manufacturers. The exhibition will run Tuesday and Wednesday, February 27 and 28.

Plenary presentations from leaders in the lithography industry include:

  • Bill Siegle, Independent Consultant and ASML Advisory Board Member: “Contact printing to EUV: lessons learned from the art of lithography”
  • Howard Ko, Senior VP and General Manager, Synopsys Silicon Engineering Group: “The evolution of EDA alongside rapid silicon technology innovation”
  • Charles Szmanda, The Patent Practice of Szmanda & Shelnut, LLC: “The new U.S. patent law: what you need to know and how it will affect your strategy.”
  • Technical talks are organized into seven conferences:
  • Alternative Lithographic Technologies
  • Extreme Ultraviolet Lithography
  • Metrology, Inspection, and Process Control for Microlithography
  • Advances in Resist Materials and Processing Technology
  • Optical Microlithography
  • Design for Manufacturability through Design-Process Integration
  • Advanced Etch Technology for Nanopatterning

Accepted papers will be published in the SPIE Digital Library as soon as approved after the meeting, and in print volumes and digital collections.

In its new report MEMS Front-End Manufacturing Trends, Yole Développement goes further in the equipment and materials market forecasts and in the manufacturing trends for MEMS. The report gives detailed analyses about MEMS device technology process flow, manufacturing trends and manufacturing cost breakdown.

Changes in MEMS manufacturing will drive the equipment & materials market from $378M to $512M for equipment and $136M to $248M for materials between 2012-2018

Innovative processes are fueling the MEMS equipment and materials market. Yole Développement forecasts that demand for MEMS-related equipment will grow from an estimated $378M in 2012 to greater than $510M by 2018, at a CAGR of 5.2% over the next five years. Yole Développement’s  MEMS market forecast will follow a cyclical up/downturn similar to what the mainstream IC equipment market underwent.

The demand for materials and related MEMS consumables will grow from an estimated $136M in 2012 to greater than $248M by 2018 at a CAGR of 10.5% over the next five years. 

As MEMS become commodity products, manufacturing will change and mature

Today, MEMS fabrication is still very diversified and lacking in standardization; Yole Développement’s rule, One product, one process, still applies. Indeed, MEMS has a different story than IC and doesn’t follow the same roadmap as the semiconductor industry. Thus, it’s still common to see many players with radically different manufacturing approaches for the same MEMS device, sometimes within the same company (i.e. both the CMOS MEMS and hybrid approaches can be used for inertial devices or microphones).

However, as MEMS becomes a commodity product with a quicker time-to-market compared to previous generations, anything that speeds up the commercialization process is welcome. MEMS packaging is evolving in a different direction than front-end processing, and Yole Développement has already identified that packaging standardization will become increasingly critical in order to support the massive volume growth in unit shipments, and decrease overall costs associated with MEMS and sensor content. For example, microphone packaging is very similar between one manufacturer and another. Additionally, this report shows that at the front-end level, companies are developing in-house technological platforms targeted for different MEMS devices.

In this report, Yole Développement shows that as MEMS moves from competing on process technology to competing on functions and systems, a move towards more standard solutions is necessary to drive down package size and cost.

Currently, MEMS foundries still compete at the process level and have to propose a wide range of processes in order to cope with new MEMS designs and structures. This approach differs from fabless companies, which usually focus on one type of MEMS design. Their main objective is to find the most experienced and reliable foundry partner in order to convince customers of their expertise. IDMs, meanwhile, generally rely on robust and established MEMS processes to manufacture their products. Foundries, which must always remain at the forefront of changes in the MEMS manufacturing landscape, have the biggest challenge.

TSV & unique wafer stacking solutions are key enablers for reducing die size and cost

This report highlights the major front-end manufacturing changes. For example, TSV for CSP is gradually seeping into the MEMS industry.

However, since miniaturization will be limited, new detection principles are currently being developed at various R&D Institutes (i.e. Tronic’s M&NEMS concept) in order to lower MEMS size at the silicon level. This technology is based on piezoresistive nanowires rather than pure capacitive detection, and is poised to be a leap forward in terms of device performance and chip size. This will set the stage for a new generation of combo sensors for motion sensing applications, achieving both significant surface reduction and performance improvement for multi-DOF sensors.

Amongst the large array of MEMS technologies, Yole Développement identified several that will have the widest diffusion in the years to come.

The list includes:

• Through Si Vias

• Room Temperature Bonding

• Thin Films PZT

• Temporary Bonding

• Cavity SOI

• CMOS MEMS

Other MEMS technologies, i.e. gold bonding, could be widely used to reduce die size while maintaining great hermeticity for wafer level packaging.

Experts present advances in lithography at SPIE 2013SEMATECH experts will present research and development results on extreme ultraviolet (EUV) manufacturability and extendibility, alternative lithography, and related areas of metrology at the SPIE Advanced Lithography 2013 conferences taking place February 25-28 at the San Jose Convention Center and Marriott in San Jose, CA.

“We are enthusiastic about sharing our progress on some of the most critical aspects of the development of EUV infrastructure,” said Stefan Wurm, director of lithography at SEMATECH. “SEMATECH lithographers will recount achievements in multiple areas of EUV to further enable EUVL pilot line readiness and advance EUV extendibility.”

SEMATECH engineers will report progress on EUV mask infrastructure, manufacturability, extendibility and metrology, and will showcase some of their findings in over 30 papers and posters demonstrating breakthrough results in exposure tool capability, resist advances, defect-related inspection, e-beam and nanoimprint. 

More importantly, the results presented will be instrumental in driving timely creation of the remaining infrastructure required to bring EUV to production. In one area of investigation, technologists from SEMATECH’s Mask Blank Development Center will report progress with its multilayer deposition process, including recent defect printability results from an NXE3100 tool with comparison of the imaging to various simulation modeling approaches.

Other SEMATECH papers will showcase advances in metrology techniques, photoresist shrinkage, nanopolishing, scatterometry, through-silicon via (TSV) reveal, transmission electron microscopy (TEM) tomography, critical dimension atomic force microscopy (CD-AFM), critical dimension X-ray scattering (CD-SAXS)—a potential metrology technique for FinFET and 3D memory structures—and a through-focus scanning optical microscopy (TSOM) technique being explored for future defect inspection or to enable high-volume manufacturing of high-aspect ratio features.

Additionally, technologists will present a “big picture” CD metrology gaps analysis, which interrelates the combined results from years of SEMATECH CD metrology studies to summarize the outlook for various tool technologies for different applications.

“We will be showcasing impressive metrology advances achieved through collaborative research, as well as revealing new defect characterization results for EUV mask blanks that form the basis of the technology for SEMATECH’s new Nanodefect Center,” said Michael Lercel, senior director of nanodefectivity and metrology at SEMATECH.

Among the global semiconductor community’s leading gatherings, the SPIE conference series attracts thousands of specialists in various aspects of lithography and related metrology, two of the most challenging areas of advanced microchip production.

Gigaphoton, Inc., a major lithography light source manufacturer, announced today that the company has achieved EUV light output equivalent to maximum of 20W for its laser-produced plasma, or LPP light sources for EUV lithography scanners. This result was obtained by irradiating the Sn target with a solid-state pre-pulse laser and a CO2 laser at 100kHz. An average EUV output of 10W was confirmed during operation. Considering that the current commercially accepted EUV output levels are around 10W, the results demonstrated by Gigaphoton represents that a critical milestone has been reached for pre-production level output.

Gigaphoton has focused on developing high output, stable, and economical LPP light sources since 2002. Since that time, Gigaphoton has introduced several unique technologies including the development of on-demand tin droplets generator with droplets measuring less than 20μm, the combining of short wavelength solid-state pre-pulse lasers and CO2 lasers as a main pulse and the utilization of magnetic field for debris mitigation.

The unique LPP light source technology introduced by Gigaphoton extends the lifetime of droplet generators by utilizing ultra-small tin droplets on-demand, reducing downtime and cost. In addition, high EUV output conversion efficiency has been achieved through the optimized combination of short wavelength solid-state pre-pulse laser and CO2 laser as the main pulse. This technology contributes to the real possibility of achieving efficient, high output EUV light sources. In order to maximize the life of the collector mirror, a superconducting magnet is used to generate a powerful magnetic field that guides the unwanted debris resulting from the thermal expansion of the tin droplets towards the tin catcher. This results in further reduction of cost and downtime.

"The fact that our unique LPP light source technology is now able to achieve the level of EUV output matching that of today’s pre-production performance, proves that our vision for high output, low running cost, stable LPP light sources are indeed achievable," said Hitoshi Tomaru, President and CEO of Gigaphoton. "Our efforts will help to bring the industry closer to realizing mass production level EUV lithography scanners. We are making firm progress towards our entry into the EUV light source business – focusing on technology development to accommodate the future industry needs."

The latest details of Gigaphoton’s LPP light source technology will be presented at the SPIE Advanced Lithography 2013, being held in San Jose, California from February 24 through the 28.  Gigaphoton has developed and delivered DUV laser light sources used by major semiconductor chipmakers in the Pan-Asian, US and European regions since its founding in 2000.

Gas chromatograph by ShimadzuShimadzu Corporation today introduced the Tracera, a high-sensitivity gas chromatograph. Tracera is equipped with the newly developed barrier discharge ionization detector (BID), which is capable of detecting all types of trace organic and inorganic compounds, with the exception of helium (He) and neon (Ne), at the 0.1 ppm level (i.e. sub-ppm, where ppm refers to parts per million). Tracera GC is applicable for many types of high-sensitivity analyses typically performed with GC systems incorporating multiple detectors.

Background to Development

Gas chromatographs are used for research and development and quality control in a number of fields, involving petrochemistry, fine chemicals, the environment, pharmaceuticals, foods, electronics/semiconductors, and fragrances. In recent years, demands for higher sensitivity and trace quantity analyses have increased.

Thermal conductivity detectors (TCD) and flame ionization detectors (FID) are general-purpose detectors used in conventional gas chromatographs. A TCD detects a variety of inorganic and organic compounds, excluding the carrier gas component, but the sensitivity is insufficient. An FID is capable of detecting trace components at the ppm level, but can only detect organic compounds (excluding formaldehyde and formic acid). Analysis has thus required complex systems incorporating a variety of detectors to suit the target component.

With this issue in mind, Shimadzu has investigated the basics of plasma detection technology as a means for increasing sensitivity stability and the detectable concentration range. This has resulted in the barrier discharge ionization detector (BID), a new detector capable of the high-sensitivity detection of both organic and inorganic compounds, while providing excellent durability.

"The Tracera is a ground-breaking new system that combines this new type of detector, offering features not provided by conventional detectors, with the Shimadzu GC-2010 Plus high-performance capillary gas chromatograph," Said Masahito Ueda, general manager of GC & TA Business Unit, Analytical & Measuring Instruments Division. "It is expected to improve the efficiency of high-sensitivity, trace-quantity analyses, and to reduce equipment and analysis costs."

Main Features of This System

High Sensitivity—Achieves detection sensitivity over 100 times that of TCD, and over twice that of FID

The built-in barrier discharge ionization detector (BID) generates helium plasma. The extremely high photon energy of this plasma ionizes the sample components, enabling high-sensitivity detection. This system achieves at least 100 times the sensitivity of a conventional TCD, and at least twice the sensitivity of FID, enabling the detection of all types of trace components at the 0.1 ppm level.

Universal Detector—Capable of detecting both organic and inorganic compounds with no difference in sensitivity

The new BID helium plasma has an extremely high energy. It can detect all organic and inorganic compounds, with the exception of He and Ne, with no difference in sensitivity. It improves analysis sensitivity even with aldehydes, alcohols, and halides, for which sensitivity decreases with FID. A single Tracera system can perform analyses that conventionally required complicated systems equipped with multiple detectors and units. Examples include the analysis of hydrogen and organic compounds such as formic acid, generated as part of the reaction process during artificial photosynthesis, and the analysis of low concentration hydrocarbons and permanent gases generated in lithium ion rechargeable batteries.

Long-Term Stability—Adopts electrode-preserving plasma generation technology

With the new BID, the plasma is generated inside a quartz tube, so it makes no contact with the discharge electrode used for plasma generation. As a result, the detector electrode is not degraded, achieving long-term analytical stability.

Research and Markets has announced the addition of the "Global 3D IC Market 2012-2016" report to their offering.

TechNavio’s analysts forecast the global 3D IC market to grow at a CAGR of 19.7 percent over the period 2012-2016. One of the key factors contributing to this market growth is the huge demand for memory-enhanced applications. The global 3D IC market has also been witnessing the increase of multi-chip packaging. However, the thermal conductivity issues could pose a challenge to the growth of this market.

The key vendors dominating this market space are Advanced Semiconductor Engineering Co. (ASE), Samsung Electronics Co. Ltd., STMicroelectronics N.V., and Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC). Other vendors mentioned in the report include Elpida Memory Inc., IBM Corp., Intel Corp., and Micron Technology Inc.

“One of the emerging trends in the global 3D integrated circuit (IC) market is multi-chip packaging. In this type of packaging more transistors can be packed into a single 3D IC,” an analyst from TechNavio’s Hardware team said, commenting on the report.  “This type of packaging is very important for memory-enhanced applications because this approach enables improved interaction between the memory and the processor. It is expected that multi-chip packaging will be a promising approach for most applications in the future. Thus, vendors consider that multi-chip packaging is one of the crucial trends that will lead to the growth of the Global 3D IC market.’

According to the report, one of the major growth drivers is the increasing demand for 3D ICs in memory products (flash memory and DRAM). 3D ICs are able to improve the performance and reliability of memory products and can also help reduce their cost and size.

TechNavio’s report, the Global 3D IC Market 2012-2016, was prepared based on an in-depth market analysis with inputs from industry experts. The report covers the Americas, and the EMEA and APAC regions; it also covers the global 3D IC market landscape and its growth prospects in the coming years. The report also includes a discussion of the key vendors operating in this market. The study was conducted using an objective combination of primary and secondary information including inputs from key participants in the industry. The report contains a comprehensive market and vendor landscape in addition to a SWOT analysis of the key vendors.

The relentless march of process technology brings more integration and performance. IBM’s System z processor leads the charge at ISSCC 2013 clocking in at 5.7GHz and with 2.75B transistors.

The chip complexity chart below shows the trend in transistor integration on a single chip over the past two decades. While the 1 billion transistor integration mark was achieved some years ago, we now commonly see processors with beyond 2B transistors on a die.

Leveraging sophisticated strategies to lower leakage and manage voltage, variability and aging, has bolstered the continuing reduction in total power dissipation. This is helping rein in the increase in energy demands from PCs, servers, and similar systems. As power reduction becomes mandatory in every application, the trend towards maintaining near-constant clock frequencies also continues as shown below in frequency trends plot. This will yield solutions with less cost and cooling demands, resulting in greener products in the future.

Processors are choosing to trade off performance by lowering supply voltage. The performance loss of reduced voltage and clock frequency is compensated by further increased parallelism. Processors with more than eight cores are now commonplace. This year at ISSCC 2013, a 24-core processor from Fudan University will be presented as noted in the core count trend chart below.

In addition to the trend to integrate more cores on a single chip, multiple die within a single package are appearing. In ISSCC 2013, IBM will present a multi-chip module with six CPUs and two embedded DRAM cache chips. As well, dedicated co-processing units for graphics and communications are now commonly integrated on these complex systems-on-chip. Design of these SoCs requires broad collaboration across multiple disciplines including circuits, architecture, graphics, process technology, package, system design, energy efficiency and software. New performance and power-efficient computing techniques continue to be introduced at targeted, critical applications such as floating point and SIMD.

As technology continues to scale to finer dimensions, large caches are being integrated into microprocessor die.

Methods to communicate within-die as well as cross-die are becoming increasingly important. This is being driven by two trends: (1) 3D integration continues to grow in interest and (2) intra-die communications become more challenging with process scaling due increases in delay per unit interconnect length. Work on bringing package-level inter-chip transport onto the die has been gaining in popularity and we see this trend continuing.

This and other related topics will be discussed at length at ISSCC 2013, the foremost global forum for new developments in the integrated-circuit industry. ISSCC, the International Solid-State Circuits Conference, will be held on February 17-21, 2013, at the San Francisco Marriott Marquis Hotel.