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January 17, 2013 – Printed, flexible, and organic electronics have garnered more than $7.5 billion in venture funding from 1996-2011, but funding has declined sharply from a peak in 2007, according to a report from Lux Research. Funding topped $990M in 2007, but lost a third of that value within four years to $626M in 2011.

"A number of high-profile failures like Konarka have soured many investors’ impressions of this space — cutting away some unwarranted hype, but potentially raising the hurdles for companies with more promising technologies to secure funds," stated Anthony Vicari, Lux Research associate and lead author of a new report examining investments and opportunities in printed, flexible, and organic electronics. He points to "glaring funding imbalances, with overfunding in areas such as organic photovoltaics, but promising technologies such as electrowetting and electrochromic displays haven’t received investment that matches their potential."

Lux will present a Webinar on Feb. 5 to discuss the report’s findings, but here’s some insights in a nutshell:

– Display technologies have huge potential. Electrowetting, electrochromic, and metal oxide thin-film transistors (MOTFTs) are potential gold mines, offering high technical performance and value relative to competing reflective displays and TFTs.

– Asian startups are underfunded. North America leads overall investment at $5.1B, or 67% of the world total. However, Asian start-ups, like OLED developers in South Korea, account for just $506M of investing. That indicates not a lack of innovation, but the need for an alternate funding model, Lux says.

– Dow, Samsung, and Intel are trendsetters. These three giants lead corporate venture capital (CVC) investors, with high levels of activity in this space. Their best bets have targeted the more promising, higher-potential technologies such as OLEDs and RFID.

Semiconductor Research Corporation (SRC) and the Defense Advanced Research Projects Agency (DARPA) announced that $194 million will be dedicated during the next five years to six new university microelectronics research centers to support the continued growth and leadership of the U.S. semiconductor industry.

The new Semiconductor Technology Advanced Research network (STARnet) includes:

  • the Center for Future Architectures Research (C-FAR) at the University of Michigan;
  • the Center for Spintronic Materials, Interfaces and Novel Architectures (C-SPIN) at the University of Minnesota;
  • the Center for Function Accelerated nanoMaterial Engineering (FAME) at the University of California, Los Angeles;
  • the Center for Low Energy Systems Technology (LEAST) at the University of Notre Dame;
  • the Center for Systems on Nanoscale Information fabriCs (SONIC) at the University of Illinois at Urbana-Champaign; and
  • the TerraSwarm Research Center at the University of California, Berkeley.

“STARnet is a collaborative network of stellar university research centers whose goal is to enable the continued pace of growth of the microelectronics industry, unconstrained by the daunting list of fundamental physical limits that threaten,” said Gilroy Vandentop, the new SRC program executive director.

STARnet is funded by the DARPA as part of the Department of Defense and U.S. semiconductor and supplier industries as a public-private partnership. Annually, $40 million is dedicated to the program, with each center receiving about $6 million.

SRC administers the STARnet program. Industry partners include Applied Materials, GLOBALFOUNDRIES, IBM, Intel Corporation, Micron Technology, Raytheon, Texas Instruments and United Technologies.

By bringing together industry participants and DARPA, SRC has a successful track record of not only helping provide state-of-the-art military applications, but also laying the foundation for advancing the microelectronics industry. Beyond military applications and workforce benefits, SRC technologies arising from this university research make significant contributions to the $144 billion U.S. semiconductor industry.

The STARnet program supports 145 research professors and about 400 graduate students at 39 universities overall (including those from the six research centers). The program is also helping develop the next-generation of Ph.D. graduates in electrical engineering, computer science, and the physical sciences.

The specific missions of the STARnet university research centers include:

  • C-FAR at University of Michigan: Research future scalable computer systems architectures that maximally leverage emerging circuit fabrics to enable whole new commercial/defense application areas through a highly collaborative research agenda. Participating universities include: Columbia, Duke, Georgia Tech, Harvard, MIT, Northeastern, Stanford, UC Berkeley, UCLA, UC San Diego, Illinois, Washington and Virginia.
  • C-SPIN at University of Minnesota: Bring together multi-disciplinary researchers in the area of spintronic materials, devices, circuits and architectures to explore and create the fundamental building blocks that allow revolutionary spin-based multi-functional, scalable memory devices and computational architectures to be realized. Participating universities include: UC Riverside, Cornell, Purdue, Carnegie Mellon, Alabama, Iowa, Johns Hopkins, MIT, Penn State, UC Santa Barbara, Michigan, Nebraska and Wisconsin.
  • FAME at UCLA: Create and investigate new nonconventional atomic scale engineered materials and structures of multi-function oxides, metals and semiconductors to accelerate innovations in analog, logic and memory devices for revolutionary impact on the semiconductor and defense industries. Participating universities include: Columbia, Cornell, UC Berkeley, MIT, UC Santa Barbara, Stanford, UC Irvine, Purdue, Rice, UC Riverside, North Carolina State, Caltech, Penn, West Virginia and Yale.
  • LEAST at Notre Dame: Explore the physics of new materials and devices that can lead to disruptive advances in integrated circuits and systems, and focus on discovering the best material systems for ultralow voltage and steep transistors. Participating universities include: Carnegie Mellon, Georgia Tech, Penn State, Purdue, UC Berkeley, UC San Diego, UC Santa Barbara, UT Austin and UT Dallas.
  • SONIC at the University of Illinois at Urbana-Champaign: Enable equivalent scaling in beyond-CMOS nanoscale fabrics by embracing their statistical attributes within statistical-inference-based applications, architectures and circuits to achieve unprecedented levels of robustness and energy efficiency. Participating universities include: UC Berkeley, Stanford, UC Santa Barbara, UC San Diego, Michigan, Princeton and Carnegie Mellon.
  • TerraSwarm at UC Berkeley: Enable the simple, reliable and secure deployment of a multiplicity of advanced distributed sense-control-actuate applications on shared, massively distributed, heterogeneous and mostly uncoordinated swarm platforms through an open and universal systems architecture. Participating universities include: Michigan, Washington, UT Dallas, Illinois at Urbana-Champaign, Penn, Caltech, Carnegie Mellon and UC San Diego.

For more information on STARnet, visit http://www.src.org/program/starnet/.

 

January 15, 2013 – The semiconductor industry is undergoing massive transformation as the rise in mobile computing, changes to the fabless-foundry model, uncertainties in technical innovation, and global macroeconomic trends become the dominant forces in 2013 and beyond, according to industry leaders speaking at the SEMI Industry Strategy Symposium (ISS), opening this week in Half Moon Bay, CA.

Ajit Manocha, CEO of GlobalFoundries, during his keynote presentation discussed the dynamic technology and economic needs of mobile computing that is driving new approaches to the chip design-to-production cycle. Calling it "Foundry 2.0," he sees outsourced semiconductor manufacturing moving toward a more IDM-like model, creating new collaboration models and techniques to close the gap between process teams at foundries and design teams at the fabless companies. With daunting technical challenges like 3D stacking, 450mm fabs, new transistor architectures, multi-patterning, and the uncertainties to lithography-based scaling, product development paths with virtual teams will evolve and adapt rapidly in the coming months and years.

With new fabs now costing upwards of $8 billion and leading-edge manufacturing investments expected to exceed $40 billion this year alone, global economic trends and forces — increasingly influenced by uncertain consumer spending in both developed and emerging markets — have never been more important to the semiconductor ecosystem. Dr. John Williams, president and CEO of the Federal Reserve Bank of San Francisco, said "Many businesses are locked into a paralyzing state of anxiety."

Williams used the ISS conference to lessen uncertainty and anxiety in the capital markets, pledging to keep interest rates near zero until the unemployment rate drops to 6.5%, as long as inflation expectations do not climb above 2.5%.

Bruce Kasman, chief economist and managing director of global research at JP Morgan, shared a positive economic outlook, especially in the second half of the year, that is "bumpy, better and less risky." He sees Asia leading the economic rebound, as China demand accelerates with the change in leadership and improved access to credit. University of Texas Austin Churchill scholar, Matthew Gertken, however, discussed the simmering "Asian cold war" developing as territorial disputes with China generate an emerging "containment policy" by many of China’s neighbors.

How these macroeconomic dynamics are impacting the semiconductor industry was discussed by speakers who saw both perils and opportunities. Andy Oberst, senior VP, strategy and corporate development at Qualcomm, looked at what mobile phones would likely look like in 2020, but also pointed out how disruptive changes — not incremental changes — have always driven the mobile phone market.

Satya Kumar, vice president at Credit Suisse, discussed how original equipment makers like phone and computer manufacturers have always benefitted from the declining cost of transistors and pondered, "Could stopping Moore’s Law be a good thing?"

As the world’s largest semiconductor company, Intel’s view is different. Michael Bell, vice president and general manager, mobile and communications group at Intel, brought the audience up to date on the company’s mobile strategy, offering confidence that Intel’s portfolio of RF baseband technologies, leading-edge scaling performance, and supply chain excellence will ultimately deliver significant success.

Conference speakers on Day 2 and Day 3 of ISS will discuss how these and other mega-trends are specifically impact the R&D, product development, manufacturing, investment, and supply-chain challenges impacting various sectors of IC and microelectronics industry.

The SEMI Industry Strategy Symposium (ISS) examines global economic, technology, market, business and geo-political developments influencing the semiconductor processing industry along with their implications for your strategic business decisions. For more than 35 years, ISS has been the bellwether semiconductor conference for senior executives to acquire the latest trend data, technology highlights and industry perspective to support business decisions, customer strategies and the pursuit of greater profitability.

January 11, 2012 – The annual Consumer Electronics Show in Las Vegas has become a mecca for all things electronic and digital, from useful to cool to just plain bizarre. Among the technologies at the confluence of cool and useful were two things that aim to rethink the PC model. (And for the cool/bizarre side of the CES spectrum, behold eatART’s rideable robot Mondo Spider.)

This year’s CES emphasized "designs that defied or pushed the limits of convention," with two clear examples, points out DisplaySearch’s Richard Shim: size-defying "phablets," and even more size-defying "table PCs."

The phablet — a combination of phone and tablet — got its start with Samsung’s Galaxy Note, which offered an expanded 5-in. OLED screen; the Galaxy Note II was even bigger at 5.5-in. At this year’s CES, the phablet took another screen-size step up thanks to China’s Huawei, which unveiled its Ascend Mate ,which has a 6.1-in. 1280 × 720 screen. (Huawei also touted its Ascend D2 with a 5-in., 1920 × 1080 display.) The Ascend D2 will be available in China later this month, followed by the Ascend Mate in February.

The "table PC," meanwhile, is essentially a supersized tablet, with the screensize of a large computer monitor. Sony’s Vaio Tap 20 (20-in. display) is now joined by Lenovo’s IdeaCentre Horizon with a 27-in. resistive touch-based display, and the company has a prototype 39-in. version planned for later this summer. Each of these "table PCs" can stand upright like an all-in-one desktop PC, but also laid down flat, Shim notes.

"Both the phablet and the table PC categories represent the extreme end of a form factor trend that we expect to see throughout 2013," Shim explains. "The traditional lines that have been used to define, categorize, and track devices are expected to only become more difficult to maintain," and suppliers will increasingly tinker with formfactors to find what resonates with consumers. (In his own CES research note, Barclays analyst CJ Muse acknowledged the interest shown in phablets, and likely reverberations they should cause among suppliers, along with "large screen touch, Next Gen TVs, and the Internet of everything.") Shim doesn’t expect these design tinkerings will greatly impact shipment trends in the near-term (DisplaySearch still sees notebook PC shipments dipping 5% Y/Y in 2013), but "we anticipate that brands can score image points and credibility with consumers for willing to be bold with design. That has translated to good fortune for Apple so it should not be underestimated."

(photos via DisplaySearch; credit photo #1 to Lori Grunin/CNet)

January 11, 2012 – GlobalFoundries says it plans to build a $2 billion R&D facility at its Fab 8 campus in Saratoga County, NY. The new Technology Development Center (TDC) will span more than 500,000 sq. ft of "flexible space" for various technology development and manufacturing activities, including cleanroom and lab space. Construction is planned to begin in early 2013 and completed in late 2014.

The TDC will focus on a variety of semiconductor development and manufacturing work "to support the transition to new technology nodes," and development of "innovative capabilities to deliver value to customers beyond the traditional approach of shrinking transistors," according to the company. Broadly speaking, the TEC is planned to be a collaborative space to develop "end-to-end solutions covering the full spectrum of silicon technology," from EUV lithography photomasks to new interconnect and packaging technologies enabling 3D chip stacking, "and everything in between."

"As the industry shifts from the PC era to a market focused on mobile devices, we have seen increasingly strong interest from customers in migrating to advanced nodes on an accelerated schedule," stated GlobalFoundries CEO Ajit Manocha. "To help facilitate this migration, we are making significant investments in strengthening our technology leadership, including growing our workforce and adding new capabilities to make Fab 8 the hub of our global technology operations." Toward that end, "the new TDC will help us bridge between the lab and the fab by taking research conducted with partners and further developing the technologies to make them ready for volume manufacturing," he added

Other regional New York State leaders chimed in with appreciation and optimism for the project’s synergy with the local and regional economy. "New York has become the world’s hub for advanced semiconductor research and now, the Technology Development Center will further help ensure the innovations developed in New York, in collaboration with our research institutions, are manufactured in New York," said Governor Andrew M. Cuomo. "New York State’s public investments to develop CNSE as a hub of innovation coupled with the private investments of GLOBALFOUNDRIES are prime examples of best practices for public-private partnerships linking research, innovation and production that have made New York a globally recognized center of innovation," added Charles W. Wessner, director of the National Academies’ Innovation Program.

GlobalFoundries began developing its Fab 8 project in the summer of mid-2009; today its campus includes approximately 2 million sq. ft of development. The company has continued to make investments in manufacturing production as well as technology development, including work underway on 20nm and 14nm technology nodes.

January 10, 2012 – Reaffirming its earlier assertions about the health of fabless & foundry chipmakers vs. the rest of the industry, IC Insights says fabless IC suppliers saw sales rise 6% in 2012, compared with a -4% decline by IDMs (those with their own IC fabs), and the overall market’s -2% decline for the year.

Since 1999, the firm tracks, fabless company IC sales have outpaced IDMs (or the decline has been less severe) in every year except 2010. That year was an outlier largely because of strength in DRAM and NAND flash memory, areas in which fabless companies don’t have a presence, the firm points out.

Fabless vs. IDM company sales, 1999-2012. (Source: IC Insights)

Since 1999, fabless IC sales started out as roughly 7% of IDM sales, but have steadily risen and now make up about 27% of total IC sales. And fabless IC market CAGR from 1999-2012 was 16% vs. the overall industry’s 5% CAGR. More comparison metrics: fabless IC sales are at levels 7× what they were in 1999, vs. 50% for IDM IC sales, and IDM IC sales are now only 10% higher than 2000 and actually lower than they were in 2007.

By 2017, fabless IC companies will command a full third of the total IC market, IC Insights predicts, and this could be easily attained especially if larger companies (e.g. IDT, LSI Logic, Agere, and AMD) become entirely fabless. "Over the long-term, IC Insights believes that fabless IC suppliers, and the IC foundries that serve them, will continue to become a stronger force in the total IC industry," the firm notes.

These statistics are part of IC Insights’ annual McClean Report analysis of the entire IC industry, from technologies to applications. The firm is holding half-day seminars this month to release and discuss the findings. Contact the firm for more information about the report and the seminars.

by Todd Traylor, Vice President of Global Trading for Smith & Associates.

Consumer devices and cutting-edge tech make Consumer Electronics Show (CES) exciting; this year’s show stealers are the components that power it all. If you have any doubt look to center stage and Qualcomm’s opening keynote.

To those embedded (pun intended) in the semiconductor and electronics industry, Qualcomm is not a surprise keynote presenter. But CES is about the consumer, and their keynote highlighted what’s really at the core of consumer electronics’ (CE) success: powerful components. Components, after all, enable the innovative feature capabilities, mobility, power efficiency, and the integration of hardware and software, all which make CE devices "smart."   

Get smarter

The innovation behind the expanding class of smart devices (from phones to cars and all that is between) is the component breakthroughs from manufacturers – the processors, microelectromechanical sensors (MEMS) and sensor hubs, and the chips that are the brains, communication, and power of the devices.

Qualcomm unveiled their Snapdragon 800 and 600 series, processors designed for a range of mobile devices. The 800 series, manufactured using 28nm architecture, enables the integration of the new Krait 400, quad-core CPU with each core running at 2.3GHz, the new Adreno 330 GPU, 4G LTE, and 802.11ac WiFi, all with reduced power consumption, due in part to the smaller and more integrated chipset; the Snapdragon 600 series has similar architecture but slower speeds. The user experiences fast processing power for the next generation of smart devices, but at the level of traditional PCs, with the added benefits of always-on, always-connected plus the enhanced graphics and fast data communication speeds.

Nvidia’s latest Tegra 4 and Samsung’s Exynos 5 are among the direct competitors to the Snapdragon series . Nvidia’s Tegra 4 boasts 72 GPU cores in addition to the powerful quad-core Cortex A15 CPU, code-named "Wayne," for processing plus an additional low-power Cortex A15 running background tasks. The Tegra 4 CPU combination improves power use, essential in today’s devices, while integrating the CPU and GPU to improve performance and signal processing, important for graphics in digital cameras.

Tough competition improves CE field

At CES we see the envelope pushed to  be the  fastest, lightest, smallest, most efficient, best integrated, or first-mover. Intel scooped CES with the announcement of the new, quad-core, 22nm, Atom processor, Bay Trail, due this year to compete with ARM processors in mobile. Beyond speed, Bay Trail is only 8mm thick and enables all-day battery-life, essential to both mobile and Ultrabooks. AMD is showcasing its new Temash chip, based on the Jaguar CPU core, designed for tablets to support long battery life, HD graphics, powerful processing for full-applications for business productivity, as opposed to the reduced capabilities found mostly today. AMD’s Kabini chips are also on display, designed for the new line of low-powered laptops with A8 and A10 quad-core chips. These advances will support Ultrabook adoption in 2013 as prices decreases and features increase.

Expanded connectivity is also CES theme this year, such as Broadcom’s "Connected Life," enhancing consumer experiences in the home, car, and across wired and wireless devices. Pushing connectivity moves CE toward a unified experience as users move through environments. It also paves the growth path for NFC opportunities, content sharing, and allows for the latest in seamless "whole-home connectivity" through Broadcom’s  4th-generation, Gigabit DOCSIS system-on-chip (SoC) series, and dedicated SoC solutions for the fastest TV, internet, and mobile connected solutions.

Another set of breakthroughs comes from Atmel XSense™ flexible touch sensor, winner of CES’ Innovations Award in the Embedded Technologies. Flexible touchscreens are certain to be a desired feature in next-gen mobile devices, and Atmel’s expertise in sensor hubs and innovative material designs will ensure success.

Opportunities for everyone

One final note, it is not just the high-end CE devices that are targeted at CES. There is more attention this year to low-cost solutions designed for the emerging markets, which are set for double-digit growth for these devices, provided low-price points are met.

Author biography:

Todd Traylor began his career with Smith in 1997 in OEM sales, and was promoted to Trading Manager in 1999. In 2001, he transferred to The Netherlands to serve as General Manager of Smith’s Amsterdam office, and was promoted to Managing Director of Europe for Smith in 2002. Todd was named CPU Commodity Manager upon returning to Houston in 2003, and in 2012 was promoted to Vice President of Global Trading. Todd is a 1991 graduate of Texas A&M University, where he earned his bachelor’s degree in Business Management.

By David DiPaola, DiPaola Consulting, LLC.

New product development is an extremely rewarding area of engineering and business. It often brings innovation to unmet needs that can improve quality of life and be extremely profitable for entrepreneurs and large corporations alike. With MEMS technology exploding with new business opportunities, this blog will discuss the critical factors needed for success in the early stage of new product development.

New product development starts with an idea. A product to enable the blind to see is very appealing to consider. However, without a viable business and technical plan to show the path to commercialization, the idea is not worth very much and it’s impossible to influence investors or managers to support it. Hence the first step is to identify an application and a lead customer that a business plan can be developed around. Equally important are a favorable competitive landscape, no or limited patents surrounding the area of interest, and a large impact to society.

Applications that are driven by legislation or regulations are excellent because they have a high likelihood of fruition with definitive timelines. Legislation in automotive resulted in the development of MEMS based occupant weight sensors that provided feedback in systems used to deploy air bags with different force levels or not at all to better protect passengers in the event of an accident.  Even better are applications that give consumers what they want. The Argus II Retinal Prosthesis System is a device that partially restores sight for specific blindness. This device provides electrical stimulation of the retina to elicit visual patterns of light that can be interpreted by the brain (see figure). Hence users can recognize doorways and windows and gain greater independence; a highly desired quality with significant impact. Over 1 million people in the US may benefit from this device and the lead customers are people with profound retinitis pigmentosa.

The Argus II will be the first device to hit the market and hence the competitive landscape is extremely favorable.  Second Sight also benefits from large barriers to enter this market due to the rigorous FDA approval process. However, competition is on their heels. Nano Retina is developing another device that is smaller, fits uniquely in the eye alone and promises to provide greater number of pixels enabling recognition of humans.  Second Sight is also developing the next generation device to be smaller, places the video camera in the eye and provides improved vision with greater number of electrodes.

Timing is another important aspect of new product development. There are limited windows in which a product can be developed and launched. When products are developed without an underlying customer demand, they rarely make it passed the R&D phase into commercialization.  Often, technologies are developed in universities 15 – 30 years before they become mainstream commercialized products. Conversely, if the product comes to market too late, OEMs have already picked development partners and are reluctant to change suppliers. The application space may also be saturated with competitors making it difficult to win market share. Depending on the industry, these windows vary in size considerably. A typical cycle in automotive can range from 2 – 5 years. Consumer electronics can be as little as 6 months and Class III biomedical applications can see cycles greater than 10 years. Hence it is important to fully understand market opportunities and have a detailed schedule to demonstrate the product can be launched within this defined window. Equally important, some core technology elements of the design must be developed to a functional point with limited areas needing major development or it will be challenging to meet the defined schedule.

For the occupant weight sensor, there was a limited time to engage with OEMs and show proof of concept before production suppliers were chosen after the legislation came into law. The sense element and conditioning electronics were proven in another automotive sensor and the packaging was a major development piece. The required compliance with government legislation dictated the schedule for aggressive product development, validation, launch and ramp cycle.

An often mismanaged portion of new product development is the team behind the innovation. A team with robust chemistry, passion and a single leader are key to success. Multiple team leaders and poor chemistry only leads to infighting and redundant efforts. It is also important to limit team size to a critical few to expedite decision making and keep focused on what’s important.   Larger teams tend to get distracted with items outside of the core focus and can miss critical details and deadlines causing product failure. Self assembled teams starting at the grass roots level more times than not have excellent chemistry. They begin with an idea generated by 1 – 2 people and an additional 1 – 3 trusted colleagues are brought in as support roles to help manage the work load that often occurs after hours. This natural selection process brings people with similar passions together and weeds out less motivated people as they do not want the added work load.

An extremely important attribute of successful teams is to keep a low profile and minimize negative influences from external sources. At a project’s beginning, it seems the vast majority of people are against it or have an opinion on why the project will not be successful. In reality, it is a fear of risk and the unknown. Hence those teams who understand this and maintain a high risk tolerance yet work to minimize it, have a definite advantage. Once early project successes are achieved, there will be plenty of time to tell others about the latest innovation. Having an advocate at the vice president level in this early stage is also extremely helpful because it can channel much needed funds to the project and keep middle managers without similar vision from halting activity.

Speaking the language of investors and business leaders is critical to get the financial backing to make the development happen and commercialization a reality. Hence the product’s business plan must show that target profits can be achieved with a reasonable payback time of investment dollars.  It is recommended that the plan include low, medium and high production volume estimations, product costs, product selling price and gross revenues. Operational costs, taxes, equipment depreciation, travel, engineering, marketing and overhead costs all need to be captured as accurately as possible. Concluding the analysis with return on investment, net present value and initial rate of return provide a good financial overview for the project. 

New product development is an exciting area with many opportunities in MEMS applications.  Identification of your lead customer and application, knowing the competitive and patent landscape, creating high impact products, being sensitive to timing, having small, focused teams, and developing a robust business plan can make a large difference in the success of product commercialization. Please stay tuned for future articles that explore additional aspects to achieve success in new product development.

Author Biography:

David DiPaola is Managing Director for DiPaola Consulting a company focused on engineering and management solutions for electromechanical systems, sensors and MEMS products.  A 16 year veteran of the field, he has brought many products from concept to production in high volume with outstanding quality.  His work in design and process development spans multiple industries including automotive, medical, industrial and consumer electronics.  Previously he has held engineering management and technical staff positions at Texas Instruments and Sensata Technologies, authored numerous technical papers and holds 5 patents. To learn more, please visit www.dceams.com.   

January 9, 2012 – SEMI’s HB-LED Standards Committee has approved its first standard, specifying sapphire wafers used in making high-brightness light-emitting diode (HB-LED) devices.

Sapphire wafers are used in producing HB-LED devices for multiple applications: LCD backlights, signage and solid-state lighting. Development of industry standards, in collaboration with the global LED manufacturing supply chain, will help eliminate costs and better enable equipment and process innovation.

Five categories of single-crystal, single-side polished c-axis sapphire wafers are covered by the new HB1 standard:

  • Flatted 100mm diameter, 650μm thick,

  • Flatted 150mm diameter, 1,000μm thick,

  • Flatted 150mm diameter, 1,300μm thick,

  • Notched 150mm diameter, 1,000μm thick, and

  • Notched 150mm diameter, 1,300μm thick

SEMI’s HB-LED Standards Committee was formed in late 2010, comprised of companies involved in HB-LED devices, sapphire wafers, MOCVD wafer processing, and equipment and materials suppliers. Among its various individual efforts:

— The HB-LED Wafer Task Force already is seeking refinements to the HB1 standard, including specs for patterned sapphire substrates, double-sided polished wafers, impurities and defects (wafer and bulk), laser marking and identification, and bow and warp measurements. This group also is beginning a second round of experiments with wafer marking to characterize mark survivability, width, and depth; a first round conducted this year "showed promising results" on 100mm and 150mm wafers with front and back-surface marks (i.e., data matrix and OCR) were subjected to various surface modifications (e.g., slicing, grinding, polishing, GaN Ep). For 2013, the group plans to explore core and wafer defect inspection on ultrasonic technology, and conduct surveys on patterned sapphire substrates and double-side polishing.

— The HB-LED Equipment Automation Task Force plans to reballot a SEMI Draft Document on cassettes for 150mm sapphire substrates, seeking revisions to allow interoperability with existing equipment, taking into account cassette pocket size and spacing. This also will help standardization of load ports and transport systems.

— Meanwhile, a Software Working Group continues to develop a spec for an automation communication interface between process, automation, and metrology equipment. Another new standard, submitted and approved last October at the SEMI NA Standards Fall 2012 meetings, builds on that automation spec to address materials management and job management.

SEMI also plans to begin experiments and test methods based on a survey deployed last summer about defect vs. inspection techniques, aiming to identify sapphire wafer defects and inspection techniques catering to HB-LED manufacturing.

The wafer, automation, and impurities/defects task forces will be meeting at the Strategies in Light conference Feb. 12-14 in Santa Clara, CA. The NA HB-LEB committee and task forces will meet at the NA Standards Spring 2013 meetings April 1-4 in San Jose.

By Rebecca Howland, Ph.D., and Tom Pierson, KLA-Tencor.

Is it time for high-brightness LED manufacturing to get serious about process control?  If so, what lessons can be learned from traditional, silicon-based integrated circuit manufacturing?

The answer to the first question can be approached in a straight-forward manner: by weighing the benefits of process control against the costs of the necessary equipment and labor.  Contributing to the benefits of process control would be better yield and reliability, shorter manufacturing cycle time, and faster time to market for new products. If together these translate into better profitability once the costs of process control are taken into account, then increased focus on process control makes sense.

Let’s consider defectivity in the LED substrate and epi layer as a starting point for discussion. Most advanced LED devices are built on sapphire (Al2O3) substrates. Onto the polished upper surface of the sapphire substrate an epitaxial (“epi”) layer of gallium nitride (GaN) is grown using metal-organic chemical vapor deposition (MOCVD).

Epitaxy is a technique that involves growing a thin crystalline film of one material on top of another crystalline material, such that the crystal lattices match—at least approximately. If the epitaxial film has a different lattice constant from that of the underlying material, the mismatch will result in stress in the thin film. GaN and sapphire have a huge lattice mismatch (13.8%), and as a result, the GaN “epi layer” is a highly stressed film. Epitaxial film stress can increase electron/hole mobility, which can lead to higher performance in the device. On the other hand, a film under stress tends to have a large number of defects.

Common defects found after deposition of the epi layer include micro-pits, micro-cracks, hexagonal bumps, crescents, circles, showerhead droplets and localized surface roughness. Pits often appear during the MOCVD process, correlated with the temperature gradients that result as the wafer bows from center to edge. Large pits can short the p-n junction, causing device failure. Submicron pits are even more insidious, allowing the device to pass electrical test initially but resulting in a reliability issue after device burn-in. Reliability issues, which tend to show up in the field, are more costly than yield issues, which are typically captured during in-house testing. Micro-cracks from film stress represent another type of defect that can lead to a costly field failure.

Typically, high-end LED manufacturers inspect the substrates post-epi, taking note of any defects greater than about 0.5mm in size. A virtual die grid is superimposed onto the wafer, and any virtual die containing significant defects will be blocked out. These die are not expected to yield if they contain pits, and are at high risk for reliability issues if they contain cracks. In many cases nearly all edge die are scrapped. Especially with high-end LEDs intended for automotive or solid-state lighting applications, defects cannot be tolerated: reliability for these devices must be very high.

Not all defects found at the post-epi inspection originate in the MOCVD process, however. Sometimes the fault lies with the sapphire substrate. If an LED manufacturer wants to improve yield or reliability, it’s important to know the source of the problem.

The sapphire substrate itself may contain a host of defect types, including crystalline pits that originate in the sapphire boule and are exposed during slicing and polishing; scratches created during the surface polish; residues from polishing slurries or cleaning processes; and particles, which may or may not be removable by cleaning. When these defects are present on the substrate, they may be decorated or augmented during GaN epitaxy, resulting in defects in the epi layer that ultimately affect device yield or reliability (see figure).

Patterned Sapphire Substrates (PSS), specialized substrates designed to increase light extraction and efficiency in high-brightness LED devices, feature a periodic array of bumps, patterned before epi using standard lithography and etch processes. While the PSS approach may reduce dislocation defects, missing bumps or bridges between bumps can translate into hexes and crescent defects after the GaN layer is deposited. These defects generally are yield-killers.

In order to increase yield and reliability, LED manufacturers need to carefully specify the maximum defectivity of the substrate by type and size—assuming the substrates can be manufactured to those specifications without making their selling price so high that it negates the benefit of increased yield. LED manufacturers may also benefit from routine incoming quality control (IQC) defect measurements to ensure substrates meet the specifications—by defect type and size.

Substrate defectivity should be particularly thoroughly scrutinized during substrate size transitions, such as the current transition from four-inch to six-inch LED substrates. Historically, even in the silicon world, larger substrates are plagued initially by increased crystalline defects, as substrate manufacturers work out the mechanical, thermal and other process challenges associated with the larger, heavier boule.

A further consideration for effective defect control during LED substrate and epi-layer manufacturing is defect classification. Merely knowing the number of defects is not as helpful for fixing the issue as knowing whether the defect is a pit or particle. (Scratches, cracks and residues are more easily identified by their spatial signature on the substrate.) Leading-edge defect inspection systems such as KLA-Tencor’s Candela products are designed to include multiple angles of incidence (normal, oblique) and multiple detection channels (specular, “topography,” phase) to help automatically bin the defects into types. For further information on the inspection systems themselves, please consult the second author.

Rebecca Howland, Ph.D., is a senior director in the corporate group, and Tom Pierson is a senior product marketing manager in the Candela division at KLA-Tencor.

Check out other Process Watch articles: “The Dangerous Disappearing Defect,” “Skewing the Defect Pareto,” “Bigger and Better Wafers,” “Taming the Overlay Beast,” “A Clean, Well-Lighted Reticle,” “Breaking Parametric Correlation,” “Cycle Time’s Paradoxical Relationship to Yield,” and “The Gleam of Well-Polished Sapphire.”