Category Archives: Energy Storage

February 25, 2011 — New research from the University of Pennsylvania demonstrates a more consistent and cost-effective method for making graphene, the atomic-scale material that has promising applications in a variety of fields, and was the subject of the 2010 Nobel Prize in Physics.

As explained in a recently published study on Feb. 10 in the journal Chemistry of Materials, a Penn research team was able to create high-quality graphene that is just a single atom thick over 95% of its area, using readily available materials and manufacturing processes that can be scaled up to industrial levels.

"This research is pushing closer to the ultimate goal, which is 100%," said the study’s principal investigator, A.T. Charlie Johnson, professor of physics. "We have a vision of a fully industrial process."

Other team members on the project included postdoctoral fellows Zhengtang Luo and Brett Goldsmith, graduate students Ye Lu and Luke Somers and undergraduate students Daniel Singer and Matthew Berck, all of Penn’s Department of Physics and Astronomy in the School of Arts and Sciences.

Graphene is a chicken-wire-like lattice of carbon atoms arranged in thin sheets a single atomic layer thick. Its unique physical properties could lead to major advances in solar power, energy storage, computer memory and a host of other technologies. But complicated manufacturing processes and often-unpredictable results currently hamper graphene’s widespread adoption.

One of the more promising manufacturing techniques is chemical vapor deposition (CVD), which involves blowing methane over thin sheets of metal. The carbon atoms in methane form a thin film of graphene on the metal sheets, but the process must be done in a near vacuum to prevent multiple layers of carbon from accumulating into unusable clumps. "If you need to work in high vacuum, you need to worry about getting it into and out of a vacuum chamber without having a leak," Johnson said. "If you’re working at atmospheric pressure, you can imagine electropolishing the copper, depositing the graphene onto it and then moving it along a conveyor belt to another process in the factory."

The Penn team’s research shows that single-layer-thick graphene can be reliably produced at normal pressures if the metal sheets are smooth enough. Johnson’s group used commercially available copper foil in their experiment. "The fact that this is done at atmospheric pressure makes it possible to produce graphene at a lower cost and in a more flexible way," Luo, the study’s lead author, said.

Other methods make expensive custom copper sheets in an effort to get them as smooth as possible; defects in the surface cause the graphene to accumulate in unpredictable ways. Instead, Johnson’s group electropolished their copper foil, making it smooth enough to produce single-layer graphene over 95% of its surface area.

Working with commercially available materials and chemical processes that are already widely used in manufacturing could lower the bar for commercial applications.

"The overall production system is simpler, less expensive, and more flexible," Luo said.

This research was supported by Penn’s Nano/Bio Interface Center through the National Science Foundation. Learn more at www.upenn.edu

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February 24, 2011 — NEC Corporation (NEC; TSE: 6701) announced the development of a compact sensor that measures the power consumption of electronic devices and delivers this information to energy management systems, without needing an external power supply or battery. An independent power supply to the sensor is achieved through energy harvesting.

Energy harvesting converts energy from a surrounding area into electrical energy without the need of an external power source. Although this method can be used to convert magnetic fields emitted from power lines into an operating electric supply, energy harvesting can only convert about 1mW of power, which is insufficient for sensors currently that are used to measure power consumption and send data to an energy management system.

These newly developed sensors consume less than 1mW of power by leveraging an original circuit design that enables them to both measure the power consumption of electric devices and transmit data. As a result, these sensors can provide visibility of electrical device power consumption without the need of an external energy supply. Furthermore, since these sensors do not require data transmission devices, such as wireless interfaces, they may be easily managed and produced in a compact size.

Research by NEC:
Development of a monitoring sensor that enables high precision, low power, continuous real time monitoring and measurement of current waveforms that are consumed by electronic devices. These measurements identify distinctions between each device and provide detailed information on energy consumption and operational status that also enable the detection of unusual operating conditions.

Development of a data transmission circuit that uses the measurement object’s AC power line as a transmission path to send current waveform information to a management system in order to calculate power consumption. This has eliminated the need for wireless transmission devices to send data to energy management systems, which has increased usability and enabled the miniaturization of sensors.

Development of a control circuit that manages the power consumption of sensors by alternately operating the monitoring circuit and data transmission circuit described in the points above. The control circuit ensures that the same level of power is consumed both when the monitoring circuit is operated and when the data transmission circuit is operated. The control circuit accomplishes this by concentrating its operations during the same time as the, relatively low power consuming, monitoring circuit’s operations. Conversely, the control circuit’s operations are stopped while the, relatively high power consuming, data transmission circuit is operating. As a result, these new sensors can measure current waveforms and transmit data while consuming less than 1mW of power, which enables them to operate without the use of an external power supply.

These new sensors, which enable the visualization of power consumption while being free from battery or transmission device maintenance, are suitable for a wide range of electronic devices. Looking forward, NEC will continue to develop power management systems for electronic devices that capitalize on these sensors and contribute to the realization of a low-carbon society.

NEC will present the results of this research on February 22 at the IEEE International Solid State Circuits Conference (ISSCC 2011), held February 20 -24 in San Francisco, California, U.S.A.
More from ISSCC:

NEC Corporation enables IT and network technologies that benefit businesses and people around the world. For more information, visit NEC at http://www.nec.com.

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February 16, 2011 — The realization of self-powered microsystems for medical implants, drug delivery, remote monitoring, or safety-driven applications forms the basis behind a new project being run at the UK’s NPL by the Functional Materials Group. The goal is to replace batteries in these applications with an energy-scavenging power supply.

This energy harvesting power supply would eliminate the environmental hazards and costs associated with battery technologies. Energy harvesting covers the scavenging of many low-grade energy sources such as environmental vibrations, human power, thermal sources, wind energy and their conversion into useable electrical energy.

This project is concerned mainly with environmental vibrations and human power, where the transformation of mechanical to electrical energy is used to power small autonomous devices. The conversion can be achieved by various methods; however, the most promising options for MEMS devices include magnetic, piezoelectric and magnetostrictive transformation.

Example applications might include airborne particle detection in massively parallel autonomous sensing systems (motes), medical condition monitoring with embedded active drug delivery systems, and the development of structural health monitoring systems that scavenge innate vibrations for self power.

The global market for microsystems technology is estimated at $35 billion (2002 – Nexus: Market analysis for MST 2000-2005), with biomedical applications estimated at EU12B.There are a wide range of UK companies that would benefit from this understanding of this technology, from healthcare to transport, the energy sector, aerospace and defense sectors, where MST is given a high priority. The expected time frame during which this technology will be demonstrated extends from 2 to 5 years for defense applications associated with the Smart Soldier concept to 3-7 years for domestic appliances (MP3 players with built-in energy scavengers for example).

Knowledge will be shared with all partners onboard the project, whilst the wider community will enjoy open access to the generic metrology output in the form of web-based tools, new pre-normative standards documents, and the work will be further assessed for quality through the peer-reviewed publication process. Case studies will demonstrate the concepts so that organizations not in the materials supply market will gain a better understanding of the benefits associated with energy harvesting.

Read more in the recent edition of NPL’s Environmental Measures at http://www.npl.co.uk/publications/newsletters/

The National Physical Laboratory (NPL) is the UK’s National Measurement Institute and is a world-leading centre of excellence in developing and applying the most accurate measurement standards, science and technology. Read about NPL’s Functional Materials research at http://www.npl.co.uk/advanced-materials/materials-areas/functional/

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February 8, 2011 – BUSINESS WIRE — ADA Technologies Inc. received an $70,000 contract from the U.S. Army for Phase I research into the development of advanced electrochemical ultracapacitor systems for use in hybrid electronic vehicles (HEVs) for high-power military applications.

ADA’s research will leverage its recent work funded by the National Science Foundation (NSF) in which new low-cost carbon nanotube (CNT) nanocomposite electrode materials were developed and proven in pouch-cell testing.

"ADA has considerable expertise in CNT nanotechnology. We expect the successful completion of this Phase I research to lead to development of ultracapacitors with the energy and power densities needed for military applications. In addition, these ultracapacitors will have safe operation over a wide temperature range and excellent cycle life," said Douglas Campbell, ADA R&D program manager.

ADA’s work will be performed in partnership with Maxwell Technologies, Inc., a commercial provider of ultracapacitors for HEV applications.

This material is based upon work supported by the US Army Tank-Automotive Research Development and Engineering Center (TARDEC) under Contract No. W56HZV-11-C-0058.

ADA Technologies Inc. is a research, development, and commercialization company that specializes in creating and converting innovative technologies to commercial successes. For more information, visit www.adatech.com

Also read: Destination Nano: Saluting nanotech’s defense apps  by news editor James Montgomery

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(January 10, 2011 – BUSINESS WIRE) — World investment in renewable energy will top $2 trillion on a cumulative basis from 2010 through 2015, driven by growth in Asia, North America, and Europe. Were the companies building these generating plants to utilize existing, commercially available nanotechnologies, ABI Research estimates, over the same five-year period renewable power producers could save nearly $300 billion in capital expenditure.

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For example, says research director Larry Fisher of NextGen (ABI Research’s emerging technologies research incubator), "Incorporating nanomaterials into wind turbine blades can make them stronger, lighter and more durable, so they last longer while generating more electricity."

The Energy Information Administration (EIA) of the US Department of Energy (DOE) expects world energy consumption to grow 44% from 2008’s 283 quadrillion BTUs to 678 quadrillion BTUs (7.15 exajoules) by 2030. This increase will be driven by growing energy demand from developing nations such as China and India. Concurrently, the monetary and environmental costs of fossil fuel-based power are making it necessary for governments around the world to shift electricity production to alternative forms of energy.

Fisher observes that, "The addition of nanomaterials to manufacturing processes makes solar cells, wind turbines and fuel cells cheaper to produce, while improving their efficiency in generating electricity. These factors together make even more convincing the argument that we need to move our electrical production away from fossil fuels and increasingly toward renewable sources."

ABI Research anticipates that between 2010 and 2015, new solar photovoltaic installations and new wind installations implemented over the forecast period will total 652 gigawatts (GW) of new energy production. Fuel cell shipments will total more than 35 million units over that period as well, indicating that sector is on the cusp of global commercialization.

A new study by ABI Research, "Nanotechnologies for Green Power Generation" (http://www.abiresearch.com/research/1005396) examines how the use of nanotechnology and nanomaterials in the production of solar (photovoltaic) cells, wind turbines and blades, and fuel cells, can increase these products’ efficiency in generating electricity, as well as reducing manufacturing costs and improving durability. It is part of the firm’s Energy and Clean Technology Research Service (http://www.abiresearch.com/products/service/Energy_And_Green_Technology_Research_Service).

ABI Research provides in-depth analysis and quantitative forecasting of trends in global connectivity and other emerging technologies. For more information visit www.abiresearch.com

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Executive Overview

The opportunities that nanotechnology presents to our industry are many, and a short article cannot come close to covering the breadth implied by this title! However, following a general introductory discussion, a few selected examples will help build an understanding of basic concepts behind some of the latest nanoelectronics research efforts. Most of the examples are taken from university research on potential "beyond-CMOS" device technologies funded by an industry-government partnership. References to more detailed publications on these projects are included to serve as a "pointer to the literature" on some of today’s most significant nanodevice research.

Robert Doering, Texas Instruments, Dallas, Texas, USA

In common usage, "nanotechnology" refers to structures (i.e., devices) and materials (and processes to fabricate them) that exhibit useful properties resulting from sub-100nm features. Note, however, that a somewhat vague restriction to "qualitatively new" is also usually included. For example, 90nm (or even 30nm) gate-length MOSFETs are not considered "nanotechnology" in many circles.

This point is even better illustrated via an informal poll of materials scientists and chemists at a meeting a few years ago, which indicated substantial agreement that nylon would be called a "nanotechnology" material if it had been invented "last week" rather than in 1935! Of course, this is just one of many examples from chemical synthesis illustrating the difficulty in creating a simple definition of "nanotechnology."

The current common usage of "nanotechnology" also usually implies something revolutionary rather than evolutionary. With respect to semiconductor product manufacturing, this criterion generally encourages focus on examples that are typically a decade or more from potential implementation.

Volume manufacturing

In the relatively near term, it appears that most of the opportunities for nanotechnologies in volume manufacturing involve nanomaterials as replacements for traditional materials. Note that the distinction between "nanomaterials/particles" and "conventional materials/particles" is often characterized, not just by structure size, but also by the degree to which they are "engineered" for specific combinations of properties. 

In current research, the "hot topic" nanomaterial for potential electronic applications is graphene, the subject of the 2010 Nobel Prize in Physics. Graphene is a single atomic layer of graphite (an allotrope of carbon), in various shapes (e.g., "nanoribbons") and orientations. Graphene has amazing properties, in part, stemming from a band structure that exhibits linear, rather than the usual quadratic, dependence of energy on momentum (i.e., like a "relativistic" particle). Its potential uses include ultracapacitors [2], transparent conductive electrodes for PV (replacement for expensive indium tin oxide) [3, 4], various forms of transistors, and many more. Although cost reduction would be the major benefit of using a nanomaterial in some cases, enhancement of material properties is generally the primary objective. Another electronics-industry example of the latter is improving the electrical and thermal conductivity of bonding materials, such as in packaging applications [5].

As we move to the "device level," there are often a greater number of nano-material/structure properties that must be simultaneously optimized, and, of course, the device manufacturing is typically more sensitive to contamination. However, as for packaging, the most straight-forward device opportunities for the introduction of nanotechnology are also in the form of materials replacements or additives. A long-pursued example is the use of nanoparticles in nonvolatile memory [6]. There are many others, but the remainder of this article is devoted to highlighting a few of the potential device nanotechnologies that are currently being explored as possible alternatives to CMOS transistors in future semiconductor manufacturing.

History of nanoelectronics development

In 2003, the Semiconductor Industry Association (SIA) formed a Nanoelectronics Working Group, which recommended that industry and government partner to sponsor increased university research in two related areas: (1) novel nanodevices targeted at density, power efficiency, and speed beyond estimated ultimate limits for scaled CMOS, and (2) a novel form of nanomanufacturing that would allow the industry to dramatically depart from the increasing capital and operating cost trends that are so familiar in the traditional "deposit/pattern/etch" (a.k.a, thin-film "planar process") paradigm of the last half century.

These recommendations were presented both to the President’s Council of Advisors on Science and Technology (in 2003) [7] and to the SIA Board of Directors. In March of 2005, six of the SIA member companies, AMD, Freescale, IBM, Intel, Micron, and Texas Instruments, responded by forming the Nanoelectronics Research Initiative (NRI), a consortium activity that funds university research as a part of the Semiconductor Research Corporation (SRC). In 2010, the corporate members of NRI are AMD/Global Foundries, IBM, Intel, Micron, and Texas Instruments. NRI is also currently supported by the National Institute of Standards and Technology (NIST), the National Science Foundation (NSF), and several state and local governments.

Thus far, the NRI research has identified quite a few possible approaches to "beyond CMOS" devices, which are currently at various stages of theoretical and experimental evaluation. A first pass has also been made at estimating their performance against a consensus "ultimate CMOS," which is currently equated to what is popularly called "the 15nm technology node." Details of this initial comparison have been submitted for publication [8].

The remainder of this article provides very brief descriptions of just a few of the NRI device concepts currently under study and encourages interested readers to consult specific references for detailed accounts of the research completed to date.

Exploring new switching devices

The biggest challenge in replacing the basic field-effect transistor (FET) as a switch is that it is already extremely good and further scalable! As long as its materials properties can be improved and the manufacturing technology/cost is up to the feature-scaling task, the conventional FET theoretically approaches performance and energy efficiency close to physical limits imposed by the uncertainty principal, equilibrium thermodynamics, and electrodynamics, at least for devices based on individual charged-particle (e.g., electron) behavior.

The history of studying these limits goes back to Von Neumann and was well summarized by Meindl a decade ago [9]. This recognition has prompted much of the early NRI research to focus on information state variables that are alternative to "the amount of electrical charge on FET gates" employed by CMOS logic. It has also encouraged some study of non-equilibrium operation and "thermal-phonon engineering."

Despite the just-mentioned excellence of scaled/materials-enhanced FETs, NRI research indicates that several forms of tunnel FETs (TFETs) may use less power at a given speed. An enabler for such TFETs could be graphene-nanoribbon channels [10]. In fact, many of the currently-studied NRI switches are based on using graphene in some part of the nanostructure. Thus, it’s possible that "carbon nanoelectronics" may at least augment silicon CMOS at some point in the future. Of course, we are a long-way from volume manufacturing of integrated circuits with graphene. However, NRI process/materials research has already produced a promising breakthrough in CVD of large-area graphene layers [11], which could have many uses, including the manufacturing of TFETs and more-exotic devices, as well as the previously-mentioned transparent-electrode application.

Another graphene-based switch being studied in NRI is the Veselago device [12], which is designed to manipulate electron wave functions as if they were electromagnetic waves (i.e., analogously to optics). Such devices take advantage of the focusing properties of p-n junctions in graphene and have been estimated to have the potential for very high speed.

Note that the devices previously discussed all still use "quantity of electric charge" as the logic state variable. Of course, in hard-disk and some other memories, atomic-spin orientation has long been used to represent information. So far, commercial spin-based memories have all employed spin in the form of magnetic domain orientation.

Figure 1. Magnetic force micrograph of a one-bit full adder constructed with permalloy nanomagnets. The arrows indicate the in-plane magnetic field polarity. The individual nanomagnets in the circuit are 60x90nm, with a thickness of 30nm deposited on oxidized silicon. SOURCE: Courtesy of Edit Varga, Nanomagnet Logic Group, and Alan Seabaugh and Wolfgang Porod, NRI Midwest Institute for Nanoelectronics Discovery, University of Notre Dame.

NRI research has shown that magnetic states can also be used to perform "nanomagnet logic" (NML) [13], as demonstrated in Fig. 1. Like most of the NRI spin-based devices studied thus far, NML seems to fit best with applications requiring very low power at modest speed. NRI also conducts research on devices based on electron-spin transport [14]. In some devices, the spin-state information can be moved between logic elements without transporting any electric charge, an obvious advantage for low-power operation. A general challenge for the spin-based devices is that they do not tend to have intrinsic gain and, thus, need occasional logic-level boosts.

Exploring collective "pseudospin"

One of the most exciting approaches to alternative logic state variables is the potential exploitation of collective quantum phenomena as opposed to single-particle states. Perhaps the most exotic state variable explored thus far in the NRI program is collective "pseudospin."

Actually, several different phenomena are labeled as pseudospin in modern physics. All share the simple Pauli mathematics of two-state quantum systems originally developed for description of the "ordinary spin" (i.e., intrinsic angular momentum) of spin-1/2 particles. The form of pseudospin most studied in NRI corresponds to the discrete "which-layer?" degree of freedom for the location of an electron in a bilayer graphene system. Note that "top/bottom layer" is analogous to "up/down spin."

The really exciting aspect of this form of pseudospin is the theoretical prediction that the ground state of a suitable graphene bilayer may be an above-room-temperature Bose-Einstein condensate corresponding to a coherent superposition of excitons, each consisting of an electron on one layer and a hole on the other [15]. If this prediction is correct, such a condensate would be the first room-temperature superfluid.

A simple way of understanding why this might be possible is to recognize that the binding between electron and hole in each exciton is due to their relatively strong mutual electrostatic attraction – much stronger than the lattice-distortion attraction between the Cooper pairs of electrons in the condensate corresponding to standard superconductivity. Of course, the weakly-bound Cooper pairs "fall apart" far below room temperature.

Figure 2. Current path in a bilayer-pseudospin field-effect transistor (BiSFET) as modulated by gate control of Bose-Einstein exciton condensate formation. SOURCE: Courtesy of Seyoung Kim, Emanuel Tutuc, and Sanjay K. Banerjee, NRI Southwest Academy of Nanoelectronics, University of Texas at Austin.

One of the criteria for formation of the bilayer exciton condensate is optimum spacing (perhaps via an intervening dielectric) of the graphene layers. Other criteria are related to the quality of the graphene layers and their mutual alignment. An NRI logic device based on such a superfluid condensate of excitons is the bilayer pseudospin FET (BiSFET) [16], which controls the presence or absence of the condensate via applied gate voltages. BiSFET operation is schematically illustrated in Fig. 2.

Fostering collaboration

One of the strengths of NRI is the interdisciplinary collaboration that it fosters between electrical engineers, physicists, materials scientists, et al. The potential room-temperature Bose-Einstein condensate just discussed is of obvious interest to physicists and material scientists even as "merely" a new solid-state phenomenon – one which could lead to future Nobel Prizes! However, turning this phenomenon, if it exists at room temperature, into a logic building block, such as a BiSFET, also requires investigation at the circuit level, led by the electrical engineers, but still in need of broad collaboration.

For example, in communicating with each other, such devices may need sophisticated clocking schemes, which could dilute their power-delay-product advantage over ultimate CMOS if ordinary FET clocks were needed as part of a hybrid circuit. This is analogous to the aforementioned limitation of the electron-spin devices in needing periodic logic-level boosts from devices with gain (most likely conventional FETs). In fact, a general issue at the circuit level for many of the NRI devices is an efficient mechanism for rapidly transporting the logic state from device to device. Note that this might be accomplished via an "information token" (the form in which logic state is transported) that is distinct from the logic-state variable itself.

Figure 3. Schematic view of spin wave majority-gate logic. A bit of information is encoded into the phase of the propagating spin wave (e.g., relative phases 0 and "pi" correspond to logic states 0 and 1, respectively). The phase of the output spin wave is determined by interference as the majority of phases of the input signals. SOURCE: Courtesy of Kang L. Wang, Alex Khitun, and Ming Bao, NRI Western Institute of Nanoelectronics, University of California at Los Angeles.

One approach is to use electromagnetic waves (from RF to light) to transport electric-charge-state information from one circuit to another. However, this requires emission/detection conversion processes, which generally compromise overall power efficiency. Thus, NRI has also explored a related option in which surface plasmons rather than photons are the information tokens [17]. Surface plasmons are quasiparticles representing correlated electron-photon states, and they negotiate sharp turns more efficiently than "stand-alone" photons. Overall, the transport or "interconnect" problem is often just as large a challenge as the "switch" problem. Therefore, some of the NRI devices, such as the NML, "spinwave" [18] and Veselago devices, intrinsically integrate information transport into the basic concept. Spinwave logic is depicted in Fig. 3.

Conclusion

In summary, the NRI results to date generally offer more encouragement for surpassing the capabilities of CMOS in achieving lower-power operation (at a given speed) rather than far higher ultimate speeds [6]. At this point, the NRI program has not yet identified any single, most-promising candidate for a beyond CMOS nanotechnology. However, if we are fortunate, there may eventually be several.

References

1. M. S. Fuhrer, C. N. Lau, A. H. MacDonald, "Graphene: Materially Better Carbon," MRS Bulletin, vol. 35, pp. 289-295, April, 2010.

2. M. D. Stoller, S. Park, Y. Zhu, J. An, R. S. Ruoff , "Graphene-Based Ultracapacitors," Nano Letters, vol. 9, no. 10, pp. 3498-3502, Sept. 13, 2008.

3. M. Wilson, "Graphene Production Goes Industrial," Physics Today, vol. 63, no. 8, pp. 15-16, August, 2010.

4. S. Bae, et al., "Roll-to-roll Production of 30-inch Graphene Films for Transparent Electrodes," Nature Nanotechnology, vol. 5, pp. 574-578, June, 2010.

5. D. Wakuda,   K.-S. Kim,   K. Suganuma, "Ag Nanoparticle Paste Synthesis for Room Temperature Bonding," IEEE Trans. on Comp. and Packaging Tech., vol. 33, no. 2, pp. 437-442, June, 2010.

6. D. Tsoukalas, "From Silicon to Organic Nanoparticle Memory Devices," Philosophical Trans. of the Royal Society, A28, vol. 367, no. 1905, pp. 4169-4179, Oct., 2009.

7. R. Doering, "Nanotechnology Research Recommendations," public meeting of the President’s Council of Advisors on Science and Technology, Washington, D.C., Dec. 2, 2003.

8. K. Bernstein, R. Cavin, W. Porod, A. Seabaugh, J. Welser, "Device and Architecture Outlook for Beyond-CMOS Switches," to be published in Proc. of the IEEE, submitted in January, 2010.

9. J. D. Meindl, Q. Chen, J. A. Davis, "Limits on Silicon Nanoelectronics for Terascale Integration," Science 14, vol. 293. no. 5537, pp. 2044 – 2049, Sept., 2001.

10. Q. Zhang, T. Fang, H. Xing, A. Seabaugh, D. Jena, "Graphene Nanoribbon Tunnel Transistors," IEEE Electron Device Lett., vol. 29, pp. 1344-1346, 2008.

11. X. Li, W. Cai, E. Tutuc, S.K. Banerjee, L. Colombo, R. S. Ruoff, et al., "Large-Area Synthesis of High-Quality and Uniform Graphene Films on Copper Foils," Science 5, vol. 324. no. 5932, pp. 1312 – 1314, June, 2009.

12. V. V. Cheianov, V. Fal’ko, B. L. Altshuler, "The Focusing of Electron Flow and a Veselago Lens in Graphene p-n Junctions," Science 2, vol. 315. no. 5816, pp. 1252 – 1255, March, 2007.

13. M. Alam, G. H. Bernstein, J. Bokor, D. Carlton, X. S. Hu, S. Kurtz, et al., "Experimental Progress of and Prospects for Nanomagnet Logic (NML),"Technical Digest of the 2010 IEEE Symposia on VLSI Technology and Circuits, Honolulu, HI, June, 2010.

14. B. Behin-Aein, D. Datta, S. Salahuddin, S. Datta, "Proposal for an All-spin Logic Device with Built-in Memory," Nature Nanotechnology 5, pp. 266 – 270, Feb., 2010.

15. H. Min, R. Bistritzer, J.-J. Su, A. H. MacDonald, "Room-temperature Superfluidity in Graphene Bilayers," Phys. Review B, vol. 78, 121401, Sept., 2008.

16. D. Reddy, L. F. Register, E. Tutuc, S. K. Banerjee, "Bilayer PseudoSpin Field-Effect Transistor: Applications to Boolean Logic," IEEE Trans. on Electron Devices, vol. 57, no. 4, p. 755, April, 2010.

17. A. Hosseini, H. Nejati, Y. Massoud, "Design of a Maximally Flat Optical Low-pass Filter Using Plasmonic Nanostrip Waveguides," Optics Express, vol. 15, no. 23, 1528112, Nov., 2007.

18. A. Khitun, M. Bao, Y. Wu, J.-Y. Kim, A. Hong, A. P. Jacob, et al., "Logic Devices with Spin Wave Buses – an Approach to Scalable Magneto-Electric Circuitry," MRS Symp. Proc., vol. 1067, B01-04, 2008.

Biography

Robert Doering is a Sr. Fellow and Research Strategy Manager at Texas Instruments, P.O. Box 650311, MS 367, Dallas, Texas 75265; ph.: 972-995-2405; email: [email protected].

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(December 30, 2010 – BUSINESS WIRE) — ActaCell Inc. was awarded up to $3 million over a 3-year period in funding from the U.S. Department of Commerce’s National Institute of Standards and Technology (NIST). The funding will focus on production scale up of nanocomposite alloy anode materials for lithium-ion batteries to be used in electric vehicles and other demanding applications.

ActaCell won one of nine awards from NIST and is the only energy storage company recognized. The funding will come through NIST’s Technology Innovation Program (TIP). The competition focused on technologies that could scale up advanced materials and significantly improve critical manufacturing processes. TIP promotes technological innovation by providing funding support for transformative, high-risk, high-reward research projects that address critical national needs.

Actacell recently exclusively licensed the nanomaterial from the Material Sciences and Engineering Program at the University of Texas at Austin, said Bill Ott, president and CEO of ActaCell. In regards to the award, Ott noted that "the challenge with all cutting-edge technologies is the ability to scale up production. We are very confident that, through this project, we will be able to bring a whole new approach to batteries to the emerging pure electric vehicle industry."

This new electric vehicle technology is in addition to the company’s initial lithium-ion technology targeted at the Hybrid Electric Vehicle Market. Recently, ActaCell identified the medium-to-heavy duty hybrid truck market as the initial best fit for its technology based on a set of rigorous tests run in conjunction with AVL Powertrain, an engineering, solution and testing company for the automotive industry. Additionally, ActaCell was awarded a $179, 015, 16-month technology assessment of high-power cells to meet requirements specified by USABC for power-assist hybrid-electric vehicle (PAHEV) applications. The primary purpose of the USABC contract will be to assess the performance, cycle life and accelerated calendar life of ActaCell’s HEV batteries.

ActaCell is commercializing this new lithium-ion anode technology based on its ability to deliver substantially lower cost and improved safety for materials used in pure electric vehicles. ActaCell continues to leverage the work done by Professor Arumugam Manthiram and his team in the Materials Science Lab at the University of Texas at Austin. Professor Manthiram is a world-renowned scientist with more than 20 years of experience in lithium-ion battery technology. To date, ActaCell has received nearly $7 million in funding.

ActaCell develops Li-Ion technologies for motive applications. Learn more at http://www.actacell.com/

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by Michael A. Fury, Techcet Group

December 22, 2010 – The third day of IEDM 2010 (12/08/10) began with seven parallel sessions as did Day 2. The only unique session that was not a continuation from the previous days was on characterization, reliability and yield for RTN (random telegraph noise) in memory devices. I, however, found other topics of greater interest personally.

(Additional information can be found online at 2010 IEDM Technical Program. All figures are reproduced with permission of IEDM.)

27.1: A new FinFET process for 22/20nm devices was presented by C.C. Wu of TSMC, made possible largely by a litho/etch integration scheme that produces very vertical fin sidewalls. The resulting structure give comparable IOn /IOff for both PFET and NFET devices, and claims a best-in-class drive current. The data showed a 100× reduction in leakage current compared to comparably sized planar devices, and the HKMG reliability is similar to planar devices as well. A manufacturable 0.1μm2 SRAM cell was shown.

Left: Top view image of the high-performance 0.1μm2 SRAM bit cell showing good pattern fidelity. Right: IOn /IOff curves show IOn = 1200 μA/μm for NFET and 1100 μA/μm for PFET at IOff =100nA/μm at VDD=1V.

29.2: PCRAM for embedded memory applications was raised from a vertical to a planar device using a phase-change (PC) dog-bone structure between two electrodes, as shown by K. Attenborough of the NXP-TSMC Research Center. Devices were successfully embedded in a 65nm CMOS process using doped Sb2Te. Proper encapsulation of the PC layer is critical to device performance and reliability. The PC layer requires three additional masks, and is completed before standard Cu BEOL begins. The operational switching range is between 103Ω and 106Ω states. With an optimized PC material, device lifetime is projected to be 10 years at 95°C.

 
Left: SEM top view (far left) and TEM top view (right) of integrated horizontal line-type PCM cells in contact with bottom electrode in 65nm CMOS process. Right: Numerical simulation of the temperature distribution along the center of the line. The dashed lines show the positions of the electrode edges. The dotted lines indicate the edges of the molten area.

31.3: Autonomous microelectronics systems are, by definition, required to provide their own power sources. One way to achieve this is to build a solar cell on top of the CMOS circuitry, which is what J. Lu of the MESA+ Institute for Nanotechnology talked about. Both amorphous silicon (a-Si) and copper-indium-gallium-selenide (CIGS) cells were integrated with 0.25μm Al BEOL and 0.13μm Cu BEOL. Compatibility issues of adhesion, mobile ion contamination, plasma induced damage, peak process temperatures and mechanical stress were all noted and addressed successfully. CIGS is best integrated on the chip backside, while the wider process window for a-Si makes front side integration preferred. It was never clear to me in the Terminator stories if this is how Skynet got started.

Top: , comprising a PV cell for energy collection; power management circuits in CMOS; integrated energy storage (high-density capacitor or solid-state battery) and low-power circuits. The PV cell can be realized on the chip’s front (CMOS) side or the back side. Bottom: Schematic cross-section of a-Si solar cell on CMOS chip (left) and CIGS solar cell on CMOS chip (not to scale).

32.4: Returning to the graphene session, K. Majumdar of the Indian Institute of Science simulated a dual gated device with doped semiconductor source & drain and a bilayer graphene (BLG) channel. The bandgap-free nature of graphene is overcome by inducing a bandgap with the dual gates. Objective of the modeling is to obtain complementary unipolar BLG FETs for logic devices. The simulated device characteristics compare well with state of the art Si technology, with IOn /IOff >104 and a subthreshold slope of ~110mV/decade for a 20nm gate length.

(a) Schematic of a d with source (S) and drain (D). (b) Bandstructure of an unbiased infinite BLG film with zero bandgap. (c) Bandgap opening in a "Mexican hat" shape under applied external vertical field. (d) Typical experimental transfer characteristics of a metal S/D BLG FET with on-off ratio of ~100 at Vdd=1mV and T=295K.

27.5: In the quest for superlatives, N. Butt of IBM SRDC laid claim to the smallest embedded DRAM cell (0.0394μm2) and the densest memory integrated into the highest performance 32nm HKMG SOI logic technology with 1.5nsec access time at VDD of 1V, and up to 13 levels of Cu interconnect. This deep trench eDRAM reportedly outperforms SRAM for cache-hungry multi-core processors, with 3-4× smaller area, 5× lower standby power, and 1000× better soft error reliability. ‘Nuff said; I’m impressed.

Key elements for eDRAM array design

 

Retention Variability Performance
Sub-threshold leakage Random dopant fluctuations DT resistance/capacitance
Junction leakage/GIDL Process variations Buried strap resistance
DT capacitance Line edge roughness Gate override

 
 

DT resistance extracted from S-parameter measurements for different trench processes. Inset shows the TEM image of HK/DT node stack.

31.6: At first it wasn’t clear to me why you would want a device that can switch its energy harvesting from PV to TE (thermoelectric) modes, but I have seen the light and felt the heat. T. Suzuki at Fujitsu Laboratories demonstrated an organic thin film device that can do both. When the P/N stacks are connected in series, you have a PV device; in parallel, the same stacks function as a TE device. One of the key process tricks is to dope the first P3HT layer with an atomized solution of FeCl3 and anneal it at 150°C for a uniform doping profile. Target applications include wearable healthcare monitors.

Schematic cross-sectional view of a hybrid device. A mixed layer of PCBM and undoped P3HT, which consists of a so-called bulk hetero-junction PV cell, is formed upon a doped P3HT. TE power is generated in doped P3HT film. The chemical structures are also shown.

 

Typical application using the hybrid PV/TE module. The hybrid device on a flexible substrate would be highly effective as a wearable healthcare device in the conditions where light irradiation is not essential. (a) Test module fabricated on a flexible substrate. (b) Schematic cross section of the flexible hybrid module. Copper films were patterned alternately on an upper and lower film. The difference in the thermal conductivities of copper and PI films yields the thermal difference in a P3HT film, and generates electric power in TE mode. (c) Cross-sectional view of a typical flexible module.

29.7: Replacing hard drives with NVRAM is now a bit (no pun intended) closer to reality in S.J. Whang’s paper from Hynix R&D 3D dual control gate NAND flash with a surrounding floating gate (FG). This DC-SF NAND is fabricated as a vertical device through an alternating stack of poly and oxide layers. The control gates prevent charge spreading in the floating gate, resulting in reliable retention characteristics, and also provide shielding so that FG-FG interference is low at 12mV/V. Stacking the multi-bit (2-4 bits/cell) DC-SF NAND provides a path to file storage devices of 1Tb and beyond.

Cross-sectional schematic of DC-SF NAND flash with sharing FG structure implemented in this experiment.
Bird’s view of DC-SF NAND flash. Surrounding FG has capacitive.

 

Michael A. Fury, Ph.D, is senior technology analyst at Techcet Group, LLC, P.O. Box 29, Del Mar, CA 92014; e-mail [email protected].

(December 16, 2010) — Channels in transmembrane proteins are small enough to allow ions or molecules of a certain size to pass through, while keeping out larger objects. Artificial fluidic nanochannels that mimic the capabilities of transmembrane proteins are highly prized for advanced technologies in biomedical, battery, and other technology sectors. However, it has been difficult to make individual artificial channels of this nanoscale size, until research performed by the US DOE’s Berkeley Lab.

Schematic of a 2nm nanochannel device, with two microchannels, ten nanochannels and four reservoirs. (Image courtesy of Chuanhua Duan)

Researchers with the U.S. Department of Energy (DOE)’s Lawrence Berkeley National Laboratory (Berkeley Lab) have been able to fabricate nanochannels that are only 2nm in size, using standard semiconductor manufacturing processes. Already they’ve used these nanochannels to discover that fluid mechanics for passages this small are significantly different not only from bulk-sized channels, but even from channels that are merely 10nm in size.

"We were able to study ion transport in our 2nm nanochannels by measuring the time and concentration dependence of the ionic conductance," says Arun Majumdar, director of DOE’s Advanced Research Projects Agency – Energy (ARPA-E), who led this research while still a scientist at Berkeley Lab. "We observed a much higher rate of proton and ionic mobility in our confined hydrated channels — up to a fourfold increase over that in larger nanochannels (10 to 100nm). This enhanced proton transport could explain the high throughput of protons in transmembrane channels."

Majumdar is the co-author with Chuanhua Duan, a member of Majumdar’s research group at the University of California (UC) Berkeley, of a paper on this work, which was published in the journal Nature Nanotechnlogy. The paper is titled "Anomalous ion transport in 2nm hydrophilic nanochannels."

In their paper, Majumdar and Duan describe a technique in which high-precision ion etching is combined with anodic bonding to fabricate channels of a specific size and geometry on a silicon-on-glass die. To prevent the channel from collapsing under the strong electrostatic forces of the anodic bonding process, a thick (500nm) oxide layer was deposited onto the glass substrate.

Chuanhua Duan was part of a successful Berkeley Lab effort to fabricate nanochannels that measured only two nanometers in size, using standard semiconductor manufacturing processes. (Photo by Roy Kaltschmidt, Berkeley Lab Public Affairs)

"This deposition step and the following bonding step guaranteed successful channel sealing without collapsing," says Duan. "We also had to choose the right temperature, voltage and time period to ensure perfect bonding. I compare the process to cooking a steak, you need to choose the right seasoning as well as the right time and temperature. The deposition of the oxide layer was the right seasoning for us."

The nanometer-sized channels in transmembrane proteins are critical to controlling the flow of ions and molecules across the external and internal walls of a biological cell, which, in turn, are critical to many of the biological processes that sustain the cell. Like their biological counterparts, fluidic nanochannels could play critical roles in the future of fuel cells and batteries.

"Enhanced ion transport improves the power density and practical energy density of fuel cells and batteries," Duan says. "Although the theoretical energy density in fuel cells and batteries is determined by the active electrochemical materials, the practical energy density is always much lower because of internal energy loss and the usage of inactive components. Enhanced ion transport could reduce internal resistance in fuel cells and batteries, which would reduce the internal energy loss and increase the practical energy density."

The findings by Duan and Majumdar indicate that ion transport could be significantly enhanced in 2nm hydrophilic nanostructures because of their geometrical confinements and high surface-charge densities. As an example, Duan cites the separator, the component placed between the between the cathode and the anode in batteries and fuel cells to prevent physical contact of the electrodes while enabling free ionic transport.

"Current separators are mostly microporous layers consisting of either a polymeric membrane or non-woven fabric mat," Duan says. "An inorganic membrane embedded with an array of 2nm hydrophilic nanochannels could be used to replace current separators and improve practical power and energy density."

Artificial fluidic nanochannels, like these 30nm channels shown under fluorescence, mimic the capabilities of transmembrane proteins and are highly prized for advanced technology applications. (Image courtesy of Majumdar group)

The 2nm nanochannels also hold promise for biological applications because they have the potential to be used to directly control and manipulate physiological solutions. Current nanofluidic devices utilize channels that are 10 to 100nm in size to separate and manipulate biomolecules. Because of problems with electrostatic interactions, these larger channels can function with artificial solutions but not with natural physiological solutions.

"For physiological solutions with typical ionic concentrations of approximately 100 millimolars, the Debye screening length is 1nm," says Duan. "Since electrical double layers from two-channel surfaces overlap in our 2nm nanochannels, all current biological applications found in larger nanochannels can be transferred to 2nm nanochannels for real physiological media."

The next step for the researchers will be to study the transport of ions and molecules in hydrophilic nanotubes that are even smaller than 2nm. Ion transport is expected to be even further enhanced by the smaller geometry and stronger hydration force.

"I am developing an inorganic membrane with embedded sub-2nm hydrophilic nanotube array that will be used to study ion transport in both aqueous and organic electrolytes," Duan says. "It will also be developed as a new type of separator for lithium-ion batteries."

This work was supported by DOE’s Office of Science, plus the Center for Scalable and Integrated Nanomanufacturing, and the Center of Integrated Nanomechanical Systems at UC Berkeley.

Berkeley Lab is a U.S. Department of Energy national laboratory located in Berkeley, CA. It conducts unclassified scientific research and is managed by the University of California for the DOE Office of Science. Visit http://www.lbl.gov.

More info:

Arun Majumdar: http://www.me.berkeley.edu/faculty/majumdar/
ARPA-E: http://arpa-e.energy.gov/
Center for Scalable and Integrated Nanomanufacturing (SINAM): http://www.sinam.org/
Center of Integrated Nanomechanical Systems (COINS): http://mint.physics.berkeley.edu/coins/

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(December 16, 2010) — Channels in transmembrane proteins are small enough to allow ions or molecules of a certain size to pass through, while keeping out larger objects. Artificial fluidic nanochannels that mimic the capabilities of transmembrane proteins are highly prized for advanced technologies in biomedical, battery, and other technology sectors. However, it has been difficult to make individual artificial channels of this nanoscale size, until research performed by the US DOE’s Berkeley Lab.

Schematic of a 2nm nanochannel device, with two microchannels, ten nanochannels and four reservoirs. (Image courtesy of Chuanhua Duan)

Researchers with the U.S. Department of Energy (DOE)’s Lawrence Berkeley National Laboratory (Berkeley Lab) have been able to fabricate nanochannels that are only 2nm in size, using standard semiconductor manufacturing processes. Already they’ve used these nanochannels to discover that fluid mechanics for passages this small are significantly different not only from bulk-sized channels, but even from channels that are merely 10nm in size.

"We were able to study ion transport in our 2nm nanochannels by measuring the time and concentration dependence of the ionic conductance," says Arun Majumdar, director of DOE’s Advanced Research Projects Agency – Energy (ARPA-E), who led this research while still a scientist at Berkeley Lab. "We observed a much higher rate of proton and ionic mobility in our confined hydrated channels — up to a fourfold increase over that in larger nanochannels (10 to 100nm). This enhanced proton transport could explain the high throughput of protons in transmembrane channels."

Majumdar is the co-author with Chuanhua Duan, a member of Majumdar’s research group at the University of California (UC) Berkeley, of a paper on this work, which was published in the journal Nature Nanotechnlogy. The paper is titled "Anomalous ion transport in 2nm hydrophilic nanochannels."

In their paper, Majumdar and Duan describe a technique in which high-precision ion etching is combined with anodic bonding to fabricate channels of a specific size and geometry on a silicon-on-glass die. To prevent the channel from collapsing under the strong electrostatic forces of the anodic bonding process, a thick (500nm) oxide layer was deposited onto the glass substrate.

Chuanhua Duan was part of a successful Berkeley Lab effort to fabricate nanochannels that measured only two nanometers in size, using standard semiconductor manufacturing processes. (Photo by Roy Kaltschmidt, Berkeley Lab Public Affairs)

"This deposition step and the following bonding step guaranteed successful channel sealing without collapsing," says Duan. "We also had to choose the right temperature, voltage and time period to ensure perfect bonding. I compare the process to cooking a steak, you need to choose the right seasoning as well as the right time and temperature. The deposition of the oxide layer was the right seasoning for us."

The nanometer-sized channels in transmembrane proteins are critical to controlling the flow of ions and molecules across the external and internal walls of a biological cell, which, in turn, are critical to many of the biological processes that sustain the cell. Like their biological counterparts, fluidic nanochannels could play critical roles in the future of fuel cells and batteries.

"Enhanced ion transport improves the power density and practical energy density of fuel cells and batteries," Duan says. "Although the theoretical energy density in fuel cells and batteries is determined by the active electrochemical materials, the practical energy density is always much lower because of internal energy loss and the usage of inactive components. Enhanced ion transport could reduce internal resistance in fuel cells and batteries, which would reduce the internal energy loss and increase the practical energy density."

The findings by Duan and Majumdar indicate that ion transport could be significantly enhanced in 2nm hydrophilic nanostructures because of their geometrical confinements and high surface-charge densities. As an example, Duan cites the separator, the component placed between the between the cathode and the anode in batteries and fuel cells to prevent physical contact of the electrodes while enabling free ionic transport.

"Current separators are mostly microporous layers consisting of either a polymeric membrane or non-woven fabric mat," Duan says. "An inorganic membrane embedded with an array of 2nm hydrophilic nanochannels could be used to replace current separators and improve practical power and energy density."

Artificial fluidic nanochannels, like these 30nm channels shown under fluorescence, mimic the capabilities of transmembrane proteins and are highly prized for advanced technology applications. (Image courtesy of Majumdar group)

The 2nm nanochannels also hold promise for biological applications because they have the potential to be used to directly control and manipulate physiological solutions. Current nanofluidic devices utilize channels that are 10 to 100nm in size to separate and manipulate biomolecules. Because of problems with electrostatic interactions, these larger channels can function with artificial solutions but not with natural physiological solutions.

"For physiological solutions with typical ionic concentrations of approximately 100 millimolars, the Debye screening length is 1nm," says Duan. "Since electrical double layers from two-channel surfaces overlap in our 2nm nanochannels, all current biological applications found in larger nanochannels can be transferred to 2nm nanochannels for real physiological media."

The next step for the researchers will be to study the transport of ions and molecules in hydrophilic nanotubes that are even smaller than 2nm. Ion transport is expected to be even further enhanced by the smaller geometry and stronger hydration force.

"I am developing an inorganic membrane with embedded sub-2nm hydrophilic nanotube array that will be used to study ion transport in both aqueous and organic electrolytes," Duan says. "It will also be developed as a new type of separator for lithium-ion batteries."

This work was supported by DOE’s Office of Science, plus the Center for Scalable and Integrated Nanomanufacturing, and the Center of Integrated Nanomechanical Systems at UC Berkeley.

Berkeley Lab is a U.S. Department of Energy national laboratory located in Berkeley, CA. It conducts unclassified scientific research and is managed by the University of California for the DOE Office of Science. Visit http://www.lbl.gov.

More info:

Arun Majumdar: http://www.me.berkeley.edu/faculty/majumdar/
ARPA-E: http://arpa-e.energy.gov/
Center for Scalable and Integrated Nanomanufacturing (SINAM): http://www.sinam.org/
Center of Integrated Nanomechanical Systems (COINS): http://mint.physics.berkeley.edu/coins/