Category Archives: SST

Spansion Inc. today announced production of a new family of 16 Mb, 32 Mb and 64 Mb Spansion FL-1K Serial Flash memory devices.

“Serial Flash is one of the fastest growing memory markets,” said Alan Neibel, founder and CEO of WebFeet Research. “Worldwide serial NOR Flash shipments will grow from $1.34 billion in 2012 to greater than $2 billion by 2015. Customer platforms, particularly those with low to mid-density storage needs, benefit from serial Flash solutions for its small form factor and low pin count as a means to simplify board layouts and reduce cost."

"With the introduction of FL-1K family, Spansion continues to expand its serial peripheral interface (SPI) portfolio, delivering high performance, code-efficient small sectors and advanced security for next generation electronics," said Jackson Huang, vice president of product marketing at Spansion. "In particular, the FL-1K’s flexible data protection and one-time-programmable (OTP) features help prevent unintentional programming errors and hacking, allowing for a more secure user experience and high levels of system integrity."

The entire Spansion FL Serial Flash portfolio scales from 4 Mb up to 1 Gb to serve the broad needs of embedded applications with input output (IO) options for single, dual and quad bit read operation as well as a double data rate (DDR) mode that doubles the read throughput of the system.

Samsung announced today that it is mass producing the world’s fastest embedded memory – the industry’s first eMMC 5.0 devices – in 16 gigabyte (GB), 32GB and 64GB densities for next-generation smartphones and tablets.

Featuring an interface speed of 400 megabytes per second (MB/s), the lightning-fast eMMC PRO memory provides exceptionally fast application booting and loading. The chips will enable much faster multi-tasking, web-browsing, application downloading and file transfers, as well as high-definition video capture and playback, and are highly responsive to running large-file gaming and productivity applications.

“With timely mass production of our ultra-fast eMMC PRO line-up offering a more than 10X performance increase over external memory cards, Samsung will accelerate the spread of high-end mobile devices as the market for devices with larger screens and more multimedia functionality expands even further,” said KyongMoo Mang, vice president of memory marketing. “We will continue to provide advanced mobile memory solutions that allow users to enjoy high definition, large-volume content seamlessly, as we also strengthen technological cooperation with mobile devices manufacturers.”

Samsung’s eMMC PRO memory chips, being produced in 16, 32 and 64GB versions, are based on Samsung 64Gb 10nm class NAND flash technology.

The new Samsung chips support the eMMC version 5.0 standard now nearing completion at JEDEC – the largest standards-setting body in the microelectronics industry.

In 32GB and 64GB densities, the new memory solution has a random read speed of 7000 IOPS (inputs/outputs per second), and a random write speed of 7000 IOPS (in cache on mode, without host overhead). In addition, these chips read sequentially at 250MB/s and write sequentially at 90MB/s.

As the fastest eMMC devices at more than 10 times the speed of a class 10 external memory card (which reads at 24MB/s and writes at 12MB/s), the new mobile memory greatly enhances the movement from one application to another in multitasking activities.

Samsung’s 16GB, 32GB and 64GB eMMC 5.0 devices come in 11.5x13mm packages, making them ideal for mobile devices where space on the printed circuit board is extremely limited.

In a season when their sales should be rising sharply, suppliers of large-sized liquid-crystal (LCD) panels instead are encountering weak demand growth in the third quarter, exacerbating the glut already plaguing the market.

Measured in terms of square meters, supply of large-sized LCDs is expected to exceed demand by 15.9 percent during the period from July through September, according to the latest report entitled “Oversupply to Continue Due to Weak Economy” from information and analytics provider IHS. This is up nearly 3 percentage points from the previous forecast of a 13.2 percent oversupply, as presented in the figure below.

While the glut will decline compared to the second quarter—as is normal during the pre-holiday season—the surplus remains at elevated levels.

“This is the time of the year when LCD panel makers usually are ramping up production to meet holiday demand for televisions, notebook PCs, tablets and other consumer-oriented electronics,” said Ricky Park, senior manager for large-area displays at IHS. “However, the display industry is confronting the prospect of weak sales growth and a lack of visibility into future demand trends. With a combination of flagging economic conditions and the end of a popular television incentive plan in China, large-sized LCD panel supply is expected to overshoot demand by a higher margin than previously predicted.”

IHS defines large-sized LCDs as panels that have a diagonal dimension of 7 inches or greater used in devices such as televisions, notebook PCs and monitors.

Demand dearth

Global large-sized LCD panel demand in terms of square meters is expected to rise by a tepid 6 percent in the third quarter compared to the second. In most years, growth is typically larger because of seasonal factors. Expansion in 2012, for instance, was in double-digit territory at more than 10 percent.

Meanwhile, production capacity utilization among large-sized LCD makers is on the rise, increasing to 84 percent in the third quarter, up from 79 percent in the second.

The combination of the weaker-than-normal increase in demand and the significant expansion in utilization will combine to inflate the excess supply to higher levels.

China’s challenge

For their part, Chinese television makers are experiencing swelling inventories because of weaker-than-expected sales. The companies are likely to reduce their sales targets for 2013 and are trimming panel orders for the second half of the year.

Although China continues to enjoy the strongest economic growth among the major world economies, signs of weakness abound as export growth has declined sharply, due to a stagnant global economic recovery, a stronger yuan, and the Chinese government’s efforts to stem currency speculation. Given the deterioration of its export industry and the sluggish global economy, China can no longer depend on exports to fuel its overall economic growth.

Furthermore, the Chinese government has terminated its subsidy program for energy-saving TVs that had been driving sales earlier this year. This will further reduce panel demand.

Researchers from the National Institute of Standards and Technology (NIST) and the University of North Carolina have demonstrated a new design for an instrument, a "instrumented nanoscale indenter," that makes sensitive measurements of the mechanical properties of thin films — ranging from auto body coatings to microelectronic devices — and biomaterials. The NIST instrument uses a unique technique for precisely measuring the depth of the indentation in a test surface with no contact of the surface other than the probe tip itself.

Nanoindenter head

Indenters have a long history in materials research. Johan August Brinell devised one of the first versions in 1900. The concept is to drop or ram something hard onto the test material and gauge the material’s hardness by the depth of the dent. This is fine for railway steel, but modern technology has brought more challenging measurements: the stiffness of micromechanical sensors used in auto airbags, the hardness of thin coatings on tool bits, the elasticity of thin biological membranes. These require precision measurements of depth in terms of nanometers and force in terms of micronewtons.

Instead of dents in metal, says NIST’s Douglas Smith, "We are trying to get the most accurate measurement possible of how far the indenter tip penetrates into the surface of the specimen, and how much force it took to push it in that far. We record this continuously. It’s called ‘instrumented indentation testing’."

A major challenge, Smith says, is that at the nanoscale you need to know exactly where the surface of the test specimen is relative to the indenter’s tip. Some commercial instruments do this by touching the surface with a reference part of the instrument that is a known distance from the tip, but this introduces additional problems. "For example, if you want to look at creep in polymer — which is one thing that our instrument is particularly good at—that reference point itself is going to be creeping into the polymer just under its own contact force. That’s an error you don’t know and can’t correct for," says Smith.

The NIST solution is a touchless surface detector that uses a pair of tiny quartz tuning forks — the sort used to keep time in most wrist watches. When the tuning forks get close to the test surface, the influence of the nearby mass changes their frequency — not much, but enough. The nanoindenter uses that frequency shift to "lock" the position of the indenter mechanism at a fixed distance from the test surface, but without exerting any detectable force on the surface itself.

"The only significant interaction we want is between the indenter and the specimen," says Smith, "or at least, to be constant and not deforming the surface. This is a significant improvement over the commercial instruments."

The NIST nanoindenter can apply forces up to 150 millinewtons, taking readings a thousand times a second, with an uncertainty lower than 2 micronewtons, and while measuring tip penetration up to 10 micrometers to within about 0.4nm. All of this in done in a way that can be traceably calibrated against basic SI units for force and displacement in a routine manner.

The instrument is well suited for high-precision measurements of hardness, elasticity and creep and similar properties for a wide range of materials, including often difficult to measure soft materials such as polymer films, says Smith, but one of its primary uses will be in the development of reference materials that can be used to calibrate other instrumented indenters. "There still are no NIST standard reference materials for this class of instruments because we wanted to have an instrument that was better than the commercial instruments for doing that," Smith explains.

Together with its partners STFC and Fraunhofer IIS, imec announced today that the European Commission has pledged to continue funding the Europractice IC services for another three years under the Seventh Framework Programme (FP7).

"The EU’s continued support of the Europractice IC services speaks to the value of our efforts to help get European ASIC (application specific integrated circuits)-based products to market quickly and cost effectively,” stated Carl Das, director of the Europractice IC service at imec. “This funding will enable us to continue to provide the best and most advanced solutions to European academia and research institutes, start-up companies and companies within small niche markets.”

Europractice IC service is internationally recognized as a leading service to universities and industry for design, development, prototyping and manufacturing of application specific integrated circuits (ASICs) on a cost-sharing basis. Today, about 500 universities, 150 research centers and more than 200 European companies have access to this service.

Europractice IC services offers dedicated training courses on design flows and methods in advanced technologies, and has negotiated low cost opportunities with the most popular industry-standard CAD vendors and foundries.  As such, academics and research centers have access to state-of-the-art CAD tools for training and non-commercial research, and to multi-project wafer (MPW) runs for prototyping and manufacturing.  Europractice IC services also supports companies in the assembly and testing phase. Over the next three years, the service will expand its offering from ASIC services to prototyping possibilities in MEMS and photonics-related technologies.

Compound Photonics announced an agreement with RFMD whereby Compound Photonics will purchase Europe’s largest gallium arsenide (GaAs) manufacturing facility in Newton Aycliffe, County Durham, England.

"Compound Photonics will soon release projector products for mobile devices that are three times brighter and smaller than current state of the art.  To achieve these next generation levels of performance we need to vertically integrate the design and manufacture of the entire light engine.  This acquisition will bring in-house the manufacturing capabilities for the lasers required to power these engines," said Jonathan A. Sachs, Ph.D., president and CEO of Compound Photonics. "The skilled and experienced people, the fab with its toolset, supply chain, mature processes, and a track record of high volume production are ready made for our laser production."

Compound Photonics will use the 53 acre site with its 50,000-square-foot GaAs wafer fab to produce green, red and infrared lasers. The addition of the systems, fabrication equipment, and research and development capabilities as well as the manufacturing team with experience supplying high volume components to leading mobile phone manufacturers  expands Compound Photonics capacity and flexibility to meet its aggressive growth plans.

The powerful, high efficiency, wavelength stabilized laser diodes will be used as illumination sources in miniature high definition 1080p projectors for smartphones, tablets and other mobile devices, as well as ultra high definition 4K projectors and automotive head up displays. Wavelength stabilized infrared lasers for emerging gesture recognition applications will also be manufactured using wafer scale production methods in Newton Aycliffe.

The Newton Aycliffe facility complements Compound Photonics’ 40,000 square-foot semiconductor processing facility in Phoenix, Arizona where it manufactures liquid crystal on silicon displays and optics systems for its laser projection light engines.

Terms of the transaction were not disclosed.

Rudolph Technologies, Inc., a provider of process characterization, photolithography equipment and software for the semiconductor, FPD, LED and solar industries, today released three new application-specific configurations of its industry-leading NSX 320 Automated Macro Defect Inspection System. The suite includes specially-designed configurations for wafer level packaging, 2.5D (interposer) and 3DICs using through-silicon via (TSV) as interconnects. The first NSX 320 Metrology System for wafer level packaging shipped in June to a major outsourced assembly and test (OSAT) facility in Asia.

“These new application-specific configurations of our established NSX 320 System are designed to address the emerging need for fast, precise three-dimensional (3D) measurements in the rapidly growing advanced packaging market sector,” said Rajiv Roy, vice president of business development and director of back-end marketing at Rudolph Technologies. “We have completed the integration of 3D measurement sensors, recently acquired from Tamar Technology, into the NSX System. Tamar’s sensor technology is well recognized and widely used, and integrating it into the NSX 320 System adds critical capability required for enabling advanced packaging applications such as copper pillar bumping and TSV.”

The NSX 320 wafer level packaging configuration is designed to measure film thickness (polymers, photoresist, glass), thin remaining silicon thickness (RST), surface topography, copper pillar height and solder bump height. The advanced wafer level packaging configuration adds measurements of the wafer profile (warp and bow), total stack thickness and thick/thin RST (bonded wafer before and after grind). The 3DIC configuration is capable of all the above measurements plus via depth, trench depth, bonded wafer TTV and adhesive layers.

Roy stated, “3DIC device volume is forecasted to grow to $38.4B by 2017, according to Yole Développement. Rudolph is positioned to address the growth requirements for wafer level packaging, as well as 2.5D and other advanced packaging technologies, with industry-proven metrology tools that offer superior speed and measurement solutions.”

IC Insights’ new 250-page Mid-Year Update to the 2013 McClean Report, which is slated to be released by the end of July, describes why a very clear distinction should be made between the IC market (i.e., consumption) in China and IC production within China.  Although China has been the largest individual market for ICs since 2005, it does not necessarily mean that large increases in IC production within China would immediately follow, or ever follow. IC production in China represented only 11.1 percent of its $81 billion IC market in 2012.  Moreover, IC Insights forecasts that this share will increase only about three percentage points to 14.4 percent in 2017.

China-based IC production is forecast to exhibit a very strong 2012-2017 CAGR of 17.6 percent.  However, considering that China-based IC production was only about $8.9 billion in 2012, this growth will come off a relatively small base.  In 2012, SK Hynix, TSMC, and Intel were the major foreign IC manufacturers that had significant IC production in China.  In fact, SK Hynix’ China fab had the most capacity of any of its fabs last year.  In 2012, Intel continued to ramp-up its 300mm fab in Dalian, China (it started production in late October 2010), which is expected to give a noticeable boost to the China-based IC production figures over the next few years.  This fab currently has an installed capacity of 30,000 300mm wafers per month with a maximum capacity of 52,000 wafers per month.

In early 2012, Samsung gained approval from the South Korean government to construct a 300mm IC fabrication facility to produce NAND flash memory in Xian, China.  Samsung started construction of the fab in September of 2012 with production set to begin in the first half of 2014.  The company expects to invest $2.3 billion in the first phase of the fab with $7.0 billion budgeted in total.  This facility is targeting NAND flash production using a 10-19nm feature size process technology.

If China-based IC production rises to $20.0 billion in 2017 as forecast, it would still represent only 5.6 percent of the total forecasted 2017 worldwide IC market of $359.1 billion.  Even after adding a significant “markup” to many of the Chinese producers’ IC sales figures (since many of the Chinese IC producers are foundries that sell their ICs to companies that re-sell these products to the electronic system producers), China-based IC production would still represent less than 10 percent of the global IC market in 2017.

China's IC producers

Historically, the lack of consistent intellectual property protection has been a major deterrent for foreign firms seeking to establish state-of-the-art IC fabrication facilities in China.  The lack of intellectual property protection is also a reason many large fabless IC suppliers (e.g., Qualcomm, Broadcom, etc.) have not brought leading-edge IC designs into China for the indigenous Chinese IC foundries to manufacture.  It should also be noted that, thus far, Chinese IC foundries have also been unable to offer large amounts of IC production using leading-edge feature sizes.

IC Insights believes that the future size of the IC production base in China is more dependent upon whether foreign companies continue to locate, or re-locate, IC fabrication facilities in China than on the success of indigenous Chinese IC producers (e.g., SMIC, Hua Hong Grace, etc.).  As a result, IC Insights forecasts that at least 70 percent of IC production in China in 2017 will come from foreign companies such as SK Hynix, TSMC, Intel, and Samsung.

Ulsan National Institute of Science and Technology (UNIST) researchers report considerable improvement in device performance of polymer-based optoelectronic devices. Published in Nature Photonics, the new plasmonic material, can be applied to both polymer light-emitting diodes (PLEDs) and polymer solar cells (PSCs), with world-record high performance, through a simple and cheap process.

The contrary demands of these devices mean that there are few metal nanoparticles that can enhance performance in PLEDs and PSCs at the same time.

Most semiconducting optoelectronic devices (OEDs), including photodiodes, solar cells, light emitting diodes (LEDs), and semiconductor lasers, are based on inorganic materials. Examples include gallium nitride for light-emitting diodes and silicon for solar cells.

Due to the limited availability of raw materials and the complex processing required to manufacture OEDs based on inorganic materials, the cost of device fabrication is increasing. There is great interest in thin-film OEDs that are made from alternative semiconductors.

Among these materials, organic semiconductors have received much attention for use in next-generation OEDs because of the potential for low-cost and large-area fabrication using solution processing.

Despite extensive efforts to develop new materials and device architectures enhancing the performance of these devices, further improvements in efficiency are needed, before there can be widespread use and commercialization of these technologies.

The material prepared by the UNIST research team is easy to synthesize with basic equipment and has low-temperature solution processability. This low-temperature solution processability enables roll-to-roll mass production techniques and is suitable for printed electronic devices.

“Our work is significant also because it anticipates the realization of electrically driven laser devices by utilizing carbon dot-supported silver nanoparticles (CD-Ag NPs) as plasmonic materials.” says said Prof. Byeong-Su Kim. “The material allows significant radiative emission and additional light absorption, leading to remarkably enhanced current efficiency.”

Surface Plasmon resonance is an electro-magnetic wave propagating along the surface of a thin metal layer and the collective oscillation of electrons in a solid or liquid stimulated by incident light. SPR is the basis of many standard tools for measuring adsorption of materials onto planar metal (typically gold and silver) surfaces or onto the surface of metal nanoparticles.

The team demonstrated efficient PLEDs and PSCs using surface Plasmon resonance enhancement with CD-Ag NPs. The PLEDs achieved a remarkably high current efficiency (from 11.65 to 27.16 cd A-1) and luminous efficiency (LE) (from 6.33 to 18.54 lm W-1).

PSCs produced in this way showed enhanced power conversion efficiency (PCE) (from 7.53 to 8.31 percent) and internal quantum efficiency (IQE) (from 91 to 99 percent at 460nm). The LE (18.54 lm W-1) and IQE (99 percent) are among the highest values reported to date in fluorescent PLEDs and PSCs, respectively.

“These significant improvements in device efficiency demonstrate that surface Plasmon resonance materials constitute a versatile and effective route for achieving high performance polymer LEDs and polymer solar cells,” said Prof. Jin Young Kim. “This approach shows promise as a route for the realization of electrically driven polymer lasers.”

The fellow researchers include Hyosung Choi, Seo-Jin Ko, Yuri Choi, Taehyo Kim, Boram Lee, and Prof. Myung Hoon Song from UNIST, and researchers from Chungnam National University, Pusan National University, and Gwangju Institute of Science and Technology.

This research was supported by a WCU (World Class University) program through the Korea Science and Engineering Foundation funded by the Ministry of Education, Science and Technology, the National Research Foundation of Korea Grant, the Korea Healthcare technology R&D Project, the Ministry of Health & Welfare, Korea and the International Cooperation of the Korea Institute of Energy Technology Evaluation and Planning (KETEP) grant funded by the Korean government Ministry of Knowledge Economy.

 

Steffen_SchulzeSteffen Schulze is the director of Marketing, mask Data Preparation and Platform Applications at Mentor Graphics, serving customers in mask and IC manufacturing.

Who knew that mask process correction (MPC) would again become necessary for the manufacturing of deep ultraviolet (DUV) photomasks? MPC can be called a seasoned technology; it has always been an integral part of the e-beam mask writers to cope with the e-beam proximity effects, which can extend up to 15um of the exposure point. In addition, the mask house has been compensating for process-induced biases. Residual errors were always absorbed by the models created to describe the wafer process. Range and general behavior proved to be sufficient to capture the effects and secure the accuracy requirements for the wafer lithography.

At the 40nm node, more complex techniques were considered to cope with significant proximity signatures induced by the dry etch process and the realization that forward scattering in e-beam exposure, which was not accounted for in the machine-based correction, had a significant impact especially in 2D configurations. A number of commercial tools were made available at the time but a broad adoption was thwarted by the introduction of new mask substrates and the associated etch process – OMOG blanks provided for a thinner masking layer and enabled an etch process with a fairly flat signature. The MPC suppliers moved on to the EUV technology domain where a new and thicker substrate with a more complex etch process showed stronger signatures again, along with new effects of different ranges.

So what is changing now? At the 10nm node we are still dependent on the 193nm lithography. And while the wafer resolution is tackled with pitch splitting, the accuracy requirements continue to get tighter – tolerances far below 1nm are required for the wafer model. Phase shift masks are considered with a stack that is higher and displays stronger signatures again. In addition, scatter bars of varying sizes but below 100nm at the mask fall again into the size range with significant linearity effects.

So no wonder that the mask and wafer lithography communities are turning to mask process correction technology again. Wafer models have expanded to a more comprehensive description of the 3D nature of the mask (stack height and width ratio are approaching 1). A recent study presented at SPIE (Sturtevant, et al http://dx.doi.org/10.1117/12.2013748) shows that systematic errors on the mask contribute more than 0.5nm RMS to the error budget.  Figure 1 shows the process biases present in an uncorrected mask for various feature types – dense and isolated lines and spaces. Figure 2 shows how strongly the variability in mask parameters – here stack slope and corner rounding – can influence the model accuracy for a matching wafer model.

Figure 1 copy
Figure 1. Mask CD bias (actual-target) 4X for four different pattern types and both horizontal and vertical orientations. Click to view full screen.
Figure 2 copy
Figure 2 .  Impact of changing the MoSi slope (left) and corner rounding (right) on CTR RMS error at nominal condition and through focus. Click to view full screen.

The authors showed that the proper representation of the mask to a wafer model can improve the modeling accuracy significantly. For example, even an approximation of the corner rounding by a 45deg bevel can have a significant impact. Likewise considering the residual linearity and proximity errors improves the modeling accuracy. Figure 3 shows the comparison of residual errors for a variety of test structure in the uncorrected stage and when simulated with the proper mask model. The latter one can largely compensate the observed errors.

Figure 3
Figure 3. Mask CD error (4X) versus target and residual mask process simulation error. Click to view full screen.

The methods to properly account for the effects during the simulation are anchored in mask processing technology. These results have opened the discussion as to not only describing the mask but also correcting it. The above mentioned study revealed a number of additional parameters that are generally assumed to be stable but fundamentally reveal a high sensitivity of the lithomodel to any variation –specifically the material properties and the edge slope or a substrate over-etch.  From these studies and observations one can conclude that mask process characterization and correction will be of increasing importance for meeting the tolerance requirements for wafer modeling and processing – initially by proper description of its residual errors for consideration in the wafer model but subsequently also by correction. The technology is available for quite some time and ready to be used – unless the materials and the process community come through again.

Read other Mentor Graphics blog posts:

Innovations in computational lithography for 20nm

Looking for an integrated tape-out flow