Category Archives: SST

Alchimer, S.A. today announced a collaboration with the French research institute CEA-Leti to evaluate and implement Alchimer’s wet deposition processes for 300mm high-volume manufacturing. The project will evaluate Alchimer’s Electrografting (eG) and Chemicalgrafting (cG) processes for isolation, barrier and seed layers. When combined, Alchimer’s wet deposition processes have been demonstrated to achieve 20:1 aspect ratio through silicon vias (TSVs) due to their ability to coat conformally regardless of via topography, diameter or depth.

3D integration is moving towards a "via middle" approach where TSVs are formed after front-end processes, but prior to stacking.  Several applications are in the development phase, leading to constraints and different specifications for TSVs. Alchimer’s technology shows the potential to break through existing barriers to achieve high aspect ratio TSVs. This collaboration will evaluate the potential of its technology and its suitability for high-volume manufacturing.

"Current techniques, such as PECVD isolation and iPVD metallization, have performance limitations that are limiting achievable TSVs to 10:1 aspect ratios," said Bruno Morel, CEO of Alchimer. "Our 3D TSV products have unequivocally demonstrated their ability to deliver 20:1 aspect ratios at a significantly reduced cost as compared to current approaches. Now it is critical to validate the products’ full potential for 300mm high-volume manufacturing as well as to study their compatibility with the overall 3D integration process. Leti’s leading 3D expertise and world-class infrastructure will allow us to do that.

"Collaborating with Alchimer fits perfectly our strategy of delivering innovative solutions to industry," added Fabrice Geiger, head of Leti’s Silicon Technology Division. "Alchimer’s eG technology is a promising, cost-effective and breakthrough solution to address the challenges of future 3D TSV integration. Through this collaboration, Alchimer will have access to Leti’s expertise in the domain of 3D TSV integration and its world-class 300mm 3D platform capabilities."

eG is based on surface chemistry formulations and processes. It is applied to conductive and semiconductive surfaces and enables self-oriented growth of thin coatings of various materials, initiated by in-situ chemical reactions between specific precursor molecules and the surface. This process achieves a combination of conformality, step coverage and purity that cannot be matched by dry processes.

Imec announced on Monday a cryogenic etching method that protects the surface of porous ultralow-k dielectrics against excessive plasma induced damages.

As semiconductor technology scales below the 20nm node, the capacitance increases between nearby conductive portions of high-density integrated circuits, resulting in loss of speed and cross-talk of the device. To control the increase in capacitance in deeply-scaled devices, insulating layers of porous low-k dielectrics are integrated through plasma etching. However, plasma etching exposes the dielectrics to active plasma radicals that penetrate deeply into the porous substrate, which then react and change the composition of the dielectric.

To bypass such damages, imec developed a new cryogenic etching method. By applying very low (cryogenic) temperatures during etching, a condensation of etch products in the pores of the low-k material, results in a protection of the dielectrics’ surface. Imec demonstrated the method on a porous organosilicate (OSG) film. The results showed that no carbon depletion occurred when the wafer temperature remained below a certain critical level during plasma etching.

“Our cryogenic etch method solves a key issue to further advancing scaling limits. It overcomes the disadvantages of current methods used to reduce plasma induced damage, such as dielectric etch at regular temperatures or low-k repair or high temperature pore stuffing, and it enables sub k=2.0 materials for integration,” stated Zsolt Tokei, program director interconnect at imec. “Our method is a true solution to further drive the development of next-generation, deeply-scaled technologies.”

Imec exhibits at SEMICON West, July 9-11, 2013. To learn more about imec and its new cryogenic etching method, please visit booth 1741, South hall.

 

Graph: Etching at cryogenic temperature results in targeted k-value

EV Group (EVG), a  supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today introduced the latest version of its EVG40NT automated measurement system, which is designed to work in concert with the company’s GEMINI FB fusion wafer bonding system to support the manufacture of next-generation 3D-integrated CMOS image sensors.  The enhanced EVG40NT measures wafer-to-wafer alignment accuracy to within 40nm (3 sigma), while its seamless software integration with the GEMINI FB provides a closed-loop fusion bonding control system that enables the manufacture of ultra-fine-pitch (less than two micron) through-silicon vias (TSVs).  These tighter specifications are necessary for enabling the production of 3D-integrated image sensors, and pave the way for accelerating 3D-integration with other device types, such as stacked memory.

"EV Group’s GEMINI FB fusion wafer bonding platform is the de facto industry standard for CMOS image sensor production, and already leads the industry in wafer-to-wafer alignment accuracy due to our proprietary SmartView alignment technology," stated Dr. Thorsten Matthias, business development director at EV Group.  "The integration of GEMINI FB with the enhanced EVG40NT brings statistical process control and alignment accuracy to a whole new level, and pushes 3D-IC manufacturing to new limits.  High-precision manufacturing requires accurate metrology that is seamlessly integrated into the process to enable real-time monitoring and fast corrective action.  In the case of wafer bonding, measuring and mapping each die gives valuable insight into local stress variations created during upstream processes, which can cause distortions and local misalignments further downstream."

Fusion wafer bonding is ideally suited for 3D-integrated image sensors and other stacked devices because it is a room-temperature bonding process, which eliminates misalignment due to thermal expansion mismatch between the wafers.  Having the ability to inspect the quality of the wafer bond and measure alignment accuracy prior to the final annealing step provides an easy rework path, thereby enabling 100-percent yield for wafer stacking.  The GEMINI FB platform combines EVG’s LowTemp plasma activation technology, wafer cleaning, SmartView wafer-to-wafer alignment and fusion wafer bonding in a single fully automated high-volume-manufacturing system.  The EVG40NT performs highly accurate, non-destructive, top-to-bottom side alignment accuracy measurements on double-sided structured wafers or bond interfaces, as well as critical dimension and box-in-box measurements of single and double-sided structured wafers.

"Next-generation image sensors are the technological frontrunners for 3D-IC manufacturing technology," according to Hermann Waltl, executive sales and customer support director at EV Group.  "High-density TSV arrays, sub-micron-diameter TSVs and ultra-thin wafers have all been successfully transferred into high-volume image sensor manufacturing.  Now that adoption of wafer-to-wafer 3D stacking for image sensors is well underway, we expect to see 3D-integration follow very soon for other devices such as stacked memory."

Media and analysts interested in learning more about EVG’s latest developments in wafer bonding and other processing solutions are invited to visit the company’s booth #819 in the South Hall of the Moscone Convention Center in San Francisco at the SEMICON West show this week, as well as attend the company’s presentations during the show’s technical program.  Markus Wimplinger, corporate technology development and IP director of EV Group, will present "High Resolution In-line Metrology Module for High-Volume Temporary Bonding Applications" at the SEMATECH Workshop on 3D Interconnect Metrology on Wednesday, July 10 from 11:20 – 11:40 a.m. at the San Francisco Marriott Marquis.  In addition, Dr. Thorsten Matthias, business development director at EV Group, will present "From Sensor Fusion to System Fusion" at the TechXPOT session "MEMS and Sensor Packaging for the Internet of Things" on Thursday, July 11 from 12:10 – 12:30 p.m. in the Moscone North Hall.

Boston University filed a lawsuit against Apple Inc. and several other big tech companies over an alleged patent infringement, a thin film semiconductor technology that they claim was developed by one of their professors.

The suit, which was filed on Tuesday in a federal district court in Boston, the school claims that Apple violated its patent on “highly insulating monocrystalline gallium nitride thin films.” BU says this technology is being used in products such as the iPhone, iPad and MacBook Air.

Boston University names Theodore Moustakas, a professor of electrical and computer engineering, as the inventor of the technology, and claims that the patent for the semiconductor film was issued in 1997.

The school is seeking financial compensation that will be determined by a jury, if the case goes to trial. However, the patent on Moustakas’ technology expires in 2015, leaving experts to speculate on what little impact a Boston University victory could have on Apple’s future.

Neither party has commented on the case.

Toshiba Corporation today announced that it will expand its No. 5 semiconductor fabrication facility (Fab 5) at Yokkaichi Operations in Mie, Japan, to secure manufacturing space for NAND flash memories fabricated with next generation process technology and for future 3D memories. Fab 5 second phase construction will start at the end of August this year and be completed in summer next year. Decisions on equipment investment and production will reflect market trends.

Yokkaichi Operations currently has three Fabs mass producing NAND flash memory, including Fab 5 phase 1. Fab 5’s construction was planned around two phases, the first of which went into operation in July 2011. After giving careful consideration to the balance of product supply and demand, and noting a recovery driven by growing demand for smartphones, tablets, SSD for enterprise servers and other new applications, Toshiba now anticipates further medium- to long-term market expansion and recognizes that the time is right to expand Fab 5.

In addition to securing capacity for future generations of NAND Flash memory fabricated with the company’s latest process technology, Toshiba will also use Fab 5 phase 2 for production of 3D memories that are expected to find growing application in coming years. The extension will allow the company to boost competitiveness and enhance its responsiveness to technology advances and market demands.

Fab 5 phase 2 will have an automated product transportation system and quake-absorbing structure and will be designed to minimize environmental loads. Deployment of LED lighting and up-to-date energy-saving production facilities, along with full and effective use of waste heat, are expected to cut CO2 emissions by 13 percent compared with Fab 4.

Going forward, Toshiba will expand its memory business and boost competitiveness by timely investments, leadership in advanced process technology and the development of new generation memories that answer market needs.

Following last week’s formal announcement from Governor Cuomo of the formation of the Facility 450 Consortium (F450C), ten leading nanoelectronics facility companies from around the world will collaborate at CNSE to lead the global effort to design and build the next-generation 450mm computer chip fabrication facilities. At the semiconductor industry’s annual SEMICON West tradeshow, taking place at the Moscone Center in San Francisco, CA on July 9-11, the F450C will host its first public panel discussion about facility and infrastructure solutions for the transition to 450mm wafer fabrication.

Who: Members of the Facility 450 Consortium (F450C)

What: Panel entitled: The 450mm Facility; F450C’s Parallel Pathway

When: 4-5 pm on Tuesday, July 9

Where: The Impress Lounge, located at the B Bar above Moscone’s North

Why: Beyond the manufacturing hurdles that 450mm wafer processing brings, next generation fabs present new challenges with respect to the design of the facilities, substrate handling, tool connection, chemical distribution, water and electrical systems and many other areas. Where the G450C provides leadership in the area of 450mm equipment and process technologies, the goal of the F450C is to develop facility and infrastructure solutions essential to the transition to 450mm wafer fabrication.

On the Agenda:

  • Allen Ware, M+W Group & F450C: An Introduction to the F450C
  • William Corbin, G450C: Design to Requirement at the Utility Level
  • Adrienne Pierce, Edwards Vacuum: The ŒGreen Pump Strategy
  • Lothar Till, Ovivo: Water Use at 450mm

To register for the event please RSVP to [email protected]

The Facilities 450mm Consortium (F450C) is a first-of-its-kind partnership at SUNY’s College of Nanoscale Science and Engineering (CNSE) that is leading the global effort to design and build next-generation 450mm computer chip fabrication facilities. The collaboration includes 10 of the world¹s leading nanoelectronics facility companies, including Air Liquide, CH2M HILL, CS Clean Systems, Ceres Technologies, Edwards, Haws Corporation, Mega Fluid Systems, M+W Group, Ovivo, and Swagelok. Members of F450C are working closely with the Global 450mm Consortium (G450C), as announced by New York Governor Andrew M. Cuomo, to identify viable solutions required for 450mm high-volume facility construction, with initial focus areas to include reducing tool installation cost and duration, and improving facility sustainability.

BOE Technology Group announced that it has placed significant orders for advanced Gen 8.5 and Gen 5.5 display production equipment from Applied Materials for use in multiple facilities. BOE selected these systems because of their ability to produce faster, smaller thin film transistors for the next era of high definition televisions and high pixel density displays for future mobile devices. Applied Materials is providing a full suite of advanced deposition equipment including the leading-edge Applied  PiVot PVD  and PECVD systems, which are capable of supporting critical new technologies such as metal oxide and LTPS.

"BOE continues to execute on its manufacturing capacity and technology initiatives and appreciates the strong cooperative relationship with Applied Materials in developing and creating value in support of the world’s largest TV and mobile display market," said Mr. Liu Xiaodong, executive vice president, chief operation officer of BOE. "Over the past year we have achieved key high-volume Gen 8.5 production and yield milestones, which demonstrate our leadership in growing this strategic industry in China. We are pleased to work with Applied Materials to implement the new technologies needed to continue meeting the high quality, high performance screens consumers have come to expect and demand."

"Applied Materials is delighted to play an important role in BOE’s growth strategy and is committed to providing the leading-edge technologies to enable its continued success," said Ali Salehpour, group vice president, general manager, Applied Materials Energy and Environmental Solutions and Display Business Group. "There is a major shift taking place in the display industry toward adopting new materials, and BOE selecting Applied Materials equipment validates the technology differentiation and productivity gains we provide to our customers. Together, BOE and Applied are enabling consumers to experience displays with world-class color, clarity and brightness."

The Applied PiVot PVD and PECVD systems selected by BOE provide a high-performance, cost-effective path to manufacturing stunning high resolution amorphous silicon, metal oxide and LTPS displays.  These systems can significantly increase production and achieve the same economies of scale that enabled the cost of LCD TVs to fall by more than 95 percent over the past decade and brought large-area LCD televisions within the reach of billions of consumers around the globe.

Applied Materials, Inc. provides equipment, services and software to enable the manufacture of advanced semiconductor, flat panel display and solar photovoltaic products. Our technologies help make innovations like smartphones, flat screen TVs and solar panels more affordable and accessible to consumers and businesses around the world.

ROFIN, a manufacturer of industrial lasers and laser systems enters the semiconductor market with a turnkey solution for front-end-of-line (FEOL) processing. The new laser wafer processing system Waferlase 200/300/450, is a fully automated modular platform comprising a market-leading handling system for (ultra) thin semiconductor wafers and a choice of laser processing modules, depending on the type of application. The Waferlase 200/300/450 product family starts with solutions for IGBT laser annealing and debris-free wafer marking.

Leading ultra-thin wafer handling technology

ROFIN integrated top-notch wafer handling technology to provide precise, non-contact transportation of ultra-thin wafers, even with considerable warpage and bow. The system comes with two or more cassette ports for Open Cassette or FOUP wafer carrier systems. Integrated scanners detect the exact position of the wafer in its carrier. The comprehensive but easy-to-use system software controls slot allocation, wafer warpage measurement, wafer location as well as wafer ID detection, and would even change the pick-and-place sequence automatically in case of a wafer damage threat, e.g. due to extensive or opposite bowing of neighboring wafers. A high-end dual-arm robot takes care of wafer loading and unloading. The pre-aligner module centers and aligns the wafer. A “vacuum handshake” between end-effector and pre-aligner, including wafer safeguard, secures damage-free handling of the wafer back side. Thus, high-end technology and sophisticated software control integrated in ROFIN’s Waferlase 200/300/450 guarantees highest throughput at negligible wafer breakage rates.

IGBT laser annealing

The Insulated Gate Bipolar Transistor (IGBT) market is constantly growing because of significant advantages IGBTs offer compared to other transistor devices such as high voltage capability, low ON-resistance, ease of drive, fast switching speeds, robustness, etc.

One of the key factors contributing to this market growth is the increasing demand in automotive and industrial applications, including renewable energy, communications, medical, lighting and transportation.

IGBTs are manufactured on mechanically thinned wafers with a typical thickness of 100μm or less. In order to establish a field stop and/or emitter layer on the rear side of the wafer, deep-implanted doping elements (like phosphorous or boron) have to be activated through a high-temperature annealing process towards the end of the FEOL process chain. Very often, the sensitive devices on the wafer front side are protected by an attached tape. Due to low damage temperatures of the tape, the heat-sensitivity of the front side devices, as well as a non-uniform heat distribution in the processing chamber, conventional oven activation is characterized by low activation levels and rates. ROFIN’s laser annealing process has been developed to overcome these issues and to provide significantly higher process stability and yield at competitive costs/wafer levels. Laser annealing deep-activates the dopants and simultaneously prevents damage to the wafer front side and the protection tape. The laser allows for precise depth control of the field stop and/or emitter layer activation in the range of up to 2μm. With activation rates exceeding 90 percent, ROFIN’s IGBT laser annealing solution is far superior to conventional methods.

Wafer marking

ROFIN’s Waferlaser 200/300/450 systems produce traceable markings on transparent, semitransparent and opaque wafer materials. Two methods – hard and debris-free marking – are used which differ in terms of process, depth and location of the mark. Debris-free marking in clean-room environment is achieved solely by melting of the silicon wafer surface.

ROFIN’s new patent-pending marking technology allows the user to precisely control the marking depth ranging from less than 1μm to 7μm. The debris-free marking process uses a tailor-made IC–marking laser source with 532nm wavelength. This dedicated solution achieves high contrast with excellent performance at small character heights.

SEMI today announced that Ajit Manocha, CEO of GLOBALFOUNDRIES, has been selected to receive the “SEMI Outstanding EHS Achievement Award — Inspired by Akira Inoue.” The Environment, Health and Safety (EHS) Award is sponsored by SEMI and will be presented on July 9 at 9:00am during the SEMICON West 2013 Opening Keynote and Ceremonies in San Francisco.

“We are pleased to present this award to Ajit Manocha for his outstanding contribution and commitment to EHS issues," said Denny McGuirk, president and CEO of SEMI.  “Ajit joins a distinguished group of semiconductor executives who have been honored by our industry for notable EHS achievement and leadership.”

“Excellence in Environment, Health and Safety is not only a mandate that we set for ourselves, but a fundamental expectation of our customers and the communities where we operate,” Manocha said. “Corporate responsibility is fundamental to our culture and our value proposition to our customers, the communities in which we live and do business, and our full range of global stakeholders.”

Manocha heads GLOBALFOUNDRIES Executive Stewards Council (ESC), the leadership forum for strategic direction and accountability for risk management, corporate responsibility and sustainability.  Manocha’s leadership has resulted in significant EHS achievements at GLOBALFOUNDRIES. Those cited by the Award committee in the selection of Manocha include:

  • Zero-Incident Safety Culture — GLOBALFOUNDRIES safety goal is to continually reduce all injuries and Manocha continually challenged the EHS and project management teams to achieve zero incidents. For example, Manocha ensured that there was a strong focus on safety metrics in the executive project reviews of the new Fab 8 in Malta, New York. GLOBALFOUNDRIES’ Singapore Fabs all received “Silver Awards” for Health and Safety presented by the Workplace Safety and Health Council and supported by the Singapore Ministry of Manpower.
  • Commitment to Eco-Efficiency in Foundry Operations — In 2012, GLOBALFOUNDRIES set corporate environmental goals to reduce GHG emissions 40 percent by 2015, electricity consumption 35 percent by 2015 and water consumption 10 percent by 2015, all normalized to a manufacturing index and compared to 2010.  Fab 8 incorporates multiple energy efficiency measures, waste heat recovery, and “idle mode” for abatement systems and vacuum pumps. Fab 1 in Dresden is powered by two energy-efficient tri-generation power plants that provide electricity, heating and cooling to fab operations, GLOBALFOUNDRIES’ Singapore utilizes reclaimed NEWater for incoming supply and achieved an energy reduction of 50 GWh in 2012, with a 2013 goal of a further 57 GWh reduction.
  • WSC Commitment to Best Practices for Perfluoro-Compound (PFC) Reduction — At the 2012 annual CEO meeting of the World Semiconductor Council (WSC), Manocha led the discussion of EHS topics, urging his fellow CEOs to take action to protect the environment, conserve resources, and achieve the WSC’s PFC reduction goal. GLOBALFOUNDRIES’ newest U.S. fab, Fab 8, meets the WSC Best Practice commitment for PFC emission reduction, and Fab 1 has incorporated best practices for PFC reduction since 1999.
  • WSC Commitment to a “Conflict-Free Supply Chain” — At the 2013 WSC meeting, Manocha  championed a “Conflict-free Supply Chain” policy to address concerns related to sourcing tantalum, tungsten, tin and gold from “conflict regions” of the Democratic Republic of Congo and adjoining countries. The WSC subsequently adopted such a policy. For its part, GLOBALFOUNDRIES has already met customer requests for “Tantalum Conflict-free” products in 2012.

In addition to receiving the EHS Award at SEMICON West, Manocha will deliver the Opening Keynote for the event on July 9 at 9:00am at Moscone Center (Esplanade Hall, Keynote Stage) in San Francisco, Calif.  For more information about SEMICON West — including registration and keynote attendance —   visit http://www.semiconwest.org.

The “Outstanding EHS Achievement Award — Inspired by Akira Inoue” is sponsored by the EHS Division of SEMI. The award is named after the late Akira Inoue, past president of Tokyo Electron Limited and a strong advocate of EHS. Inoue also served on the SEMI Board of Directors. The award recognizes individuals in industry and academia who have made significant contributions by exercising leadership or demonstrating innovation in the development of processes, products or materials that reduce EHS impacts during semiconductor manufacturing.

Past recipients of the SEMI EHS Akira Inoue Award include: Richard Templeton (president and CEO, Texas Instruments), Atsutoshi Nishida (president and CEO, Toshiba), Dr. Jong-Kap Kim (chairman and CEO, Hynix Semiconductor), Dr. Morris Chang (chairman and CEO, TSMC) and other prominent industry leaders.

 

 

Since 2008, the majority of integrated circuit production has taken place on 300mm wafers.  In terms of surface area shipped (i.e., on a normalized 200mm-equivalent wafer basis), 300mm wafers represented 56 percent of worldwide installed capacity in December 2012.  Production using 300mm wafers is forecast to steadily increase and reach 70.4 percent in 2017, according to IC Insights’ Global Wafer Capacity 2013 report (see figure).

300mm wafers

For the most part, 300mm fabs are, and will continue to be, limited to production of high-volume, commodity-type devices like DRAMs and flash memories, and very recently image sensors and power management devices; complex logic and microcomponent ICs with large die sizes; and products manufactured by foundries, which can fill a 300mm fab by combining wafer orders from many sources.

The list of companies with the most 300mm wafer capacity includes DRAM and flash memory suppliers like Samsung, SK Hynix, Toshiba, Micron, Elpida, and Nanya; the industry’s biggest IC manufacturer and dominant MPU supplier Intel; and two of the world’s largest pure-play foundries TSMC and GlobalFoundries.  These companies offer the types of ICs that benefit most from using the largest wafer size available to best amortize the manufacturing cost per die.

It is interesting to point out that when (or if) the pending acquisition of Elpida by Micron goes through as expected, the merged company will have the industry’s second-largest share of 300mm wafer fabrication capacity, trailing only fellow memory chip manufacturer Samsung.

Meanwhile, the share of the industry’s monthly wafer capacity represented by 200mm wafers is expected to drop from 32 percent in December 2012 to 21 percent in December 2017, as seen in the figure. Fabs running 200mm wafers will continue to be profitable for many more years and be used to fabricate numerous types of ICs, such as specialty memories, image sensors, display drivers, microcontrollers, analog products, and MEMS-based devices.  Such devices are certainly practical in fully depreciated 200mm fabs that were formerly used in making devices now produced on 300mm wafers.

A significant trend with regard to the industry’s IC manufacturing base, and a perhaps worrisome one from the perspective of companies that supply equipment and materials to chip makers, is that as the industry moves IC fabrication onto larger wafers in bigger fabs, the group of IC manufacturers continues to shrink in number.  There are about 61 percent fewer companies that own and operate 300mm wafer fabs than 200mm fabs.  The distribution of worldwide 300mm wafer capacity among those manufacturers is very top-heavy.  Essentially, there are only about 15 companies that comprise the entire future total available market (TAM) for leading-edge IC fabrication equipment and materials, according to the Global Wafer Capacity 2013 report.  When 450mm wafer fabrication technology comes into existence, this manufacturer group is predicted to shrink even further to a maximum of just 10 companies, and a few of those are questionable.  Despite growing momentum, IC Insights expects that 450mm wafer capacity will account for only one-tenth of a percent of global IC capacity in December 2017.