Category Archives: SST

Inside the Hybrid Memory Cube

September 18, 2013

The HMC provides a breakthrough solution that delivers unmatched performance with the utmost reliability.

Since the beginning of the computing era, memory technology has struggled to keep pace with CPUs. In the mid 1970s, CPU design and semiconductor manufacturing processes began to advance rapidly. CPUs have used these advances to increase core clock frequencies and transistor counts. Conversely, DRAM manufacturers have primarily used the advancements in process technology to rapidly and consistently scale DRAM capacity. But as more transistors were added to systems to increase performance, the memory industry was unable to keep pace in terms of designing memory systems capable of supporting these new architectures. In fact, the number of memory controllers per core decreased with each passing generation, increasing the burden on memory systems.

To address this challenge, in 2006 Micron tasked internal teams to look beyond memory performance. Their goal was to consider overall system-level requirements, with the goal of creating a balanced architecture for higher system level performance with more capable memory and I/O systems. The Hybrid Memory Cube (HMC), which blends the best of logic and DRAM processes into a heterogeneous 3D package, is the result of this effort. At its foundation is a small logic layer that sits below vertical stacks of DRAM die connected by through-silicon -vias (TSVs), as depicted in FIGURE 1. An energy-optimized DRAM array provides access to memory bits via the internal logic layer and TSV – resulting in an intelligent memory device, optimized for performance and efficiency.

By placing intelligent memory on the same substrate as the processing unit, each system can do what it’s designed to do more efficiently than previous technologies. Specifically, processors can make use of all of their computational capability without being limited by the memory channel. The logic die, with high-performance transistors, is responsible for DRAM sequencing, refresh, data routing, error correction, and high-speed interconnect to the host. HMC’s abstracted memory decouples the memory interface from the underlying memory technology and allows memory systems with different characteristics to use a common interface. Memory abstraction insulates designers from the difficult parts of memory control, such as error correction, resiliency and refresh, while allowing them to take advantage of memory features such as performance and non-volatility. Because HMC supports up to 160 GB/s of sustained memory bandwidth, the biggest question becomes, “How fast do you want to run the interface?”

The HMC Consortium
A radically new technology like HMC requires a broad ecosystem of support for mainstream adoption. To address this challenge, Micron, Samsung, Altera, Open-Silicon, and Xilinx, collaborated to form the HMC Consortium (HMCC), which was officially launched in October, 2011. The Consortium’s goals included pulling together a wide range of OEMs, enablers, and tool vendors to work together to define an industry-adoptable serial interface specification for HMC. The consortium delivered on this goal within 17 months and introduced the world’s first HMC interface and protocol specification in April 2013.
The specification provides a short-reach (SR), very short-reach (VSR), and ultra short-reach (USR) interconnection across physical layers (PHYs) for applications requiring tightly coupled or close proximity memory support for FPGAs, ASICs and ASSPs, such as high-performance networking and computing along with test and measurement equipment.

FIGURE 1. The HMC employs a small logic layer that sits below vertical stacks of DRAM die connected by through-silicon-vias (TSVs).

The next goal for the consortium is to develop a second set of standards designed to increase data rate speeds. This next specification, which is expected to gain consortium agreement by 1Q14, shows SR speeds improving from 15 Gb/s to 28 Gb/s and VSR/USR interconnection speeds increasing from 10 to 15–28 Gb/s.

Architecture and Performance

Other elements that separate HMC from traditional memories include raw performance, simplified board routing, and unmatched RAS features. Unique DRAM within the HMC device are designed to support sixteen individual and self-supporting vaults. Each vault delivers 10 GB/s of sustained memory bandwidth for an aggregate cube bandwidth of 160 GB/s. Within each vault there are two banks per DRAM layer for a total of 128 banks in a 2GB device or 256 banks in a 4GB device. Impact on system performance is significant, with lower queue delays and greater availability of data responses compared to conventional memories that run banks in lock-step. Not only is there massive parallelism, but HMC supports atomics that reduce external traffic and offload remedial tasks from the processor.

As previously mentioned, the abstracted interface is memory-agnostic and uses high-speed serial buses based on the HMCC protocol standard. Within this uncomplicated protocol, commands such as 128-byte WRITE (WR128), 64-byte READ (RD64), or dual 8-byte ADD IMMEDIATE (2ADD8), can be randomly mixed. This interface enables bandwidth and power scaling to suit practically any design—from “near memory,” mounted immediately adjacent to the CPU, to “far memory,” where HMC devices may be chained together in futuristic mesh-type networks. A near memory configuration is shown in FIGURE 2, and a far memory configuration is shown in FIGURE 3. JTAG and I2C sideband channels are also supported for optimization of device configuration, testing, and real-time monitors.

HMC board routing uses inexpensive, standard high-volume interconnect technologies, routes without complex timing relationships to other signals, and has significantly fewer signals. In fact, 160GB/s of sustained memory bandwidth is achieved using only 262 active signals (66 signals for a single link of up to 60GB/s of memory bandwidth).

FIGURE 2. The HMC communicates with the CPU using a protocol defined by the HMC consortium. A near memory configuration is shown.

FIGURE 3.A far memory communication configuration.

FIGURE 2. The HMC communicates with the CPU using a protocol defined by the HMC consortium. A near memory configuration is shown.

A single robust HMC package includes the memory, memory controller, and abstracted interface. This enables vault-controller parity and ECC correction with data scrubbing that is invisible to the user; self-correcting in-system lifetime memory repair; extensive device health-monitoring capabilities; and real-time status reporting. HMC also features a highly reliable external serializer/deserializer (SERDES) interface with exceptional low-bit error rates (BER) that support cyclic redundancy check (CRC) and packet retry.

HMC will deliver 160 GB/s of bandwidth or a 15X improvement compared to a DDR3-1333 module running at 10.66 GB/s. With energy efficiency measured in pico-joules per bit, HMC is targeted to operate in the 20 pj/b range. Compared to DDR3-1333 modules that operate at about 60 pj/b, this represents a 70% improvement in efficiency. HMC also features an almost-90% pin count reduction—66 pins for HMC versus ~600 pins for a 4-channel DDR3 solution. Given these comparisons, it’s easy to see the significant gains in performance and the huge savings in both the footprint and power usage.

Market Potential

HMC will enable new levels of performance in applications ranging from large-scale core and leading-edge networking systems, to high-performance computing, industrial automation, and eventually, consumer products.

Embedded applications will benefit greatly from high-bandwidth and energy-efficient HMC devices, especially applications such as testing and measurement equipment and networking equipment that utilizes ASICs, ASSPs, and FPGA devices from both Xilinx and Altera, two Developer members of the HMC Consortium. Altera announced in September that it has demonstrated interoperability of its Stratix FPGAs with HMC to benefit next-generation designs.

According to research analysts at Yole Développement Group, TSV-enabled devices are projected to account for nearly $40B by 2017—which is 10% of the global chip business. To drive that growth, this segment will rely on leading technologies like HMC.

FIGURE 4.Engineering samples are set to debut in 2013, but 4GB production in 2014.

Production schedule
Micron is working closely with several customers to enable a variety of applications with HMC. HMC engineering samples of a 4 link 31X31X4mm package are expected later this year, with volume production beginning the first half of 2014. Micron’s 4GB HMC is also targeted for production in 2014.

Future stacks, multiple memories
Moving forward, we will see HMC technology evolve as volume production reduces costs for TSVs and HMC enters markets where traditional DDR-type of memory has resided. Beyond DDR4, we see this class of memory technology becoming mainstream, not only because of its extreme performance, but because of its ability to overcome the effects of process scaling as seen in the NAND industry. HMC Gen3 is on the horizon, with a performance target of 320 GB/s and an 8GB density. A packaged HMC is shown in FIGURE 4.

Among the benefits of this architectural breakthrough is the future ability to stack multiple memories onto one chip. •

THOMAS KINSLEY is a Memory Development Engineer and ARON LUNDE is the Product Program Manager at Micron Technology, Inc., Boise, ID.

IDT president and CEO resigns

August 28, 2013

Integrated Device Technology, Inc., the analog and digital company delivering mixed-signal semiconductor solutions, announced that Dr. Ted Tewksbury has resigned as president, chief executive officer and board member, effective August 27, 2013. The Board of Directors has appointed board member Jeffrey McCreary as interim president and CEO.

Jeffrey McCreary has served on IDT’s Board since June of 2012. A former Texas Instruments senior vice president, McCreary brings thirty years of broad based semiconductor industry leadership and significant boardroom experience to the role. As interim president and CEO, McCreary will work closely with IDT’s current executive team and board of directors to oversee the company’s ongoing operations and strategic initiatives. The board has formed a search committee to identify and consider candidates for the permanent president and CEO role.

“On behalf of the board of directors, I want to thank Ted for his many contributions to IDT over the past five years,” said John Schofield, IDT’s Chairman of the Board. “Since joining the company, he has directed IDT’s transformation into a premier analog and mixed signal semiconductor company delivering system level solutions.”

Schofield continued, “As we begin the CEO search, we are fortunate to have Jeffrey McCreary available to serve in the interim role. Jeff possesses a proven track record as a semiconductor industry executive and has spent significant time making vital decisions in the boardroom as well. We are confident he will provide essential leadership for the Company for as long as required.”

“I am excited about the future for IDT and look forward to contributing to the team’s success,” said McCreary. “We are on a path to reach our previously stated financial targets and to continue leveraging our proven strengths in timing solutions, memory interface, RF, serial switching and power management with great new products.”

TowerJazz announces the creation and accreditation of Jazz Semiconductor Trusted Foundry

August 28, 2013

Jazz Semiconductor Inc., a fully owned U.S. subsidiary of Tower Semiconductor Ltd., has announced the accreditation for trusted status of Jazz Semiconductor Trusted Foundry (JSTF). JSTF has been accredited as a Category 1A Trusted Supplier by the United States Department of Defense as a provider of trusted semiconductors in critical defense applications. JSTF joins a small list of companies accredited by the DoD Trusted Foundry Program, established to ensure the integrity of the people and processes used to deliver national security critical microelectronic components, and administered by the DoD’s Defense Microelectronics Activity (DMEA).

TowerJazz said in its official release that the creation and accreditation of JSTF will help broaden existing business relationships previously disclosed with major defense contractors such as Raytheon, Northrop Grumman, BAE Systems, DRS, Alcatel-Lucent, and L-3 Communications.

“In the United States, there was no ‘pure play’ trusted foundry capability available,” TowerJazz CEO Russell Ellwanger said. “Our aerospace and defense customers asked that we would go this route to enable them greater freedom to serve their great country’s needs; a country that stands as a banner for democratic process throughout the world. Primarily for this purpose, we went beyond our initial commitment to the US State Department to continue support of our ITAR customers and engaged in rounds of discussion with the US Department of Defense toward participation in the Trusted program in our Newport Beach facility. And, as in all activities where one serves purposes of great principle, it is also good business."

“Jazz Semiconductor Trusted Foundry is proud to join the DoD Trusted Foundry Program to enable trusted access to a broad range of on-shore technologies and manufacturing capabilities,” said Scott Jordan, president, JSTF. “The accreditation process adds trust to the existing quality and security systems, improving our level of service to our military and defense customers.”

Entegris and imec collaborate on 3D wafer handling and shipping challenges

August 28, 2013

Entegris, Inc., a developer of contamination control and materials handling technologies for highly demanding advanced manufacturing environments, and imec, a research center in nanoelectronics, announced they are collaborating to advance the development and broaden the adoption of 3D integrated circuits.

3D IC technology, a process by which multiple semiconductor dies are stacked into a single device, is aimed at increasing the functionality and performance of next-generation integrated circuits while reducing footprint and power consumption. It is a key technology to enable the next generation of portable electronics such as smartphones and tablets that require smaller ICs which consume less power.

One of the key steps in 3D IC manufacturing process entails thinning semiconductor wafers while they are bonded to carrier substrates. Handling such thinned 3D IC wafers during the production process can result in wafer breakage, edge damage, and particle generation. A standardized, fully automated solution that supports the handling of multiple types of wafers would result in a significant cost reduction and pave the way toward further development and scaling of 3D IC technologies. Imec and Entegris are working on creating a solution to safely transfer and handle multiple kinds of 3D IC wafers without the risk of breakage and other damage that may occur during the 3D production process.

"We are excited to work with the imec team, which is a key research center leading technology innovation for the semiconductor industry," said Bertrand Loy, president and CEO of Entegris. "Our current collaboration is aimed at leveraging our wafer handling expertise and technology to reduce contamination and breakage by applying full automation to the handling of thin wafers during 3D wafer production. This project builds on our previously completed work with imec to develop dispense and filtration methods to reduce bubble and defect formation during the dispense of material that is used to temporarily bond 3D wafers to carrier substrates," said Loy.

"This collaboration with Entegris aims at developing a solution toward fully automated handling of multiple types of 3D IC wafers," stated Eric Beyne, director of imec’s 3D integration research program. "Such a general solution would imply a significant reduction of the development cost, which is key to the realization of a scalable and manufacturable 3D IC technology."

TSMC becomes the largest semiconductor supplier in the world in 2Q13

August 27, 2013

IC Insights’ recently released August Update to The McClean Report includes Part 1 of an in-depth analysis of the fast-growing IC foundry market. Part 2 of the IC foundry analysis will be presented in the September Update.

Figure 1

Figure 1 shows the reported IC foundry sales and “final market value” IC foundry sales as a percent of total IC industry sales from 2007-2017. The “final market value” figure is 2.22x the reported IC foundry sales number. The 2.22x multiplier estimates the IC sales amount (i.e., market value) that is eventually realized when an IC is ultimately sold to the final customer (i.e., the electronic system producer).

An example of how an IC foundry’s “final market value” sales level is determined can be made using Altera. Since a fabless company like Altera purchases PLDs from an IC foundry, and does not incorporate them into an electronic system, Altera is not considered the final end-user of these ICs. Eventually, Altera resells its IC foundry-fabricated PLDs to electronic system producers/final end-users such as Cisco or Nokia at a much higher price than it paid the IC foundry for the devices (i.e., gross margin). As a result, a 2.22x multiplier, which assumes a 55 percent industry-wide average gross margin for the IC foundry’s customer base, is applied to the IC foundry’s reported sales to arrive at the “final market value” sales figure.

As was shown in Figure 1, the total “final market value” sales figure for the IC foundries is expected to represent just over 36 percent of the worldwide $271 billion IC market forecast for 2013, and just over 45 percent of the $359 billion worldwide IC market forecast for 2017. The “final” IC foundry share in 2017 is forecast to be slightly more than double the 22.6 percent “final” marketshare the IC foundries held ten years earlier in 2007.

To further illustrate the increasingly important role that foundries play in the worldwide IC market, IC Insights applied the “final market value” sales multiplier to TSMC’s quarterly revenues and compared them to Intel’s quarterly IC sales from 1Q11 through 2Q13. Since TSMC’s sales are so heavily weighted toward leading-edge devices, IC Insights estimates that the gross margin for TSMC’s customer base averages 57 percent (a 57 percent gross margin equates to a 2.33x sales multiplier). Using the 2.33x multiplier, IC Insights believes that TSMC’s “final market value” IC sales surpassed Intel’s IC sales in 2Q13 (Figure 2), and that TSMC currently has more impact on total IC market revenue than any company in the world. Considering that Intel’s IC sales were 45 percent greater than TSMC’s “final market value” IC sales as recently as 1Q12, this was a dramatic change in a very short period of time.

Lone Japanese semiconductor supplier ranked among top 10 in 1H13

August 27, 2013

In its Research Bulletin dated August 2, 2013, IC Insights published its list of the top semiconductor sales leaders for the first half of 2013. The list showed the usual big-time players that we’ve come to expect like Intel, Samsung, and TSMC, leading the way in semiconductor sales through the first six months of the year. What stood out nearly as much, however, was that only one Japanese company—Toshiba—was present among the top 10 suppliers through the first half of 2013. Anyone who has been involved in the semiconductor industry for a reasonable amount of time realizes this is a major shift and a big departure for a country that once was feared and revered when it came to its semiconductor manufacturing presence on the global market.

Figure 1 traces the top 10 semiconductor companies dating back to 1985, when Japanese semiconductor manufacturers wielded their influence on the global stage. That year, there were five Japanese companies ranked among the top 10 semiconductor suppliers. Then, in 1990, six Japanese companies were counted among the top 10 semiconductor suppliers—a figure that has not been matched by any country or region since. The number of Japanese companies ranked in the top 10 in semiconductor sales slipped to four in 1995, then fell to three companies in 2000 and 2006, two companies in 2012, and then to only one company in the first half of 2013.

It is worth noting that Renesas (#11), Sony (#16), and Fujitsu (#22) were ranked among the top 25 semiconductor suppliers in 1H13, but Sony has been struggling to re-invent itself and Fujitsu has spent the first half of 2013 divesting most of its semiconductor operations.

Japan’s total presence and influence in the semiconductor marketplace has waned. Once-prominent Japanese names now gone from the top suppliers list include NEC, Hitachi, Mitsubishi, and Matsushita. Competitive pressures from South Korean IC suppliers—especially in the DRAM market—have certainly played a significant role in changing the look of the top 10. Samsung and SK Hynix emulated and perfected the Japanese manufacturing model over the years and cut deeply into sales and profits of Japanese semiconductor manufacturers, resulting in spin-offs, mergers, and acquisitions becoming more prevalent among Japanese suppliers.

1999 — Hitachi and NEC merged their DRAM businesses to create Elpida Memory.
2000 — Mitsubishi divested its DRAM business into Elpida Memory.
2003 — Hitachi merged its remaining Semiconductor & IC Division with Mitsubishi’s System LSI Division to create Renesas Technology.
2003 — Matsushita began emphasizing Panasonic as its main global brand name in 2003. Previously, hundreds of consolidated companies sold Matsushita products under the Panasonic, National, Quasar, Technics, and JVC brand names.
2007 — To reduce losses, Sony cut semiconductor capital spending and announced its move to an asset-lite strategy—a major change in direction for its semiconductor business.
2010 — NEC merged its remaining semiconductor operations with Renesas Technology to form Renesas Electronics.
2011 — Sanyo Semiconductor was acquired by ON Semiconductor.
2013 — Fujitsu and Panasonic agreed to consolidate the design and development functions of their system LSI businesses.
2013 — Fujitsu sold its MCU and analog IC business to Spansion.
2013 — Fujitsu sold its wireless semiconductor business to Intel.
2013 — Elpida Memory was formally acquired by Micron.
2013 — After failing to find a buyer, Renesas announced plans to close its 300mm and 125mm wafer-processing site in Tsuruoka, Japan, by the end of 2013. The facility makes system-LSI chips for Nintendo video game consoles and other consumer electronics.
2013 — Unless it finds a buyer, Fujitsu plans to close its 300mm wafer fab in Mie.

Besides consolidation, another reason for Japan’s reduced presence among leading global semiconductor suppliers is that the vertically integrated business model that served Japanese companies so well for so many years is not nearly as effective in Japan today. Due to the closed nature of the vertically integrated business model, when Japanese electronic systems manufacturers lost marketshare to global competitors, they took Japanese semiconductor divisions down with them. As a result, Japanese semiconductor suppliers missed out on some major design win opportunities for their chips in many of the best-selling consumer, computer, and communications systems that are now driving semiconductor sales.

It is probably too strong to suggest that in the land of the rising sun, the sun has set on semiconductor manufacturing. However, the global semiconductor landscape has changed dramatically from 25 years ago. For Japanese semiconductor companies that once prided themselves on their manufacturing might and discipline to practically disappear from the list of top semiconductor suppliers is evidence that competitive pressures are fierce and that as a country, perhaps Japan has not been as quick to adopt new methods to carry on and meet changing market needs.

RFMD surpasses shipment milestone with breakthrough CMOS power amplifiers

August 27, 2013

RFMD today announced it has shipped more than one million RF7196D high-power, high-efficiency CMOS power amplifiers (PAs). The ultra-low cost RF7196D is RFMD’s newest and most innovative CMOS PA, delivering a revolutionary combination of cost, size and performance. It is in mass production in support of multiple high-volume 2G and 3G handset platforms, and shipments are expected to increase rapidly, reaching approximately 10 million units by the end of the September quarter.

RFMD is seeing strong adoption of its CMOS power amplifier technologies in next-generation handset platforms targeting emerging markets. The company is migrating its diverse set of customers of 2G power amplifiers (both GaAs and CMOS) to its ultra-low cost RF7196D and expects shipments will more than double in the December quarter and exceed 100 million units worldwide in calendar 2014.

Eric Creviston, president of RFMD’s Cellular Products Group (CPG), said, "RFMD’s ultra-low cost CMOS PA technology delivers excellent overall performance at highly competitive costs versus prior generations. We intend to launch a broad portfolio of innovative new CMOS products in the coming quarters, and we forecast strong growth in emerging markets across a highly diversified customer set."

Industry analysts forecast the total addressable market for RF applications in emerging markets will increase at a compound annual growth rate of approximately 20 percent through 2018 as next-generation 3G and 4G air standards are introduced, as existing subscribers upgrade their devices, and as new subscribers are added.

O2Micro introduces 3-way LED bulb driver controller with power factor correction

August 26, 2013

O2Micro(R) International Limited today introduced the patent pending OZ2083 3-Way LED Bulb Driver Controller with Power Factor Correction.

Anapass announces mass production of leading-edge LCD panel controller

August 26, 2013

Anapass, Inc, a display SoC solution provider, today announced that it has successfully completed development of a leading-edge panel controller system on chip “SoC” for UHD TV applications and has recently started mass production. As a result of the successful commercialization of a competitive panel controller SoC for UHD TV, Anapass will be well positioned as a leading panel controller provider for the rapidly growing next generation world-wide TV market, UHD TV.

According to a market research report produced by SNE Research in May 2013, the number of worldwide TV shipments forecasted for this year is 235.1M, 2.6M units of which are expected to be UHD TVs. This year is the first to show significant emergence of UHD TVs as the next generation TV. According to the report, between this year and 2016, the UHD TV market is expected to rapidly grow with 191 percent of CAGR, therefore nearly doubling every year.

The rapid growth of the UHD TV market is reflecting the recent market situation in which the world’s leading flat panel TV makers are aggressively expanding their UHD TV line up from premium high-end TVs down to high volume, smaller panel size TVs ranging from 50 to 60 inch. As such, the UHD TV market is expected to have very aggressive growth. In addition, the swift evolution of the UHD (3840 x 2160) video content eco-system, which provides four times higher resolution than FHD (1920×1080) is strongly supporting the emergence of the UHD TV market era.

Anapass said it intends to leverage its technical know-how and experience in developing and launching panel controller products for flat panel TVs for leading the commercialization of next generation panel controller products optimized for the rapidly growing UHD TV market. Anapass said it is expecting that this will significantly contribute to continuous growth of its core panel controller business.

Researchers offer explanation for strange magnetic behavior at semiconductor interfaces

August 26, 2013

They’re not exactly the peanut butter and jelly of semiconductors, but when you put them together, something magical happens.

Alone, neither lanthanum aluminate nor strontium titanate exhibit any particularly notable properties. But when they are layered together, they become not only conductive, but also magnetic.

In the current online edition of Nature Physics, researchers at The Ohio State University report the first-ever theoretical explanation to be offered for this phenomenon since it was discovered in 2004.

Understanding how these two semiconductors interact at their interface could someday lead to a different kind of material—one that provides a single platform for computation and data storage, said Mohit Randeria, co-author of the paper and professor of physics at Ohio State.

"The whole question is, how can you take two materials which do not conduct electricity and do not have magnetic properties, make a sandwich out of them and—lo and behold—at the interface tween them, charge begins to flow and interesting magnetic effects happen?" he said.

"It’s like taking two pieces of bread and putting them together and having the sandwich filling magically appear."

By making calculations and modeling the basic physical properties of both materials, Randeria’s team has hit upon an explanation for the behavior that seems ironic: the interface between two non-magnetic materials exhibits magnetism.

The team showed how the elemental units of magnetism, called "local moments," are formed at the interface of the two materials. They then showed how these moments interact with the conducting electrons to give rise to a magnetic state in which the moments are arranged in an unusual spiral pattern.

If the physicists’ explanation is correct, then perhaps someday, electronic devices could be constructed that exploit the interface between two oxides. Theoretically, such devices would combine the computational abilities of a silicon chip with the magnetic data storage abilities of permanent magnets like iron.

"If you had conduction and magnetism available in the same platform, it could be possible to integrate computer memory with data processing. Maybe different kinds of computation would be possible," Randeria said.

But those applications are a long way off. Right now, the physicists hope that their theoretical explanation for the strange magnetic behavior will enable other researchers to perform experiments and confirm it.

Randeria’s coauthors included Ohio State postdoctoral researcher Sumilan Banerjee and former doctoral student Onur Erten, who graduated this summer and is about to begin a postdoctoral fellowship at Rutgers, The State University of New Jersey.