Category Archives: Editors Picks

October 4, 2012 – Fab equipment spending continues to soften in 2012, but don’t hope for a reprieve until later in 2013, warns one analyst.

Worldwide wafer fab equipment (WFE) spending is projected at $31.4 billion in 2012, a -13.3% decline from 2011, according to Gartner. But counter to some other industry watchers, the firm now thinks there won’t be a big rebound in 2013 — it’s now forecasting a -0.8% slip next year to $31.2B, before finding its footing again and bouncing back in 2014 with 15.3% growth to $35.9B.

Earlier this summer Gartner foresaw a -8.9% decline in 2012, followed by 7.4% growth in 2013. Less than a month ago SEMI predicted 2013 could be a "golden year" with nearly 17% growth in fab spending.

"The outlook for semiconductor equipment markets has deteriorated as the macro economy has weakened," stated Bob Johnson, research VP at Gartner. After starting the year strong thanks to sub-30nm production ramps at foundries and other logic manufacturers, demand for new equipment logic production will soften as yields improve, leading to declining shipment volumes for the rest of the year."

Fab utilization rates will erode to the low 80% range by the end of this year, slowly increase to about 87% by the end of 2013. (That’s less optimistic than its June outlook which saw mid-80% in mid-2012 and 87% by the end of the year.) Leading-edge capacity will recover slightly better, hitting the high-80% range by year’s end and gradually getting into the low-90% range as 2013 progresses.

Increased demand combined with less-than-mature yields at the leading edge had been hoped to consume extra capacity and raise utilization rates. In leading-edge logic that has in fact helped create inventory shortages, Johnson noted, but "not enough to bring total utilization levels up to desired levels. In the memory segment, some suppliers are even cutting production in an attempt to shore up weak market fundamentals."

Memory is expected to be weak through 2012, with strong declines in DRAM investments and a virtually flat NAND market, the firm notes. Foundry spending has been revised downward for both 2012 and 2013; some foundries have improved their 28nm yields, but mainly for SiON technology, as 28nm high-k/metal gate (HKMG) processes are still yielding below normal. Longer-term, Gartner thinks foundries will ratchet up their spending more in future years due to aggressive development of EUV lithography and 450mm wafer processing.

by Dan Tracy, senior director, SEMI Industry Research and Statistics

October 3, 2012 – Semiconductor manufacturers in Japan are either consolidating or closing fabs, and, in several cases, transitioning to a "fab-lite" strategy, all in a restructuring effort to meet the market challenges ahead. While device manufacturers are consolidating manufacturing operations and plan to outsource more wafer fabrication and package assembly to foundries and packaging subcontractors, a large installed fab capacity remains in Japan. Recent data for the year shows overall wafer area shipments into Japan’s fabs being the same as shipments into Taiwan.

By 2014, the total installed fab capacity Japan should increase slightly from about 4.5 million to 4.6 million 200mm equivalent wafers per month. Installed 300mm fab capacity is expected to increase from about 760,000 to 840,000 300mm wafers per month — representing, by region, the third largest 300mm fab manufacturing capacity base globally. Over the next several years, fab spending in the Japan market will be directed towards the production of NAND flash memory, power semiconductors, high-brightness LEDs, and CMOS image sensors.


Regional share forecasted for 2013 fab materials market. Total market size: $25.7 billion.

Overall equipment spending in Japan will likely range on the order of $4 billion per year. Expected NAND flash investments in 2013 could approach up to $2.5 billion. LED fab equipment spending is estimated to be $340 million next year. Finally, Sony is expected to invest about US$ 1 billion or more in its CMOS image sensor production.

Japanese equipment and material suppliers are leading players on the global semiconductor industry stage. It is estimated that Japan-headquartered equipment companies collectively capture about 35% share of the global semiconductor industry spending per annum. Like their North American and European counterparts, customers in the rest of the Asia Pacific region are the largest base for new equipment sales.

Chemical and other material suppliers in Japan are market leaders in the manufacturing of silicon wafers, III-V wafers, advanced chemicals, packaging resins, and packaging substrates. It is estimated that the Japanese material suppliers sales represent about 70% of the global semiconductor materials market, both fab and packaging.

Japanese suppliers showcase the latest products at SEMICON Japan 2012

Leading Japanese equipment and materials suppliers will exhibit at SEMICON Japan 2012 on December 5- 7, along with global key players, at the Makuhari Messe, Japan. Find the latest products and innovations this companies offer to customers globally that enable key technologies for the future including 450mm, EUV, TSV, power devices, and HB-LEDs to name a few. Also, the show will co-locate with a major photovoltaic show, PVJapan 2012 so you can connect to two major microelectronics industries in a single visit.

For more information, including registration and exhibition, visit www.semiconjapan.org/en.

October 3, 2012 – Macroeconomic malaise continues to weigh down global semiconductor sales, although there’s a possible ray of hope for a boost by year’s end thanks to introduction of much-desired electronics devices (hello iPhone 5).

Worldwide sales of semiconductors in August were $24.30 billion, up just a fraction of a percent from the previous month (as they were in July), and down a couple of percentage points from the same month a year ago (also continuing the trend). For the year through August, chip sales are down about -4.6% to $189.46 billion. (The WSTS’ midyear forecast in June, which the SIA now "endorses" in lieu of its own numbers, projected a scant 0.4% increase in 2012.)

The regional sales map remained uneven in August, with month/month pullbacks in Japan and Europe, but a surprising rebound in the Americas — its first M/M growth period since April. Compared with a year ago though, the Americas is still showing weakness (around -9%).

"Global semiconductor sales have held steady in recent months despite strong macroeconomic headwinds, but these challenges have hampered growth," stated Brian Toohey, SIA president & CEO. He also urged "vigorous discussion" between the two US presidential candidates heading into the final weeks of the election period, to enact "government policies to reduce business uncertainty, accelerate the economic recovery and keep America at the forefront of innovation."

Barclays’ CJ Muse breaks down the SIA’s August numbers by device category and end market, determining that almost every sub-segment underperformed in the quarter except NAND thanks mainly to ASP declines. He also points out that with most industry watchers still holding out hope for even 1% growth in 3Q12 (and for the full year 2012), September’s chip sales would have to be gangbusters at 6% growth — and in recent days both Intel and TI have lowered their 3Q outlooks echoing softness (a $1B shortfall for INTC).

Analyzing end market demand, Muse notes that a weak back-to-school period pushed consumer chip sales into negative territory for the first time since the beginning of the year (-4.3% Y/Y), though there was a slight uptick in sales M/M thanks to ASPs.

Chip sales tracking is now entering the critical seasonal period of buildup to make electronics products for year-end holiday sales. And therein lies a ray of hope, at least for some vendors — there’s a new iPhone 5 hitting shelves, and reports of an iPad mini ahead, Muse notes.

October 2, 2012 – Researchers at the U. of Illinois have devised a method to monitor a semiconductor surface as it is etched, in real time, with nanometer precision.

The new method, dubbed "epi-diffraction phase microscopy" (epi-DPM), is purely optical, and thus noncontact, so researchers can monitor the entire wafer at once instead of point-by-point. It’s faster, lower in cost, and less noisy than the widely used methods of atomic force microscopy or scanning tunneling microscopy, which can only compare before/after etch measurements, the researchers say.

In their work, a grayscale image is shined via projector onto the sample being etched, enabling creation of complex patterns quickly and easily, and the ability to adjust them as needed. "The idea is that the height of the structure can be determined as the light reflects off the different surfaces," stated electrical and computer engineering professor Lynford Goddard, who co-led the group with fellow electrical and computer engineering professor Gabriel Popescu. "Looking at the change in height, you figure out the etch rate. What this allows us to do is monitor it while it’s etching. It allows us to figure out the etch rate both across time and across space, because we can determine the rate at every location within the semiconductor wafer that’s in our field of view."



A three-dimensional image of an etched GaAs semiconductor in a wet etch
solution, taken during etching with the new "epi-diffraction phase microscopy"
(epi-DPM) technique. The height difference between the orange and purple
regions is about 250nm. (Photo by Chris Edwards, Amir Arbabi, Gabriel
Popescu and Lynford Goddard)   And here’s a video describing the process.

Besides monitoring the etching process, the light also catalyzes the etching process itself ("photochemical etching"), a process already used in place of chemical etching on curved features or other shapes. It eliminates the problem of using expensive masks to pattern light through by degrees — and requiring new masks for every tweak of the chip features to achieve correct patterning. "Because our technique is controlled by the computer, it can be dynamic. So you can start off etching one particular shape, midway through realize that you want to make some change, and then change the projector pattern to get the desired outcome," Goddard said.

Beyond semiconductor etching, the researchers see applications for real-time monitoring of other processes in materials and life sciences, e.g. observing carbon nanotubes self-assembly, error monitoring during large-scale computer chip manufacturing, or ensuring precise equipment calibration. Their work, funded by the National Science Foundation, appears in the Sept. 28 journal Light: Science and Applications. Here’s a snippet:

We present epi-diffraction phase microscopy (epi-DPM) as a non-destructive optical method for monitoring semiconductor fabrication processes in real time and with nanometer level sensitivity. The method uses a compact Mach–Zehnder interferometer to recover quantitative amplitude and phase maps of the field reflected by the sample. The low temporal noise of 0.6nm per pixel at 8.93 frames per second enabled us to collect a three-dimensional movie showing the dynamics of wet etching and thereby accurately quantify non-uniformities in the etch rate both across the sample and over time. By displaying a gray-scale digital image on the sample with a computer projector, we performed photochemical etching to define arrays of microlenses while simultaneously monitoring their etch profiles with epi-DPM.

Visit the Semiconductors Channel of Solid State Technology, and sign up for our WaferNEWS e-newsletter!

October 2, 2012 – Driven by market demand, the semiconductor industry is progressing toward consensus on building-block standards for automating LED production on 6-in wafers, explains Paula Doe in an article for SST sister magazine LEDs Magazine.

With the fast-growing demand for HB-LEDs, the industry has added roughly 100 new fabs in the last five years, for a total of 169 LED fabs worldwide. Total industry epitaxy capacity has subsequently ballooned 5× to some 2 million (4-in equivalent) wafers a month.

But there’s still considerable headroom to improve yields and reduce costs — and drive the growth of the solid-state lighting (SSL) market — by moving to larger-diameter wafers and automated production with tighter process controls. Lower front-end processing costs for 6-in wafers mean translate to a 25% cost savings vs. 4-in wafers, per unit surface area, assuming equivalent yields and around $150/wafer for the bigger wafers.

In the latest issue of LEDS Magazine, Paula Doe examines the major players’ progress in enabling this transition, forging consensus on the basics of common wafer parameters, common interfaces for production equipment, and common communication software to communicate data from analysis tools. Bottom line: efforts could enable a $7/$8 60W-equivalent LED bulb by 2014, which would propel the general lighting industry to surpass displays as the main driver of the LED market.

Click through to read the full article.


(Image via LEDs Magazine)

Visit the LED Manufacturing Channel on Solid State Technology and subscribe to the LED Manufacturing News monthly e-newsletter!

October 1, 2012 – Tezzaron Semiconductor is taking over SVTC Technologies’ wafer fab in Austin, TX, amid reports that the semiconductor/MEMS development organization is cutting back activities in Austin and in California — and perhaps shutting its doors entirely.

In a statement, the Naperville, IL-based 3D IC technology firm acknowledges that days ago SVTC "announced to customers and employees that the [Austin] plant would be closed and liquidated by month’s end." This confirms local reports that SVTC had filed notice with the State of Texas about imminent and permanent layoffs of more than a hundred workers at the former SEMATECH ATDF facility. One report further suggested that SVTC might consolidate its operations in Austin.

More bad news for SVTC may be afoot. Last week local reports surfaced that the group has filed similar notification to authorities in California. That report includes a copy of the actual filing with the Economic Development Department, which lists another 106 layoffs — among them the positions of CEO and CFO, and dozens of directors and managers.

Tezzaron processes some of its wafers at the SVTC Austin fab, and intends to expand the fab’s capabilities to support some of its specialized 3D steps that are currently done elsewhere, a Tezzaron official told SST. While the firm says it will continue to support all other processes and services currently offered at the site, its "main strategy is not changing; our focus is still 3D," the official explained. "This acquisition allows us to consolidate much of our processing in one US location while continuing the fab’s current business model."

SVTC Technologies — née Cypress Semiconductor’s Silicon Valley Technology Center — was spun off in early 2007 with VC/private equity backing, and later that year combined with SEMATECH’s ATDF in Austin, TX.

"This is the only facility of its kind on the continent. It supports product innovations for semiconductors, life sciences, clean energy, aerospace, and defense," stated J.T. Ayers, Tezzaron’s CEO. "When we became aware it might be shut down, we knew we had to work quickly to retain this highly valuable group of people and capabilities."

No terms of the Austin deal were offered, though Tezzaron says it should close within two weeks, during which time the fab will continue normal operations. The Austin fab will become a subsidiary of Tezzaron and be led by David Anderson, SVTC VP and former SEMATECH/ATDF director.

Check out our Semiconductors Channel of Solid State Technology and WaferNEWS e-newsletter!. And visit the Advanced Packaging Channel of Solid State Technology, and sign up for our Advanced Packaging News e-newsletter!

September 28, 2012 – Want another snapshot of who’s leading the pack among pure-play foundries, and who’s falling off the curve? Look more closely at <45nm offerings, as framed by a recent analysis from IC Insights.

Overall, total pure-play IC foundries will register about 30% of their sales in <45nm process technologies, up from 22% in 2011, IC Insights calculates. Older (>0.18μ) technologies will account for 13%, down from 14% in 2011 and 15% in 2010.

GlobalFoundries, which earlier this year passed UMC to become the No.2 foundry, has rapidly narrowed the technology gap enjoyed by TSMC over its foundry rivals. GF actually has had a significantly higher percentage of its sales coming from 45nm and below process technologies than TSMC (55% vs. 26% in 2011, 65% vs. 37% in 2012), thanks to its MPU-centric focus. TSMC’s still far ahead in terms of actual dollars ($3.8B vs. $1.9B in 2011, $6.2B vs. $2.8B in 2012).

In contrast, look at the next two "Big 4" pureplay foundries: UMC’s <45nm technology generated 6% of sales ($243M) in 2011 and 11% ($427M) in 2012, while SMIC has gotten less than 1% in both years ($1M and $6M). IC Insights thus connects the dot from <45nm sales, through the metric datapoint of revenue/wafer, and into profit margins. (To be fair, UMC is skipping 45nm and offering a 40nm process.)

That lead for TSMC and GlobalFoundries is widening more now that 28nm devices are starting to emerge. "Although many of the pure-play foundries other than the Big 4 focus on specialized processes and technology, the process technology gap between the other significant pure-play IC foundries and the leading-edge producers is enormous," IC Insights notes. Beyond UMC and SMIC who are falling behind, of the next 14 pureplay foundries only four (TowerJazz, Grace/HHNEC, Dongbu, and Xinxin) are expected to have even limited <90nm capabilities this year. Their total overall sales will amount to $4.6B, only about 15% of the total pureplay IC foundry market.

What’s the takeaway from all this? Successful (i.e., profitable) foundries will be the ones "at the leading edge of the process technology roadmap," IC Insights says. (Note that GlobalFoundries is already talking about its 14nm FinFET technology coming in 2014, barely a year after its new 20nm process.) And for all chip companies, those who have the money have the ability to invest in R&D as required to keep up with more complex IC designs and new process technologies.

Major pure-play foundry comparisons. (via IC Insights)

September 27, 2012 – A device that measures very thin quantities of liquid, such as the synovial fluid in knee joints, and a device that measures change in mass when a microdevice adsorbs small amounts of material earned top honors in Sandia National Labs’ annual student design contest for microelectromechanical system (MEMS) devices.

Texas Tech took top "novel design" honors with a micro-rheometer device that can measure the behavior of very thin quantities of liquid, such as the synovial fluid in knee joints. The method requires much smaller samples compared to macro-scale rheometers. "It is much easier, and usually less painful, to obtain small quantities of bodily fluids from patients," according to the students’ submission.


Texas Tech proposes to create a micro-rheometer to measure very thin quantities
of liquid, like that found in knee joints. (Image courtesy of Texas Tech U.)

Carnegie Mellon students won in the education category, for a device that measures the (relatively large) change in mass with a microdevice material adsorbtion, which alters the vibrational frequencies of the system. This could identify surface changes in the structure — e.g., water vapor on MEMS devices may reduce the fatigue strength of polysilicon MEMS, while hydrocarbons adsorb onto microrelay contacts and increase their electrical resistance.

Both schools were repeat winners from Sandia’s 2011 MEMS competition. Last year Texas Tech showed off an ingenious, dust-sized dragonfly with surveillance possibilities, while Carnegie Mellon won acclaim for an ultrasensitive microvalve to control very small fluid flows.

Carnegie Mellon students made use of the relatively large change in mass that occurs when a microdevice adsorbs even a small amount of material. (Image courtesy of Carnegie Mellon U.)

The nine-month-long University Alliance Design Competition is a program geared around MEMS design, fabrication and test, with one category emphasizing novel design concepts, and another category emphasizing unique structure design and its use as an educational tool for MEMS or science education. Students developed ideas for a device, created and analyzed a design model, and submitted the design to be judged by Sandia’s MEMS experts and university professors. The designs were fabbed at Sandia’s Microsystems and Engineering Sciences Applications (MESA) facility using its "Summit V" (Ultra-planar, Multi-level MEMS Technology 5) — a five-layer polycrystalline silicon surface micromachining process (one ground plane/electrical interconnect layer and four mechanical layers). Designs were then shipped back to the university students to test whether the final product matches the purpose of the original computer simulation.

This year’s event attracted nine universities, up from five in 2011, partly due to added participation from Mexican universities: the Air Force Institute of Technology, Arizona State U., Central New Mexico Community College, Centro de Investigación y de Estudios Avanzados del Instituto Politécnico Nacional of Mexico City, Carnegie Mellon U., Southwestern Indian Polytechnic Institute, Texas Tech U., Universidad de Autonoma de Ciudad Juarez, Universidad de Guadalajara, Universidad de Guanajuato, U. of Oklahoma, U. of Utah, and Universidad Veracruzana. (The two winners, plus Arizona, Oklahoma, and the AFIT, were the 2011 participants.)

For more information regarding the University Alliance and the design competition, contact Stephanie Johnson at [email protected].

Visit the MEMS Channel of Solid State Technology, and subscribe to our MEMS Direct e-newsletter!

by Karen Lo, director, SEMI Taiwan

September 26, 2012 – At the SEMICON Taiwan 2012 450mm Supply Chain Forum on September 7, leading foundries and equipment manufacturers such as TSMC, TEL, Lam Research, Applied Materials, and KLA-Tencor convened to discuss the latest trends in 450nm technology as well as the opportunities and challenges involved. The experts at the forum agreed that many technical obstacles remain on the path to achieve mass production for 450mm wafers by 2018. The industry supply chain must collaborate on innovation to make this vision a reality.

In a presentation entitled "450mm challenges and opportunities," Dr. C.S. Yoo, senior director of the 450mm program at TSMC, said that increasing node complexity means diminishing returns from process miniaturization. For this reason, the industry began studying 450mm wafers with the goal of improving production efficiency, accelerating technology ramp-up, and shortening production cycles. Yoo stated that these advantages, together with higher land and personnel utilization rates, hopefully will offer the semiconductor industry more opportunities for long-term development.

Dr. C.S. Yoo, sr. director of 450mm program, TSMC

According to Yoo, the biggest question in the bid to realize mass production by 2018 is whether the industry can successfully develop the lithography required for 10nm node processes by 2015. At the same time, the industry must solve problems such as rationalizing equipment costs to make return on investments predictable, realizing significant improvements in productivity, and development of automated unmanned foundry operations, smart equipment, and green foundries.

The industry made many technological breakthroughs during the conversion over to 300mm wafers — and Yoo expects that the transition to 450 will produce even more innovative technologies in the future. TSMC will leverage its partnership with the Global 450 Consortium (G450C) as well as work with IC and equipment manufacturers to support the successful transition of the industry to 450mm.

Dr. John Lin, general manager of G450C, introduced the latest developments at G450C, noting that significant advances in 450mm technology have occurred in the past year and industry interest is continuing to build. He stated that the goal of G450C is to begin demonstrating 14nm technology this year and put 10nm into pilot production between 2015 and 2016. Major improvements in the quality of supply for 450mm wafers have been made, and most of the production machinery should complete the prototype phase by 2014. As for lithography — the most crucial part of the project — the preliminary prototype will probably be completed in 2016 and be ready for mass production by 2018.

The CNSE cleanroom is expected to be ready by December 2012; it will be the first 450mm foundry in the world. Lin said that G450C will continue to collaborate with suppliers and SEMI to promote the standardization of 450mm hardware infrastructure components as well as back-end processing and packaging and testing operations. By sharing in the costs of development, the industry will enjoy the benefits offered by 450mm.

Among equipment manufacturers, Dr. Akihisa Sekiguchi (VP and GM of corporate marketing, TEL), Mark Fissel (VP of 450mm program, Lam Research), Kirk Hasserjian (corporate VP of silicon systems group, Applied Materials) and Hubert Altendorfer (senior director of 450mm program, KLA-Tencor) all talked about the challenges involved with developing 450mm equipment.

Seikiguchi believes that 450mm will revolutionize the semiconductor industry and that only companies with strong financial fundamentals will survive due to the high cost of investment. With several years to go until the target of achieving mass production by 2018, Seikiguchi believes that the risks and uncertainty during this period makes proper communication and collaboration between customers, equipment suppliers, foundries and industry associations all the more important. The semiconductor industry should learn from past experience with 300mm transition to avoid making the same mistakes.

Mark Fissel of Lam Research also invoked the transition to 300mm as an example. The first prototype was completed in 1995 but the "dot-com" bubble and other economic factors slowed progress, so it took nine years for 300mm wafer shipments to finally exceed 200mm wafers in 2004. The development of 450mm equipment must also contend with design issues and challenges in terms of technology, capacity, cost and size. Fissel believed that the industry must balance the risk for 450mm development with its long-term ROI.

Kirk Hasserjian of Applied Materials proposed six important factors for a smooth transition to 450mm: Synchronization of the industry’s transition timetable, maturity of lithography, cost sharing, collaboration, innovation, and supply chain readiness.

The eventual wafer size transition will have widespread implications, both for those who make the transition as well as for those that wait. Much of the semiconductor ecosystem is now paying attention to — and planning for — the transition. SEMI is facilitating the development of industry standards and the flow of information throughout the supply chain. SEMI recently launched 450 Central, a web-based information service to help the industry efficiently transition to 450mm-ready solutions and keep the industry informed of important news and perspectives on 450mm wafer processing.

The most knowledgeable and authoritative voices in the industry discuss these tough issues at SEMI events around the world. Our objective is advance the dialog — to convey useful information to our attendees — and to serve as a platform for productive collaboration on these and other industry issues. The upcoming SEMICON Europa (October 9-11) features a 1.5 day session on "Progress in 450mm." For more information on SEMI, visit www.semi.org.

September 25, 2012 – GlobalFoundries announced it has developed a 14nm process technology "with elements of" its 20nm planar (LPM) process, which it says will offer improved battery life and higher performance vs. other 20nm 2D planar transistors.

The new process, dubbed 14-XM ("eXtreme Mobility"), is a nonplanar architecture optimized for mobile system-on-chip designs, the company claims. The new approach is promoted as a cost-effective and power-optimized FinFET technology ideally suited for the mobile SoC market, with an "ideal" balance between performance and power consumption, while minimizing both die size and cost. Designers also will be able to reuse much of their previous-generation IP.

Specifically, the 14nm-XM technology incorporates GlobalFoundries’ 20nm-LPM "middle-of-line" processes with tight design rules to enable 8T standard cells, and the 20nm-LPM "backend-of-line" (BEOL) to realize cost and density advantages, plus some "fin-friendly” layout rules for faster porting of existing design IP. Overall results are said to be 40%-60% improved battery life and 20%-55% higher performance (depending on operating voltage) vs. other 20nm 2D planar transistors; more details will be made available in coming months after silicon validation. (Here’s the official presentation [PDF download] describing the technology and its specific benefits; here’s an abridged version as an online slideshow.)

The new 14nm-XM process’ timing is noteworthy — GlobalFoundries’ 20nm process is slated to deliver silicon sometime in 2H12 and ramp in 2013, so this new 14nm process would follow barely a year later. (Intel unwrapped its own FinFET process in May 2011 and debuted first products this past spring.) The synergy between the two processes, 20nm planar and 14nm with FinFETs, "means we will be able to offer our customers the fastest path to FinFET with the least amount of risk," the company explains.

Further helping the speedy ramp-up is the ability to leverage the 10 years of FinFET R&D know-how of the Common Platform Alliance (mostly IBM). "Through our partnership in the Common Platform Alliance, we own more than 3/4 of the industry patents on FinFET technology. We are confident that this heritage of deep R&D will allow us to lead the foundry volume ramp of FinFETs as we did with HKMG," the company explains.

GlobalFoundries also has a new multiyear agreement with ARM to optimized the SoC technology for ARM processor designs on FinFET process technologies, extending an existing collaboration for the ARM Cortex-A processors that will now focus on production IP platforms "that will promote rapid migration to three-dimensional FinFET transistor technology."

Test silicon with the technology is already running through the company’s Fab 8 in New York, and early process design kits are already available. Customer tape-outs are planned for 2013 and a ramp to volume production is planned for 2014. (The foundry’s 20nm process itself is expected to ramp in 2013.)

FinFETs operate at lower Vdd and with low off-state leakage. (Image via GlobalFoundries)