Category Archives: Editors Picks

September 25, 2012 – A three-year European project to research solution-processable materials for OLEDs has concluded, with newly developed materials that can be integrated into large-surface OLED components and are suited for printing processes.

The NEMO (NEw Materials for OLEDs from solutions) project, a consortium of 11 companies led by Merck, was formed in Nov. 2009 with backing from the German Federal Ministry of Education and Research (BMBF), to explore a variety of OLED materials and capabilities: soluble light-emitting materials, charge transport materials, new adhesives for reliable encapsulation of each OLED component. Physical tests were included to understand more about the materials for future development work. The project’s total budget was €29M (roughly US $38M).

"The success of the project is an enormous and important step for printable material systems with very good performance data," stated Dr. Udo Heider, head of the OLED unit at Merck. "We are enabling our customers to use cost-efficient manufacturing processes, which thanks to their low material losses in production, will ultimately also benefit the environment."

Results of the project include Merck’s development of a new phosphorescent materials for red, green and blue applications — increasing lifetime extrapolated to 50% of initial brightness (i.e., stability in use) of green triplet emitter materials from 10,000 hours to more than 200,000 hours, and increasing the efficiency of these materials from 30 cd/A up to more than 70 cd/A (candela/ampere) at a brightness of 1000cd/m2.

Here’s a list of other results achieved by the NEMO project’s four industry companies and seven research institute/academic groups:

Humboldt University of Berlin: Modular synthesis strategies were used to produce and test new electron transport materials.

DELO Industrie Klebstoffe: Development of adhesives with low water vapor permeation for flat encapsulation. A main focus of the work was on optimizing the compatibility of the adhesive with the OLED materials. Suitable adhesive systems were identified, and a significant reduction in component defects was achieved. The developed systems were extensively characterized.

Enthone GmbH (formerly Ormecon): Developed dispersions of polyaniline, an electrically conductive polymer, from which charge carrier layers for OLEDs were produced. These displays show electrical properties equivalent to those of the previously used material. For OLED component characterization, impedance spectroscopy was used to investigate the OLEDs prepared by Merck. It was possible to identify unstable areas, which are responsible for the short lifetimes of OLEDs. Additionally, the impedance measurements were used to predict the lifetime of displays.

Fraunhofer Institute for Applied Polymer Research (IAP): Developed polymer-based phosphorescent systems for green and red Merck emitters. Suitable charge transport molecules were bonded as a side group to a main polymer chain. It was possible to demonstrate that this leads to comparable or even better performance parameters and lifetimes of OLEDs in comparison with solution-processable small molecules. For "green", energy efficiencies of 61 cd/A and lifetimes of 66,000 h @ 1000 cd/m2 were achieved.

Heraeus Precious Metals GmbH & Co. KG (formerly H.C. Starck Clevios GmbH): Developed new materials for the intermediate layers, which will improve the charge carrier injection from the anode into the OLED emitter layer and help to increase the lifetime of the components. The work function of the hole injection layers can be set to a specific target value within a wide range of 4.8-6.1 eV. Water-soluble polymer counterions have been developed, which have helped to realize dehydrated PEDOT materials for the first time.

In parallel to this, work was conducted on transparent electrodes that can be separated from solution and are expected to lower the costs of OLEDs. The conductivity of the PEDOT:PSS films was further increased. Initial ITO-free OLED lamps have been realized. In combination with screen printed silver lines, this enables the production of OLEDs for lighting application without any identifiable decrease in luminance from the edge to the center of the component.

University of Potsdam: Studied physical properties such as charge carrier transport and excitation dynamics in newly synthesized materials and in the finished component. In combination with stationary and transient simulations, information was obtained on what processes restrict the efficiency of light emitting diodes and which ones impact component aging.

University of Regensburg: One working group, led by Professor Yersin, developed new emitter classes with both strong and weak metal-metal interactions that show a singlet harvesting effect. It is thus possible to realize highly efficient emitters for OLEDs based on highly economical copper clusters. This work on singlet harvesting with newly developed emitters made from copper clusters was recognized in April 2012 with an innovation prize at the international SPIE Organic Photonics conference in Brussels.

Another working group (led by Professor König) synthesized emitter libraries in accordance with a simple combinatorial protocol. A screening system was developed for the rapid and virtually automated identification and characterization of individual emitters as well as photostability testing thereof. This made it possible to investigate the degradation behavior of many substances and to draw conclusions on various degradation mechanisms.

University of Tübingen: Two groups from Tübingen provided new metallorganic cluster compounds that can be used as luminescent molecules in OLEDs. In chemical synthesis, coordination compounds of the metals rhodium, iridium, palladium, platinum, copper, silver and gold were presented and characterized, giving rise to new, highly promising lead structures for emitter materials.

September 24, 2012 – Sharp Corp. is in discussions with Intel to use the Japanese firm’s LCD panels in new ultrabook laptops, and could be seeking a more substantial partnership that would make the chipmaking giant its top stakeholder, according to local media.

The Mainichi reported that the two firms "are in talks" for Intel to invest more than ¥30B (roughly US $380M) in the "financial troubled" Japanese company, with a deal possible as soon as early October. In a terse announcement, Sharp denied any capital tie-up negotiations.

Sharp’s IGZO display technology (indium gallium zinc oxide) for small- and medium-sized LCDs is seen as a good fit with Intel-powered ultrabooks. It offers mobility performance somewhere between amorphous and low-temperature polysilicon. Its benefits include lower power consumption, thinness (less backlighting needed), highly touch-sensitive, and high definition.

Intel, meanwhile, is viewed as something of a white knight for the Japanese firm, which earlier this year tried a similar tie-up with Taiwanese conglomerate Hon Hai Precision Industry Co.. That deal apparently remains in limbo due to a plunge in Sharp’s valuation. Reuters notes that "cash-strapped" Sharp has nearly ¥360B in short-term loans to repay, and is approaching existing lenders for another ¥200B in more loans.

Sharp has separately announced other efforts to improve its financial standing, including the sale of its US subsidiary Recurrent Energy, two years after it bought the solar firm. It also is selling TV assembly plants in Mexico and China to Hon Hai, and instituting early retirement plans in Japan to reduce costs.

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September 21, 2012 – Demand for chip tools fell again in August and is off by -30% from its peak in early summer, fulfilling fears that the second half of 2012 will be sluggish for chipmaking investments, according to the latest data from SEMI.

North America-based manufacturers of semiconductor manufacturing equipment reported $1.12B in orders worldwide in August (a three-month moving average), down -9.2% from July’s slightly downwardly revised level of $1.23B and down -3.6% from a year ago. Worldwide billings slipped to $1.34B, off by -7.4% from a similarly lowered mark in July and off by -8.4% from the same month in 2011.

For the year through August, chip tool bookings are running about -8% off the same pace in 2011 ($10.97B), with billings off by about -15% at $11.16B, according to SEMI’s historical data. Demand clearly peaked in the spring, flattened in the summer, and has now waned significantly. Global demand for semiconductor manufacturing equipment actually started slipping in 2Q12 with softness in just about every region except Taiwan. (As bad as the current pullback is, it’s a far cry from the -40+% dropoff seen toward the end of 2011.)

"The second half of the year continues to show reduced order and billing levels for the 2012 spending cycle," said Dan Tracy, senior director of SEMI Industry Research and Statistics. Industry watchers already were expecting a pullback in demand especially in 3Q12 (and so are the chipmakers themselves), with mixed feelings about a possible bump in 4Q12.

SEMI’s still sticking with its official forecast issued at SEMICON West which predicts a -2.6% decline for the year. "We expect 2012 equipment revenues to decline slightly with total spending for front-end and back-end semiconductor equipment globally remaining at the $40 billion or greater level for the third consecutive year," reiterated Tracy.

SEMI is growing increasingly bullish, however, for 2013, with initial projections of 17% growth in equipment spending.

  Billings Bookings Book-to-bill
March 1,287.6 1,445.7 1.12
April 1,458.7 1,602.8 1.10
May 1,539.3 1,613.7 1.05
June (f) 1,535.7 1,424.3 0.93
July (r) 1,442.8 1,234.6 0.86
August (p) 1,335.5
 1,120.6
 0.84

Semiconductor bookings and billings, 3-month averages. (Source: SEMI)

Researchers are investigating the use of high electron-mobility materials as a way to improve FinFET performance, such as germanium (Ge) for the channels in p-type transistors. But it is difficult to grow Ge directly on a silicon substrate and usually many interface layers are built, each successive layer having a greater concentration of germanium. However, this gives rise to unwanted complexity and cost.

At this year’s International Electron Devices Meeting (IEDM), foundry TSMC will describe an alternative: a heterogeneous epitaxial growth process which for the first time enables Ge to be directly grown on Si. With careful process optimization, the researchers determined that when a fin’s height-width aspect ratio is ~1.4 or greater, imperfections at the Ge-Si interface (called threading dislocations) will be confined to the bottom part of the fin, leaving its top portion—the active area—defect-free. They demonstrated the technique by building devices with excellent subthreshold characteristics (slope=74mV/dec), good short-channel-effects control and high performance (1.2mA/µm at Vdd=1V). The work paves the way for the use of Ge in future p-type FinFETs.

The schematics show representations of the threading dislocations in (a) wide and (b) narrow active areas. In (b) the threading dislocations terminate at the sidewalls, leaving the top part defect-free.

The first working 3D NAND flash memory at sub-40nm feature sizes will be described by Macronix researchers at this year’s International Electron Devices Meeting (IEDM). They used vertical gates having horizontal channels to create a new architectural layout that dramatically decreases feature sizes in the wordline direction and improves manufacturability. The new architecture also enables the use of a novel “staircase” bitline contact formation method to minimize fabrication steps and cost. The result is an eight-layer device with a wordline feature size of 37.5nm, bitline feature size of 75 nm, 64 cells per string and a core array efficiency of 63%. The researchers say the technology not only is lower cost than conventional sub-20nm 2D NAND, it can provide 1 Tb of memory if further scaled to 25nm feature sizes. At that size the Macronix device would comprise only 32 layers, compared to 3D stackable NANDs with vertical channels that would need almost 100 layers to reach the same memory density.

A previously proposed 3D vertical gate NAND architecture.

An overview of the proposed architectural layout that is said to be an improvement.

 

A cross-sectional views of the new device.

 

TEM electron microscope views of the staircase bitline contacts.

RRAM synapses mimic the brain


September 20, 2012

Neuromorphic, or brain-like, electronic systems that mimic cognitive functions are the focus of research because of their potential for complex tasks such as pattern-recognition. Papers presented at the International Electron Devices Meeting in 2011 described studies using programmable phase-change memory (PCM) synapses in neuromorphic systems to carry out a function called spike-timing-dependent plasticity (STDP). STDP is an electronic analog of a brain mechanism for learning and memory, so an electronic system that accurately performs STDP can be said to be “learning.”

At this year’s IEDM, a team led by Korea’s Gwangju Institute of Science and Technology will detail a high-speed pattern-recognition system comprising CMOS “neurons” and an array of resistive-RAM (RRAM)-based “synapses,” which demonstrated STDP. The 1-Kb RRAM array has a simple crosspoint structure and possibly can be scaled to 4F (the theoretical minimum size for a crosspoint array). The work shows the feasibility of using neuromorphic architecture for high-speed pattern recognition.

 

 

Photo of CMOS neuron circuit with 1kB RRAM array as synapse

 

 

Schematic structure of the proposed system. Input spikes come from the left into the RRAM array. (The inset shows the user interface of a computer simulator.)  The ten input images in the neuromorphic system are learned by edge weighting, and during the learning process ‘5’ in node 4 is represented clearly.

 

In this comparison of artificial brain projects, Gwangju Institute of Science and Technology’s neuromorphic device is compared to other reported devices.

Graphene, a one-atom-thick sheet of carbon atoms, is seen as a potential replacement for silicon in future transistors because it has an exceptional set of properties (high current density, mobility and saturation velocity). However, transistors made of graphene cannot be turned off because graphene has almost no band gap.

Researchers have begun to investigate a new 2D material—molybdenum sulfide (MoS)—which has similar characteristics but offers something graphene doesn’t: a wide energy bandgap, enabling transistors and circuits to be built from it directly. At the upcoming International Electron Devices Meeting (IEDM), an MIT-led team will describe the use of CVD processing to grow uniform, flexible, single-molecular layers of MoS, comprising a layer of Mo atoms sandwiched between two layers of S atoms. They exploited the material’s 1.8 eV bandgap to build MoS transistors and simple digital and analog circuits (a NAND logic gate and a 1-bit ADC converter). The transistors demonstrated record MoS mobility (>190 cm2/Vs), an ultra-high on/off current ratio of 108,  record current density (~20 µA/µm) and saturation, and the first GHz RF performance from MoS. The results show MoS may be suitable for mixed-signal applications and for those which require high performance and mechanical flexibility.

 

The lattice structure of MoS.

 

A schematic of the CVD process for growing single-layer MoS.

 

An optical micrograph of single-layer MoS sheets grown by this process, showing great uniformity and coverage.

 

 

While conventional charge-based memory is approaching fundamental scaling limits, several so-called “emerging memories” have migrated from laboratory samples to integrated products. Among various emerging memory technologies, MRAM (magnetoresistive random access memory) has been making impressive progress, ahead of other emerging memories, and has demonstrated the capability to be a successor to DRAM or SRAM. MRAM data is stored via magnetic moments. Parallel or anti-parallel magnetic moments in MRAM stacks present the “0” or “1” state. In earlier generations of MRAM, these states were switched by current-induced magnetic field but that is an obstacle for scaling.

The invention of ST (spin-torque) MRAM, which is switched by injecting spin-polarized tunneling current, removes the scaling limitation. In an invited paper at the International Electron Devices Meeting, researchers from Everspin Technologies will describe how they built the largest functional ST-MRAM circuit ever built, a 64-Mb device with good electrical characteristics. The work shows that MRAM technology is fast approaching commercialization.

Everspin MRAM products employ a one transistor, one magnetic tunnel junction (MTJ) memory cell for the storage element. The MTJ is composed of a fixed magnetic layer, a thin dielectric tunnel barrier and a free magnetic layer. When a bias is applied to the MTJ, electrons that are spin polarized by the magnetic layers traverse the dielectric barrier through a process known as tunneling. The MTJ device has a low resistance when the magnetic moment of the free layer is parallel to the fixed layer and a high resistance when the free layer moment is oriented anti-parallel to the fixed layer moment.

ST-MRAM uses an alternate method for programming an MTJ element that has the potential to further simplify the MRAM cell and reduce write power. Programming is accomplished by driving current directly through the MTJ to change the direction of polarization. The read operation is accomplished by sensing the MTJ resistance, just like Toggle MRAM.

Everpsin says that ST-MRAM products will offer a new storage class memory solution for non-volatile buffers and caching applications as well as deliver a new nanosecond-class, gigabyte-per-second non-volatile storage tier. Using a spin-polarized current for switching, ST-MRAM can overcome scaling limitations to address persistent DRAM applications in densities from megabits to gigabits.

 

The device has a wide separation between applied and breakdown voltages— the more separation, the wider the device operation margin.

 

This “shmoo plot,” is a graphical display of the ST-MRAM’s performance over a range of voltages. The green area signifies there were no failures of the memory as voltages increased, indicating that its design is robust.

CMOS technology uses the two types of MOSFET transistors (N and P) working together in a complementary fashion: when one is on, the other is off. However, the conflicting materials and design requirements for N- and P-type devices make achieving balanced performance and desired threshold voltage challenging.

Meanwhile, extremely thin SOI (ETSOI) technology is a viable device architecture for continued CMOS scaling to 22nm and beyond. Among the reasons why are that it offers superior short-channel control and low device variability with undoped channels.

At the International Electron Devices Meeting (IEDM) in December, a team led by IBM will report on the world’s first high-performance hybrid-channel ETSOI CMOS device. They integrated a PFET having a thin, uniform strained SiGe channel, with an NFET having a Si channel, at 22nm geometries. A novel STI-last (isolation-last) process makes the hybrid architecture possible. The researchers built a ring oscillator circuit to benchmark performance, and the hybrid planar devices enabled the fastest ring oscillator ever reported, with a delay of only 11.2ps/stage at 0.7V, even better than FinFETs.

 

An electron microscope view at the top and an EDX (energy-dispersive X-ray) spectroscopic view below it of a SiGe-channel PFET with 6-nm channel thickness, 22-nm gate length, 100-nm contacted gate pitch, high-k/metal gate architecture and ISBD SiGe raised source drain. Source: IBM.

September 2012 – Even with the persistent troubles in global economics and various technology hurdles in advanced semiconductor manufacturing, IC market growth will continue to improve — and the key is a shift away from what’s been driving the market dynamics, explains IC Insights.

IC unit shipments have been the bedrock of growth in the IC industry for the past 15 years, underpinning roughly a 5% annual growth rate. But that rate will slow to 7% per year due as slowing global GDP weighs down demand, even as users demand electronic gadgets with more capabilities necessitating more capabilities crammed onto a single chip.

But the firm still sees the IC market expanding its long-term growth rate over the next 10 years to an 8% CAGR, because it thinks IC average selling prices (ASPs) will offset that slowing unit growth. IC ASPs actually declined an average of -4% per year for the past decade and a half, but are seen swinging to an average of 1% growth/year from 2011-2021, for an 8% CAGR.

Behind this shift, the firm explains, are four main factors:

  • No new entry-point opportunities. Door’s closed to new manufacturing startups. (It’s a familiar refrain from the firm’s leader, Bill McClean.) That means less irrational overspending in new fabs.

  • Fab-lite foundry model lives on. Another factor in reducing the exuberant overspending in IC fab capacity.

  • Capex/sales narrowing. Despite the technical challenges to be overcome, capex as a percentage of sales continues to shrink: from 21% in 2011 to 19% in 2012, and likely 15% by the end of the decade, the firm projects.

  • 450mm transition is delayed. Chipmakers have long seen a transition to 450mm wafers as their next major cost stepdown reduction — but now they have a lot of competing balls in the air: EUV, new processes, next-gen transistor structures (e.g. 3D), incorporation of new materials. Something’s got to give.

Year IC unit shipments IC average selling price IC market
1996 49.4 $2.49 $122.8
2011 192.7 $1.37 $264.0
1996-2011 CAGR 9.5% -4.0% 5.2%
2021F 380.0 $1.51 $573.8
2011-2021F CAGR 7.0% 1.0% 8.0%

IC market to show better growth. Unit shipments in
billions, IC market in US $B. (Source: IC Insights)