Single LED packages through complex power LED assemblies are evaluated at the lab, with customers encouraged to observe the in-house tests. A large one-meter integrating sphere determines color temperature (CCT) and brightness (TLF). A thermal imaging camera provides data for optimizing thermal management designs, used to extend the lifespan and light output of power LED assemblies. Other equipment includes a scanning electron microscope (SEM) with a Princeton gamma tech X-ray analyzer for failure analysis, and luminous flux and wavelength tester, a spectroradiometer system, and a goniometer. OPTEK provides comparison data for redesigns or LEDs designed to replace conventional lighting sources.
Category Archives: LEDs
Phoenix Micro, a fables IC design house, provides next-generation, high-capacity intelligent ICs for mobile terminal devices. Intel Capital led series B funding in the company, which will use the investments toward developing storage ICs and facilitating end customers’ value-add and subscriber-management services.
(May 10, 2007) NEW YORK — TT electronics OPTEK Technology opened an in-house visible LED laboratory with resources to assess LED packages on junction temperature variation, optical performance, and other parameters. The lab aids in design, manufacturing, and test.
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April 28, 2007 — /FDA News/ — The U.S. Department of Agriculture (USDA) and the U.S. Food and Drug Administration (FDA) continue their investigation of imported rice protein concentrate which has been found to contain melamine and melamine-related compounds. Based on information currently available, FDA and USDA believe the likelihood of illness after eating pork from swine fed the contaminated product would be very low. The agencies are taking certain actions out of an abundance of caution. As announced on April 26, swine known to have been fed adulterated (contaminated) product will not be approved to enter the food supply. (Because the animal feed in question was adulterated, USDA cannot rule out the possibility that food produced from animals fed this product could also be adulterated. USDA cannot approve potentially adulterated meat.) This update provides additional information regarding the ongoing investigation.
As reported on April 22 by FDA, the Agency determined that rice protein concentrate imported from China was contaminated with melamine and melamine-related compounds. The product was imported by Wilbur-Ellis, an importer and distributor of agricultural products. Although the company began importing product from China in August 2006, the company did not become aware of the contamination until April 2007. As part of the ongoing investigation, FDA has determined the rice protein was used in the production of pet food and a portion of the pet food was used to produce animal feed. The ongoing investigation is tracing products distributed since August 2006 by Wilbur-Ellis throughout the distribution chain.
At this time, we have no evidence of harm to humans associated with the processed pork product, and therefore no recall of meat products processed from these animals is being issued. Testing and the joint investigation continue. If any evidence surfaces to indicate there is harm to humans, the appropriate action will be taken.
The assessment that, if there were to be harm to human health, it would be very low, is based on a number of factors, including the dilution of the contaminating melamine and melamine-related compounds from the original rice protein concentrate as it moves through the food system. First it is a partial ingredient in the pet food; second, it is only part of the total feed given to the hogs; third, it is not known to accumulate in the hogs and the hogs excrete melamine in their urine; fourth, even if present in pork, pork is only a small part of the average American diet. Neither FDA nor USDA has uncovered any evidence of harm to the swine from the contaminated feed. In addition to the dilutional factor and the lack of evidence of illnesses in the swine fed the waste pet food, we are not aware of any human illness that has occurred from exposure to melamine or its by-products. While the Centers for Disease Control and Prevention systems would have limited ability to detect subtle problems due to melamine and melamine-related compounds, no problems have been detected to date. To further evaluate any potential harm to humans, the FDA is developing and implementing further tests and risk assessments based on the toxicity of the compounds and how much of the compounds consumers could be expected to actually consume.
The ongoing investigation and product reconciliation and testing have led to certain farms. We expect the investigation will continue to find more places where product may have been distributed. As of April 26, sites in the following states are believed to have received and used contaminated product: California, Kansas, New York, North Carolina, South Carolina and Utah. As we confirm additional sites that have received and used contaminated product, we will provide additional updates. USDA and FDA continue to conduct a full, comprehensive examination to protect the nation’s food supply and will provide updates as new information is confirmed.
 Trillions of holes create insulating vacuums around nanowires. (Photo: IBM) |
May 4, 2007 — IBM claims the first-ever application of self-assembling nanotechnology to conventional chip manufacturing. The company says it has harnessed the natural pattern-creating process that forms seashells, snowflakes, and tooth enamel to form trillions of holes and thereby create insulating vacuums around the miles of nano-scale wires packed next to each other inside each computer chip.
IBM researchers say the electrical signals on such chips can flow 35 percent faster, or the chips can consume 15 percent less energy, compared to the most advanced chips using conventional techniques.
“The IBM-patented self-assembly process moves a nanotechnology manufacturing method that had shown promise in laboratories into a commercial manufacturing environment for the first time, providing the equivalent of two generations of Moore’s Law wiring performance improvements in a single step, using conventional manufacturing techniques,” the company asserts.
This new form of insulation, commonly referred to as “airgaps” by scientists, is a misnomer, as the gaps are actually vacuums, absent of air. The self-assembly process enables the nano-scale patterning required to form the gaps; this patterning is considerably smaller than current lithographic techniques can achieve.
A vacuum is believed to be the ultimate insulator for wiring capacitance, which occurs when two conductors, in this case adjacent wires on a chip, sap energy from one another, generating heat and slowing data transmission.
Until now, chip designers often were forced to fight capacitance issues by pushing ever more power through chips, creating a range of undesireable side effects. They have also used insulators with better insulating capability, but these insulators have become tenuously fragile as chip features shrink.
The self-assembly process already has been integrated with IBM’s manufacturing line in East Fishkill, New York and is expected to be fully incorporated in IBM’s manufacturing lines and used in chips in 2009. The chips will be used in IBM’s server product lines and thereafter for chips IBM builds for other companies.
“This is the first time anyone has proven the ability to synthesize mass quantities of these self-assembled polymers and integrate them into an existing manufacturing process with great yield results,” said Dan Edelstein, IBM Fellow and chief scientist of the self-assembly airgap project.
Edelstein led the IBM team that invented the technique to use copper wiring in computer chips instead of aluminum, now a standard method for producing chips, ushering in a decade of chip innovations from the IBM labs that transformed how chips were built and used across many industries and applications.
May 3, 2007 – To match a flurry of local activity with new fab activity and upgrades, Singapore’s Economic Development Board (EDB) says it is investing about $5.2 million for a program to prepare up to 300 undergraduate engineers each year for engineering jobs within the nation’s wafer fabs.
The “Wafer Fabrication Specialist Manpower Program,” in conjunction with the Nanyang Technological U. and National U. of Singapore, involves varying levels of stipend to students who specialize in wafer fabrication for one or two years, and promises “guaranteed job offers upon graduation” for all students in the program. The program is being jointly funded by the EDB and sponsoring companies from the wafer fab sector.
Surging growth in Singapore’s semiconductor sector is driving the need for more engineering talent, according to Lim Swee Nian, executive director of EDB’s Electronics cluster. “Besides the continued expansion of existing wafer fabrication plants, new players are attracted to Singapore with advanced technologies,” he said in a statement, citing recent plans from Qimonda for a new 300mm fab, as well as 300mm plans from Intel-Micron JV IM Flash (NAND flash), Soitec (SOI), and Lumileds (LEDs).
That $5.2M in funding is just the EDB’s portion, with unidentified funds coming from other companies who are already on board, with others indicating interest to participate, noted a spokesperson for the Singapore EDB. “We are expecting all the wafer fabrication companies currently based in Singapore [14 wafer fabs] will be sponsoring companies,” the spokesperson said. The program is already being rolled out to students, and will apply only to those students in their final year specializations.
Guaranteeing placement for every one of the program graduates may seem like a bold statement, but the EDB already had been getting feedback from the fabs about their need for wafer fab engineers over the next few years, and both sides are confident that the demand expectations will remain accurate, the spokesperson said,l adding that the EDB, university partners, and participating fabs are all working to design the program’s curriculum to focus on the fab capabilities needed.
Singapore currently has 14 operating wafer fabs, 20 test/assembly facilities, and 40 IC design centers, according to the EDB. That includes three 300mm wafer fabs (Chartered Semiconductor’s Fab 7, UMC’s Fab 12i, and TECH Semiconductor, a DRAM JV between Micron Technology, Canon, and Hewlett-Packard.
By Hank Hogan
When Intel (Santa Clara, CA) recently announced volume manufacturing in the second half of 2007 of a 45 nm process, something was missing: mention of a technology node. Intel isn’t alone in abandoning nodes. The latest International Technology Roadmap for Semiconductors (ITRS) refers to product generation cycles instead.
For those in contamination control, this change could be of more than academic interest. Killer defects have traditionally been defined as a fraction of a node, which is the half pitch of a cell in a memory process or the minimum transistor width in other processes. Thus, the node served as shorthand for a contamination control requirement.
In some ways, that hasn’t changed, says John Goodman, senior vice president and chief technology officer for materials handling company Entegris (Chaska, MN). “The basic rule of thumb of a half linewidth for killer particles is still applicable.”
However, in other ways things have changed because the guideline isn’t always strictly applied anymore. For example, it may be too difficult to develop a filtration membrane to capture particles while maintaining flow. What’s more, the composition of the contaminant may be more important than its size. For those reasons, Goodman says Entegris works with its customers to come up with the right contamination control targets.
As for spotting contaminants, it isn’t always possible to follow a simple node-based formula. The technology to detect particles at low cost and in high volume sometimes doesn’t exist, notes Particle Measuring Systems (Boulder, CO) vice president of marketing John Mitchell.
Thus, those running the 45 nm process might not screen directly for 22 nm contaminants. “There’s no practical way to measure 20 nm particles, particularly in liquids,” says Mitchell.
Instead, he explains, semiconductor manufacturers monitor larger particles. If the distribution of particle sizes doesn’t change and sufficient care is taken in monitoring, this strategy works.
Another consequence of the demise of nodes is that comparisons between processes and contamination control requirements are more convoluted. When evaluating offerings from different manufacturers, Dan McGowan, a spokesperson for SEMATECH (Austin, TX), suggests asking them how their figures of merit, whatever they are, compare to a memory cell’s half pitch. “The answer should help determine how a certain technology advance can be viewed in context with ITRS terminology,” he says.
However, that comparison could be easier to describe than do. Kari Aakre, a spokesperson for Intel, notes that where the company’s technology stands in relation to the technology roadmap depends on which metric is used. She lists such possible measures as transistor gate length, contacted metal pitch, cell size of static random access memory, and others.
While these questions present problems, those who pushed for the dispatch of node nomenclature say the change solves problems. Bob Doering, Senior Fellow and technology strategy manager at Texas Instruments (Dallas, TX), notes company announcements have historically tended to tout process cycles rather than true technology nodes that are 0.7 times the previous generation, a difference that led to trouble in the ITRS. “We were getting almost a whole node out of phase between what we were calling a node and what the common parlance was. So now we don’t use that terminology,” he says.
As we put the finishing touches on our annual university rankings’ issue, the news is filled with reflection on the tragic shootings that took place at the Virginia Tech. And so we dedicate this issue to all those touched by that terrible event.
Proper education of the next generation of small-tech engineers, researchers, and technicians is key to the development of the technology and its applications-and to our nation’s competitiveness long-term. Several recent commercial and policy developments are facilitating our ability to succeed in this endeavor. Last issue we reported on a new generation of microscopes that will, because of their significantly lower price tags, allow more students and others to study micro- and nanoscience (see “Power microscopy for the masses,” Mar/Apr 2007, page 8). And breaking news on our way to print is that a new provision to U.S. competitiveness legislation authorizes use of National Science Foundation grant funds to acquire micro/nanotechnology equipment and software for teaching students in high schools, colleges, and universities.
Education is a top concern among industry players and observers. Another is the ability to process patent applications efficiently. In a recent online exclusive, Small Times’ publisher Patti Glaza reported on a nanotechnology roundtable discussion led by Under Secretary for Technology at the U.S. Department of Commerce Robert Cresanti (see “Cresanti leads nano commercialization roundtable,” at www.smalltimes.com). The report’s coverage of small-tech patent application review frustrations drew a handful of responses-one from Cresanti, himself, and another from John Doll, Commissioner for Patents.
Challenging one particular line in the report, Doll said, “It is not ‘strong union forces,’ but federal law, that makes it harder for the U.S. Patent and Trademark Office (USPTO) to recruit and retain patent examiners.” He also explained the USPTO’s new use of special law provisions to overcome the shortage of qualified examiners.
Doll then detailed work being done to fast-track patent-application review, including the provision for applicants to request accelerated examination, “guaranteeing a final examiner decision within 12 months in return for adhering to certain requirements.” He said his department knows that more must be done to ensure micro- and nanotechnology developers get decisions on their patent applications more quickly. And in the letter he announced that the USPTO is “seeking solutions from the public and those with a stake in the patent system through a series of town hall meetings and focus groups we will hold later this year.” When Doll and his team finalize plans for these meetings, they will be announced on the USPTO Website.
“We welcome the thoughts and suggestions of readers of Small Times,” Doll concluded. So send your thoughts and suggestions to me at [email protected], and I’ll pass them on to Doll.
Barbara G. Goode is editor-in-chief of Small Times. She can be reached at [email protected].
April 30, 2007 – Pricing woes continued in March across major markets in the semiconductor industry, which all saw sales decline despite higher unit shipments, according to the SIA’s latest monthly data. Overall chip sales managed to inch up in March and 1Q07, but are still well below expectations.
Global semiconductor sales (based on a 3-month moving average) rose 1% from February to $20.34 billion, representing a 3.2% increase from March 2006. Sales in the US continued to decline (-2.2% to $3.34 billion) while the Asia-Pacific region held mostly flat (-0.4% to $9.66 billion), while sales in Japan picked up due to the fiscal year’s end (+7.4% to $3.95 billion). Comparing year-on-year numbers, chip sales in the US declined by double-digits (-10.6%), while other regions showed small single-digit growth, led by the Asia-Pacific region with ~8% growth Y-Y.
Looking at actual numbers (no 3-month average), the March increase was significant — +31.8% in overall chip sales vs. February to $23.73 billion, with growth in Europe (24.8%) and the Americas (26%) trailing that of the Asia-Pacific (36.9%) and Japan (30.5%). Year-on-year, though, chip sales were up just 2.7%, as the Americas saw sales drop 11.2%, balanced by growth in Japan (10.8%) and the Asia-Pacific (5.8%).
Preliminary data for 1Q07 shows a 6.5% decline overall from 4Q06 to $61.02 billion, and 3.2% better than 1Q06. That’s well below the 10% growth that the SIA had predicted last November for 1Q07, and the group will likely reflect that new reality in its updated forecast in mid-June.
SIA president George Scalise noted that pricing pressures in major market segments including DRAM, DSP, and NAND flash all outweighed higher unit shipments. DRAM sales, for example, were down ~8% Q-Q, as 16% higher unit shipments were offset by ~20% ASP decline. Microprocessors also declined (nearly 13%), as unit sales declined while ASPs remained unchanged. Inventory pileups also were being addressed in 1Q, which added to the lower ASPs, Scalise noted, adding that all these factors spell great deals for consumers — a consumer PC now costs around $850, he pointed out.
“Despite recent signs of slowing growth in the overall economy, consumer spending on electronic products appears to have held up fairly well,” said Scalise, in a statement. He noted that another rise in gas prices seems to have not had an impact yet, but slower growth in China’s IT sector and recent numbers suggesting lower US GDP are points of concern to consider for the semiconductor industry’s near-term outlook.
April 30, 2007 – The market for chemical mechanical planarization (CMP) equipment and materials kept apace with the overall semiconductor equipment market in 2006, growing at about 24%, but despite a growing number of competitors two stalwarts still dominate the market, according to market research firm The Information Network.
After mirroring the overall chip tool sector’s growth (23%) in 2006, the CMP market should also move alongside it in 2007, with about a 3% decline, the firm noted, adding that the materials segment of CMP will grow ~15%.
Memory firms’ conversion to copper damascene for both DRAM and NAND flash operation will drive use of copper CMP slurries, said Robert Castellano, president of the market research firm. NOR flash manufacturers are already migrating to copper interconnects, to be followed by several NAND makers this year, he noted. On the DRAM side Micron is already using copper interconnects, with other DRAM manufacturers following suit later this year and into 2008.
Applied Materials and Rohm and Haas maintained their significant market leads in their respective CMP categories in 2006, according to the firm’s data. AMAT had ~70% share in CMP equipment, nearly 3x more than nearest competitor Ebara, notes the firm. Rohm and Haas led the CMP materials field, which includes slurries and pads, with about 41% share (followed by Cabot with 28% share), and an eye-popping 92% share in the pads segment.
April 25, 2007 – Kleiner Perkins Caufield & Byers (KPCB), a longtime fixture on the investment landscape of Silicon Valley, is acquiring Shanghai-based TDF Capital, and is committing $360 million to fund investments there, notes the San Jose Mercury News.
Areas of interest include high-growth industries such as technology, Internet, media and wireless communications, with possible investments in other areas including healthcare and “green” technologies. The business will be led by three TDF execs joined by Joe Zhou, formerly with Softbank Asia Infrastructure Fund.
Many US VC firms (including KPCB) typically travel to China to identify and locate possible investment opportunities, and often end up investing in domestic VC firms as a less-risky alternative to startups, the paper noted.
With the new China-based arm, KPCB will “see where technology and consumer markets are going in China, and […]where trends are heading in the US. As venture capital becomes global, we see these relationships as being very important,” noted KPCB partner Ellen Pao, quoted by the SJMN.