Category Archives: LEDs

BY SARANG SHIDORE, Flomerics, Inc.

imulation tools for thermal modeling of semiconductor packages have become routine in most design processes. Early spreadsheet tools have given way to sophisticated finite element analysis (FEA) or computational fluid dynamics (CFD) tools that interface mechanical CAD data directly into their analysis. Modeling is a necessary step, especially at early stages of thermal design, during which feasibility studies can narrow the spectrum of possible design choices. It is also used at later stages of the design for verification and design optimization.

A detailed thermal model (DTM) attempts to represent or reconstruct the physical geometry of a package to the extent that is feasible. Thus, the DTM will always look similar to the actual package geometry. Constructing a DTM in a thermal analysis tool is aided by the integration of part mechanical CAD data. A properly constructed detailed model is, by definition, boundary condition independent (BCI). For example, the model will accurately predict temperature at various points within the package – including junction, case, and leads – regardless of the cooling environment in which it is placed.

DTMs are suitable for use in design simulations consisting of few packages. For example, typical package thermal characterization problems – such as calculations to extract junction-to-ambient air thermal resistance (Θja) or junction-to-moving air thermal resistance (Θjma) – fall under this category. However, DTMs are not feasible for simulations of sub-systems or system-level computations involving numerous semiconductor packages because the computational resources required for solving large problems would be excessive if each represented a DTM package. These are the applications where a compact thermal model (CTM) should be used.

A CTM is a behavioral model that aims to predict package temperature accurately at only a few critical points – for example, junction, case, and leads – using far less computational effort. A CTM is not constructed by trying to mimic the geometry and material properties of the actual component. Rather, it is an abstraction of the component response to the environment in which it is placed. Most CTM approaches use a thermal resistor network to construct the model, in analogy with an electrical network that follows Ohm’s law. Two-resistor and a model developed by the Development of Libraries and Physical Models for an Integrated Design Environment (DELPHI) are two types of CTM in use today.

Two-resistor Compact Thermal Model

A simple, widely used CTM is a two-resistor model (Figure 1) consisting of a junction-to-board resistance (Θjb), and a junction-to-case resistance (Θjc). Both these parameters are defined by JEDEC as reference standards.1


Figure 1. A two-resistor compact thermal model.
Click here to enlarge image

Θjc is normally derived from a top cold plate test in which the package is placed on a board with all sides insulated except the top surface. A cold plate is pressed against the top surface at a specified temperature. Most of the power dissipated from the package leaves through its top (isothermal) surface. The one-dimensional equivalent of Fourier’s law is then applied to derive Θjc. Thus, Θjc = (Tj – Tcld)/P, where Tj is the junction temperature and Tcld is the temperature of the cold plate.

Θjb is derived by placing the package in a specially constructed harness called the ring cold plate (Figure 2). This fixture consists of a 4-layer PCB inserted between two cold plates in the shape of a ring. Thus, heat travels from the package through some distance within the board, and then out of the fixture through the coolant fluid in the cold plate.


Figure 2. Fixture for measuring Θjb.
Click here to enlarge image

Rjb is calculated by using the one-dimensional version of Fourier’s law: Θjb = (Tj – Tb)/P. The board temperature (Tb) is taken as the temperature at a point on the board surface located in the middle of the longest side of the package, no more than 1 mm from the package edge for an area array package, and on the center lead foot for a surface-mount leaded package.

A two-resistor model has a simple and intuitive structure. It can be created from existing test data and result in a significant increase in accuracy when predicting junction temperature as compared to traditional single-resistor metrics such as Θja.

DELPHI Compact Thermal Model

Coming up with a generalized methodology to generate a BCI CTM was a compact modeling challenge. To that end, the DELPHI consortium, made up of a number of primarily end-user companies, concluded a publicly funded research project that led to the first comprehensive methodology for the generation of BCI compact models.2 One of the key advantages of the DELPHI methodology is that it is non-proprietary and vendor/tool independent. The DELPHI method was followed up by the Supplier Evaluation and Exploitation of DELPHI (SEED) project, in which component suppliers evaluated the DELPHI model and found that it could be used satisfactorily as a predictive tool for junction temperature.3


Figure 3. A typical DELPHI compact model topology.
Click here to enlarge image

DELPHI compact models (Figure 3) are made up of several thermal resistors that connect a junction node (representing the die) to several surface nodes. Thermal links are also allowed between the surface nodes (shunt resistors).

The resistor network is derived from a step-by-step simulation and statistical optimization process that minimizes the error in junction temperature and heat flux over a wide spectrum of environments such as high-/low-conductivity PCB, bare package, package with heatsink, natural convection cooling, and fan cooling. The end result is a CTM that provides a predictive accuracy of junction temperature and major fluxes to within 10% – a major improvement over the accuracy of a two-resistor model.

The use of two-resistor and DELPHI CTMs is becoming wide-spread in the industry, just as the standardization process for these methodologies is at its final stages.

Emerging Standards for Thermal Modeling

Thermal design in the electronics industry is often an afterthought in the product cycle. Some organizations have been successful in bringing this task to an earlier stage. Still, in many cases, thermal engineers often have to work in a reactive rather than proactive mode.

This will no longer be the case in a well-integrated design chain wherein there is a seamless transfer of data and other information between semiconductor suppliers and system integrators. However, there are challenges that lie ahead before this can occur. Universal standards must be established, and a seamless data communication pathway between semiconductor suppliers and end-users must be created.

The possibility that thermal analysis environments in various stages of a design chain may experience interoperability problems means that data exchange is a huge issue. The creation of sensible and universal industry standards for thermal modeling of semiconductor packages forms the key challenge.

The need for standards is understood. The challenge is to evolve them in ways that gain universal acceptance among vendors. This means they must not give an implicit advantage to any one vendor. At the same time, technology contributions by vendors that help define standards must be taken into account.

JEDEC has been busy working on this challenge. The JC15.1 subcommittee has put thermal data exchange standards at the top of its priority list. The JC15.1 roadmap for 2006-07 includes three overview guidelines for thermal modeling of semiconductor packages: a modeling overview, a compact thermal modeling overview, and a terms and definitions document for thermal modeling. The overview documents are designed to lay out the framework of subsequent guidelines and standards for thermal modeling of semiconductor packages. They also familiarize a designer new to thermal modeling with the terminology and fundamental principles in the field.

A guideline for a two-resistor CTM lays out the theoretical framework of the two-resistor model, its definition and construction, and also provides a recipe for its use in practical design applications. A guideline for a DELPHI CTM lays out the theoretical framework of the DELPHI methodology and explains how it could be applied to generate BCI models of typical packages. The vendor-neutral CTM data standard facilitates seamless exchange of data between semiconductor manufacturers and system integrators (end-users).

Future Developments

Preparatory work has commenced on standards for dynamic CTMs, i.e., those used for time-dependent simulations. A guideline document for detailed thermal models is also being developed.

The maximum benefit of the CTM approach hinges on the willingness and ability for semiconductor manufacturers to provide ready-to-use libraries in an accessible format. The idea of on-line libraries is attractive, but is still not a reality due to the lack of comprehensive thermal standards and issues regarding data security and access. However, the emerging JEDEC standards and the increasing penetration of collaborative design practices among all industry tiers may change the situation.

REFERENCES

  1. www.jedec.org
  2. Rosten H., Parry J., Lasance C. J. M. et al, “Final Report to SEMI-THERM XIII on the European-Funded Project DELPHI – The Development of Libraries and Physical Models for an Integrated Design Environment,” Proc. of the Thirteenth IEEE SEMI-THERM Symposium, Austin, TX USA, January 28-30, 1997.
  3. Pape H., Noebauer G., “Generation and Verification of Boundary Condition Independent Compact Thermal Models for Active Components According to the DELPHI/SEED Methods,” Proc. of SEMITHERM XV, 1999, San Diego, CA, pp. 201-211.

SARANG SHIDORE, director of web business, may be contacted at Flomerics, Inc., 1106 Clayton Lane, Suite 525W, Austin, TX 78723; 512/420-9273, ext. 203; E-mail: [email protected].

Farewell to industry peer


February 27, 2007

Our condolences to family and friends of Dr. Doug Smeaton, president and CEO of Semiconductor Insights, who passed away on Feb. 18 after a diving accident. He served as president/CEO of the firm since 1992, led its management buyout in 1994, and oversaw its expansion from just over a dozen employees to over 155. Before joining Semiconductor Insights he was SVP and GM of Mitel Semiconductor (now Zarlink Semiconductor) and president/CEO of Anatek Electronics.

Smeaton was a current or past director at a number of technology companies, including SiGe Semiconductor, Triant Technologies (listed as TNT on the TSX), Skystone (acquired by Cisco), Philsar (acquired by Conexant), Sybarus (acquired by Lucent), SiGem (now Mobile Knowledge), MuAnalysis, and Symagery Microsystems (acquired by Psion Teklogix).

Donations in his memory should be made to the Ottawa Mission (www.ottawamission.com), a local charity that assists homeless people.

February 23, 2007 – Mosaid Technologies Inc. is bowing out of the automatic test equipment (ATE) market, selling assets and IP related to its high-performance memory tester platform to Teradyne Inc. for about US $17 million.

Teradyne will take on the company’s Systems Division new product development team and receive an exclusive license to certain IP associated with Mosaid’s current ATE product lines. Teradyne, which termed the assets “enabling test technology,” also said it will “immediately expense a substantial portion” of the purchase price to in-process R&D.

Mosaid, which will generate a pretax gain of ~$11 million and net cash proceeds of $13-$14 million, will wind down its remaining ATE business by April 30, with ongoing support for its installed base of tester products to be handled through alternate service providers.

“Challenging business conditions within this market, coupled with our strategic emphasis on intellectual property, led to this divestiture,” said George Cwynar, Mosaid president and CEO, in a statement. He noted that the move “is a critical step in our strategic alternatives initiative” and allows the company to sharpen its focus on developing and licensing its intellectual property.

February 20, 2007 – Showa Denko KK says it has developed a new hybrid process for making compound semiconductors based on gallium nitride (GaN) and other nitrides, using a combination of conventional metal organic chemical vapor deposition (MOCVD) and a proprietary plasma-assisted physical deposition.

The new process technology enables production of 4-in. epitaxial wafers with higher quality than is achievable with MOCVD alone. Showa Denko claims to have made blue LEDs using the hybrid process “with the highest-level brightness on the market today,” and to start shipping commercially “within this year.”

Analyzed via an X-ray rocking curve (XRC) method, the layer of single crystal nitride formed on a sapphire substrate produced by the PPD process shows significant improvement in crystal quality over a similar product produced by the MOCVD process, the company claims (see figure below).

A new facility will be built at Showa’s site in Chiba, Japan, to produce the 4-in. epi wafers based on the new process technology, and the company will more than triple its output of blue LEDs from 30 million units to 100 million units/month by year’s end.

by Matt Wickenheiser, Contributing Editor

Advanced process materials and the continued adoption march of 300mm are driving materials growth in 2007, and fabs seem to be finally learning to make smarter purchasing decisions, according to top analysts tracking the market, interviewed by WaferNEWS. Potentially troubling signs seem to be offset by mitigating factors — yet there is still no short-term answer for stretched-to-the-limit polysilicon demand, particularly from the solar segment.

Semiconductor Equipment and Materials International (SEMI) is forecasting 7.1% growth in the worldwide fab materials market for 2007 (to $22.59 billion), a drop from the 16.9% growth of 2006 that reflects slower growth in chip unit demand, according to Dan Tracy, senior director of industry research and statistics (see table, above).

On the packaging materials side, SEMI said it sees 13% growth in 2007, with the market hitting $16.64 billion, up from $14.73 billion in 2006. Combined, that’s an overall materials market of $39.23 billion forecast for 2007, and a record $35.82 billion in 2008, SEMI noted (see table, below).

Looking ahead, SEMI expects a $25.58 billion fab materials market in 2008 (13.2% growth) and a $26.82 billion market in 2009 (4.9% growth). On the packaging side, SEMI forecasts $18.24 billion in 2008 (9.6% growth) and $20.46 billion in 2009 (12.2% growth).

Key growth drivers in ’07 on the fab materials side include 300mm and SOI, as well as advanced process materials, including 193 photoresists, anti-reflective coatings, CVD precursors, and CMP consumables, said Tracy. “Besides fab materials, many of these new devices are used in portable electronics and have resulted in a tremendous change in the types of materials used in packaging from new substrates, new wire technologies, new die attach materials and more.”

Techcet Group LLC also forecasts 8% growth in total semiconductor process materials in 2007, to $37.1 billion, as the segment shrugs off rumors of a market slowdown. “Word on street on the materials side is the fabs have learned their lessons from the past and have prevented themselves from double-ordering the last six to nine months,” Lita Shon-Roy, senior market analyst, told WaferNEWS. “Now, when wafer production is slower they don’t have to yank out orders from under suppliers’ feet.” Higher-tech materials such as CMP and high-k will continue to growth faster than other materials such as gases, wet chemicals, or quartz, she added.

Polysilicon demand still a short-term risk

Device buildups and a temporary decline in fab utilization rates could potentially cast a shadow on silicon wafer demand in the latter part of ’07, according to Takashi Ogawa, Gartner Dataquest’s semiconductor manufacturing research director. But the semiconductor industry’s emphasis on cautious operation management in recent years means that any market change by device inventory adjustment “will have a short-term, temporary influence over wafer demand,” especially between late 2006 and early 2007, he said.

Wafer demand will still be slow in 1Q07, Ogawa suggested, but under the most likely scenario, Gartner thinks that 300mm wafer demand will remain firm throughout 2008, though temporary shortages may be inevitable in the small-diameter market segments, as well as in some local markets and for some customers. Silicon will recover beginning in the second quarter because of a seasonal increase in production demand, he continued, and annual demand is expected to see 8% growth in 2007.

Red flags are still being waved over polysilicon availability in the near-term, with new silicon wafer fabs in the works but not expected to be online until 2009. “Although the latest forecast indicates that wafer demand will soften in early 2007, it by no means justifies us to ‘call off the alert’ in terms of a polysilicon shortage,” Ogawa said.

Karey Holland, Techcet’s senior managing partner, noted that there’s been high demand for polysilicon for solar energy use — “It’s just been sucking the stuff away.” The firm believes silicon consumption will experience moderate growth in 2007, between 7%-8%. SEMI’s Tracy noted that in addition to capacity expansions to help relieve pressures, solar cell makers are looking to develop alternative sources for polysilicon, such as metallurgical grade polysilicon and new suppliers.

One impact of polysilicon tightness on the semiconductor side that has not been heard about much is the effect on fab process tools, Tracy added. “Some equipment requires consumable components processed from high-purity silicon and the current market conditions have resulted in some supply challenges in this area,” he said.

New developments in CMP, CVD

Elsewhere, the silicon carbide (SiC) wafer market will see 20%-25% growth in 2007 thanks to increased use for LEDs by companies like Cree, as well as for discrete devices such as Shottkey barrier diodes, IGBTs, and power devices for RFID, said Shon-Roy. For high-brightness LEDs, indium gallium nitride (InGaN) is grown on SiC wafers to manufacture blue-white LEDS.

In the area of CMP, Techcet estimates slurry revenues of >$700 million in 2007, and pad revenues of >$500 million, with two main driving factors. As fabs move toward some type of selective polish for shallow trench isolation they are abandoning standard oxide polishes (at $12/gallon) in favor of selective polishes such as cerium oxide-based ones or silica with additives ($30-$50/gallon), and that bumps up the entire slurry market. Selective STI processes will allow fabs to transition from a multistep STI process to direct CMP of the STI oxide, Holland said. Whether eCMP will start taking a significant part of the slurry market as the industry moves down to 32nm processes is still up in the air, she noted.

The other change seen in the CMP market is increased competition, where there are currently 20 companies trying to take market share from big players Rodel and Cabot, said Holland.

In CVD low-k dielectrics, 3MS (trimethylsilane) is estimated to have over 50% market share, much attributed to Applied’s Black Diamond process, and end-user feedback suggests the transition to Black Diamond-2 is going to go well, according to Techcet’s Holland. Most end users are not using 3MS for BD2 and are not saying what the precursor is, she noted, adding that the industry would see about a 10% reduction in cost/gram of other precursors.

In the photoresist segment, there’s a lot of business in 90nm resist with “very, very high-added-value materials,” noted Shon-Roy. Techcet sees the worldwide photoresist market at $1.2 billion in 2007, increasing to about $1.3 billion in ’09. Costs will jump fivefold when fabs transition from KrF for 248nm for lithography to ArF for 193nm, and going to 14 layers of copper means engineers have to do litho on each layer, increasing use of the material, added Holland.

Recouping development costs still No.1 focus

Expanded use of increasingly complex and expensive materials brings up the No.1 concern of material suppliers — the cost-down pressures companies face, and the challenge of realizing a return on their investment for all the new technologies they are being asked develop and bring to the market, noted Tracy. “In this environment there are downward pricing pressures for both older and newer materials, and this affects decisions of how and where suppliers will spend money to innovate new material technologies,” he said.

He suggested that the demands for tailored materials made by newer devices and process technologies is a challenge for both fab and packaging material suppliers. The result is lower volumes of highly engineered materials are required by a given customer, he said — instead of the high volumes that have traditionally generated the payback to materials suppliers. These niche technologies can be less attractive to the larger suppliers who need a return good enough to justify the investment to their stockholders.

“A potential consequence is that more competition could emerge as this creates an opportunity for smaller, quicker players with lower overhead and new ideas to possibly introduce new materials,” said Tracy. M.W.

February 16, 2007 – Advanced Semiconductor Engineering Inc.’s chairman/CEO Jason Chang and a consortium led by the Carlyle Group that has offered to buy the packaging services firm, have agreed to drop the proposed exclusivity clause and breakup fee arrangements as a condition to the proposed deal — essentially allowing ASE to shop for other deals without penalty.

The changes were requested by Chang and the evaluation committee formed to mull over the ~$5.5 billion acquisition proposal by the Carlyle consortium.

Forbes speculated that the change in terms may be due to pressure from the Taiwan government, as a move to check ASE and Carlyle’s possible motivation to circumvent Taiwan restrictions on investments in China by listing on a foreign market (e.g Hong Kong) and sending investments into China from there.

Investors approve of the move, sending the company’s stock (via American depositary receipts) up nearly 4% on the news, the paper pointed out.

By Tom Cheyney
Small Times Contributing Editor

Feb. 15, 2007 — As the first commercial flexible electronics reach consumers, many significant manufacturing and technological obstacles must be overcome for the market to reach its multibillion-dollar potential over the next five to 10 years. This was one of the key themes at the U.S. Display Consortium‘s sixth annual Flexible Display & Microelectronics Conference, held last week.

The conference broadened its focus beyond flexible displays this year, adding photovoltaics, RFIDs, sensors, LEDs, and other organic and printed electronics to the topical mix. The event organizers also increased the number of technical sessions, with parallel tracks for manufacturing and thin-film transistor (TFT)/flex technologies convening during the second day.

The manufacturing track was particularly well attended, with presentations by Hewlett-Packard, Philips, and Applied Materials focusing on the development and differentiation of roll-to-roll and batch-style processing techniques. Papers from Semprius, Kodak, and Fujifilm Dimatix detailed efforts to adapt inkjet and classic printing techniques to flexible electronic applications.

The popularity of the manufacturing sessions also reflected the pioneering efforts by Polymer Vision, Plastic Logic, and other companies to move from the lab or pilot-line stage to volume production. Citing a long-term goal of putting “a rollable display in every mobile device,” Polymer Vision CEO Karl McGoldrick described his company’s efforts to bring its ultrathin-film-transistor polymer display module to market.

Polymer Vision, which spun off from Philips late last year, has announced it will ramp up a Southampton, U.K., manufacturing facility (in partnership with Innos). The company has also entered into an agreement with Telecom Italia to “bring the ‘cellular book’ to market.” Models of what the company touts as the “world’s first commercial rollable display product” were to be unveiled at the 3GSM World conference in Barcelona this week, according to McGoldrick.

Company CTO Edzer Huitema told Small Times that a blend of refurbished and new AMLCD equipment will be deployed, as well as a proprietary lamination/delamination tool, in its Class 100 production facility (scheduled to come on line later this year). He said they are “on spec for creating the product,” with field-effect mobility and driving voltages comparable to conventional TFT devices. Although it is early, yields appear to be sustainable throughout the process flow. Defect sources, which are “comparable to those found in LCD manufacturing,” are “under control.” Ongoing quality control work is focusing on materials purity and various types of insulator layers, he added.


A prototype Plastic Logic e-book at the Flexible Display & Microelectronics Conference. (Photo: Tom Cheyney)

Bolstered by a recent funding round of $100 million, Plastic Logic plans to build and equip a green-field factory site in Dresden, said Simon Jones, VP of product development. The company expects to have “product-quality modules” of its “take anywhere, read anywhere thin, light, robust e-paper displays” by mid-2008, with a production target of more than 1 million 10-in.-equivalent units for 2009.

Plastic Logic’s direct-write, room-temperature process requires no mask alignment and can be scaled to a large substrate size. Jones explained that the company “measures contrast and yield on every panel” and has “captured a huge amount of defect data,” which is “essential for the move from R&D to production.”

During his presentation on the alignment of market forecasts, manufacturing capacity, and investments in organic, plastic, and printed electronics, cintelliq‘s Craig Cruickshank offered a sober assessment of the prospects for manufacturing. He said that, other than in the organic LED (OLED) sector, “the industry will take longer to commercialize than currently anticipated.”

Cruickshank’s data showed that despite the recently announced factory investments, “significant production capacity will need to be built over the next three years to satisfy demand by 2010/2011.” Nearly $800 million will be necessary over the next three years “to build the capacity needed¿to meet the forecasts.” As a result, device and materials companies “need to decide whether to enter production in the next year or so.” He also noted that government investments in the industry in Europe and North America “still exceed the accumulated venture capital funding,” which suggests that the industry remains in R&D mode.

by James Montgomery, News Editor

Applied says the beamline implant business won’t return enough profits to justify future R&D investments, but the decision may also be just as much about the dynamics of a fiercely competitive market segment — and possibly another implant card up the company’s sleeve.

Faced with what it claims is a business that would generate unacceptable returns on significant future R&D investments, Applied Materials Inc. says it will cease development of beamline implant products, and close its Applied Implant Technologies group in Horsham, UK. Support including new and refurbished tools will be phased into Applied’s global services arm. About 270 employees, located primarily in Horsham, will be affected by the closure, which is expected to be completed by year’s end at a rough cost of $90-$130 million.

Essentially, Applied didn’t see much of a profitable return to justify the R&D investments for a technology for which there “hasn’t been a major structural change…for a long time,” and in the end it was a “pretty easy decision” to cease future investment, according to Tom St. Dennis, Applied’s SVP and GM of etch, cleans, frontend, and implant products business groups, in an interview with WaferNEWS. “The technology was probably in many ways on that trajectory for some time,” and that’s been reflected in how customers are dictating their pricing, and thus the overall profitability of the tools, he said.

Trying to somehow monetize the technology via M&A or a JV was also deemed unfeasible — integration and product portfolio management is long and expensive, he pointed out, and “you quickly get to billions of dollars of investment, but what’s the likely return on that?” he asked. “It’s better to put your money in T-bills.”

Applied will continue to invest in other development work going on for implant technologies outside of beamline, St. Dennis noted, without elaborating on what those products are or when/where they might be brought to market. But it’s likely that, based on known technology development, those efforts likely target plasma-doping tools, which are based on IP from Silicon Genesis per a 1999 agreement (and originally developed and tested at UC-Berkeley).

“I was surprised” by Applied’s announcement, noted Risto Puhakka, president of VLSI Research, telling WaferNEWS that he believes Applied’s beamline tools have achieved “a reasonably strong position with key accounts.” The company’s exit from high-current implant, he surmised, is probably as much about the rise of a key competitor as it is an investment decision. In 2004 Applied led the high-implant market with $225 million in revenues, followed by Varian Semi. Equip. Assoc. with just $130 million, according to VLSI’s data. But in 2005 Varian surged to the top spot with ~$230 million, while Applied fell to second place ($200M), with Sumitomo Eaton Nova and Axcelis Technologies trailing behind. Data from Gartner Dataquest (see table below) suggests a similar marketplace shuffle.

Numbers for 2006 aren’t in yet, but Puhakka expects Varian to have continued to gain share at the expense of other suppliers, particularly as more chipmakers push into leading-edge process technology.

“Varian with their single-wafer technology was able to create a pretty sizeable technological differentiation advantage, especially going to 90nm and 65nm,” Puhakka told WaferNEWS, pointing to the need for high angles and precise controls. “It’s hard to say that ‘this tool is better than that tool,’ but Varian has been gaining share steadily.”

With Applied bowing out of future high-implant tool development, that leaves three suppliers battling for bragging rights, and essentially only two alternatives depending on where customers are located, Puhakka said. In Japan, the choice is between Varian and mainly domestic supplier Sumitomo Eaton Nova; and everywhere else it’s a race between Varian and Axcelis. — J.M.

(February 12, 2007) REDWOOD CITY, CA &#151 EoPlex Technologies closed Series C financing with $8 million in investments, led by ATA Ventures. The company plans to expand design and manufacturing capacities, and increase its customer base, with the funding.

February 9, 2007 – Advanced Semiconductor Engineering Inc. has appointed financial advisors and legal counsel to help evaluate the buyout offer proposed late last year by a consortium of investors, suggesting negotiations have taken a significant step forward, according to media reports.

The ASE evaluation committee, led by director TC Cheng, has retained Morgan Stanley Services Ltd as financial advisor, Davis Polk & Wardwell as US counsel, and LCS & Partners as Taiwan counsel, according to AFX and the Taiwan Economic News. Goldman Sachs is representing the Carlyle Group, which aims to delist ASE from the Taiwan market and relist it as several spinoffs, the Taiwan paper noted, adding that Carlyle has resisted ASE investors’ requests to up its offer of NT$39/share.

Now that the consulting panel has been formed, ASE is expected to begin formal negotiations with Carlyle over concrete terms of the acquisition, the paper noted.

In November, a consortium led by private equity firm The Carlyle Group proposed a $5.46 billion acquisition of ASE, which was interpreted as a possible move to accelerate the company’s expansion into China by relisting offshore and avoiding Taiwanese trade restrictions with the mainland. The Carlyle Group was also involved in deals earlier in 2006 for Freescale Semiconductor and Jazz Semiconductor.