Category Archives: LEDs

LED market discussedWith increasing awareness of global climate change and the importance of energy conservation, more and more countries have launched LED lighting projects and subsidy policies. As a result, even though the growth of the LED market in 2012 was hampered by global economic challenges, overall demand has continued to be on the rise. To help the Taiwan LED industry tackle the increasing challenges, an in-depth analysis of LED global market opportunities and technology breakthroughs were recently provided at the 2013 LED Market and Outlook seminar held by SEMI Taiwan.

Demand for high-power white LED is now growing at a rapid pace. Yellow and natural light LEDs will both exceed 200 lumen/watt in power rating by 2015 and even surpass 250 lumen/watt by 2020. OEM bulb prices are expected to drop from US$ 23 per 1,000 lumen in 2012 to $10 per 1,000 lumen in 2015 and then down to $5 per 1,000 lumen by 2020. The next few years will therefore see strong growth in the LED lighting market.

LED lighting market continues to grow from 2011 to 2016

Daphne Kuo, an analyst with ITRI Industrial Economics & Knowledge Center, added that the global market for general lighting has an annual growth rate of between 3 and 6%. The global market is expected to be worth $114.7 Billion in 2020, with the LED lighting market reaching a compound annual growth rate of 45% between 2011 and 2016, and 15% between 2016 and 2020. The LED lighting market could therefore reach a value of $79 billion.

In terms of the LED lighting market structure, LED home lighting will be the largest market in 2020 at $32.1 billion accounting for 41 percent of the total LED lighting. The next two largest markets will be outdoor and office lighting, with both approaching $11.3 billion. The overall market will itself be divided into the new installation market and the replacement market. The relative scale of the two markets is approximately 80:20. The scale of the replacement market is however expected to begin contracting after 2015 as LED penetration increases and lighting technology improves.

Different regions show different approaches to LED market

According to Kuo, currently Western nations account for 50% of the general lighting market and the Asian market accounts for 40%, so these two large regional markets remain evenly balanced. However, future growth will be driven mainly by emerging nations, and the BRICs in particular, because of strong government support for LED lighting. China will be the largest among them and account for approximately 70% of the BRIC lighting market. The China market is estimated to account for 45% of all demand in Asia, or 18% of the global lighting market.

Nevertheless, demand for LED lighting in China mainly comes from government projects. With local firms and governments joining forces to protect their vested interests, it is very difficult for outside firms to make any headway. Any company wishing to enter the China market must pay attention to the parochial nature of the lighting market. Adopting a profit sharing model and establishing a solid partnership with regional lighting channel operators is essential when entering the LED lighting market in China.

Keys to market: Lower production cost and improve efficiency

In addition to the market challenges, there will also be a number of technological challenges in the future. EPISTAR’s Carson Hsieh noted that solving problems with thermal resistance remains the number one priority. The current trend is using Flip-Chip technology to reduce chip-level thermal resistance. Another approach is to improve light emission efficiency. Light emission efficiency is in turn governed by internal quantum efficiency and light extraction efficiency. While improvements have been made in internal quantum efficiency, factors such as material absorption, uneven current distribution, and threshold loss mean that even high internal quantum efficiency within the LED produces relatively little external light. The bottleneck in LED light extraction efficiency must therefore be overcome.

The current trend is using Patterned Sapphire Substrate (PSS) technology as it has the advantage of increasing LED light extraction efficiency. Another method, called Nano Patterned Sapphire Substrate (NPSS), not only increases light extraction efficiency but also boosts epi wafer output. Increasing light extraction efficiency will not only boost overall light emission efficiency but also reduce thermal loss, allowing LED bulbs to do away with heat sinks and reduce costs even more.

By using GaN LED on Si technology to grow the epi layers on large silicon wafers, it will also be possible to adopt a production process that is compatible with semiconductor production lines and significantly reduce overall costs as well. However, GaN has a far higher thermal expansion coefficient than silicon so this may lead to technical problems such as epitaxial film rupture or wafer warping that will need to be overcome in the future.

Technology breakthroughs lead to further reductions in LED costs. This will in turn increase market acceptance and usher in of the era of high growth for the LED lighting market.

Agilent Technologies Inc. announced yesterday the intent to donate $90 million in software to Georgia Institute of Technology, the largest in-kind software donation ever in its longstanding relationship with the university.

“Georgia Tech is among the best research universities in the world, offering the largest, most diverse electrical and computer engineering program in the United States and regularly turning out the largest number of engineers in America,” said Steve McLaughlin, chair of Georgia Tech’s School of Electrical and Computer Engineering. “Maintaining that position requires the best teachers and facilities and, increasingly, key partnerships with companies like Agilent. Thanks to Agilent’s support, our students now have access to the industry’s leading software and hardware tools.”

Last year, Georgia Tech dedicated a new laboratory to Agilent after the company made a substantial donation to the university’s School of Electrical and Computer Engineering (ECE).

Agilent’s latest in-kind donation is valued at approximately $90 million over three years and will comprise Agilent EDA software, support and training. The donation is being given as part of the Agilent EEsof EDA University Alliance program. It includes a tailored, three-year custom license program that provides member companies of ECE’s Georgia Electronic Design Center with access to Agilent’s EEsof EDA solutions.

“This is one of the largest academic donations of Agilent EEsof products to a single institution and the largest software gift Georgia Tech has ever received,” said Todd Cutler, general manager with Agilent EEsof EDA. “We realize that universities and start-up incubator programs play a crucial role in pushing the limits of EDA tools; feedback from our partnership with Georgia Tech helps us target our development investments to make sure our products support leading-edge technology development.”

Academic uses of Agilent EDA software will focus on Agilent EEsof’s Advanced Design System and SystemVue solutions. ADS is the world’s leading electronic design automation software for RF, microwave and high-speed digital applications, pioneering innovative and commercially successful technologies such as X-parameters and 3-D electromagnetic simulators. SystemVue is Agilent’s premier platform for designing communications systems. It enables system architects and algorithm developers to innovate the physical layer of wireless and aerospace/defense communications systems and provides unique value to RF, DSP, and FPGA/ASIC implementers.

A new report from IHS Displaybank examined a total of 483 patents on roll-to-roll processing technologies, focusing on 32 that were flexible, OLED-related. 43 flexible OLED-related roll-to-roll application technologies and 23 roll-to-roll patents by SiPix were also selected for an analysis. 

A flexible display is considered as the next-generation display that is bendable and rollable without damage, by using a paper-thin and flexible substrate. The flexible display market is projected to lead the market growth by creating a new display market as well as by replacing the current display market. In addition, when producing flexible displays, if a large-area and low-cost technology based on the roll -to-roll process is realized, new demands with such as indoor/outdoor advertising and various decorative purposes are expected to be created.

The roll-to-roll process is a foundation to mass produce flexible electronics applications at low cost. It is a greatly demanded technology in the related-product manufacturing industry. The technology at the present level allows high speed printing, but the ink viscosity and the resolution vary depending on the printing method, and the equipment research on the device manufacturing process has not yet conducted enough.

The report contains the application trend and in-depth analysis of key patents on the roll-to-roll processing technology.

Looking at the application trend of 483 patents on roll-to-roll processing technology, the number of applications has continuously increased since mid 2000s, and many were applied in the U.S. Major applicants include 3M Innovative Properties, SiPix Imaging, Fuji Film, and General Electric. Amid vigorous developments of roll-to-roll processing technologies, competition among companies in the U.S., Japan, and South Korea gets increasingly fierce.

Roll-to-roll Processing Technology Patent Application Trends by Year/Country

 

Source: Displaybank, “Key Patent Analysis—Flexible Roll-to-roll Processing Technology”

Of a total of 483 roll-to-roll processing technology patents, 23 flexible OLED-related U.S. published/issued patents and 9 international patents were extracted as key patents. In-depth analyses were conducted on the 32 key patents after divided into the roll-to-roll manufacturing processing technology and apparatus technology. The key patent analysis includes key patent status, technology development map, and abstract.

Five University of California, Riverside professors will receive a total of $5 million as part of a $35 million research center aimed at developing materials and structures that could enable more energy efficient computers, mobile phones, and other electronic devices.

The research center, which will be called the Center for Function Accelerated nanoMaterial Engineering (FAME), will be located at UCLA and led by Jane P. Chang, a professor of chemical and biomolecular engineering at UCLA.

Four professors from UC Riverside’s Bourns College of Engineering are part of the center: Alexander A. Balandin, Alexander Khitun, Jianlin Liu and Roger Lake, all of whom are part of the electrical engineering department and materials science and engineering program. Jeanie Lau, a professor of physics and astronomy who is also part of the materials science and engineering program, is the fifth professor. Each professor will receive about $1 million.

FAME is one of six new university microelectronics research centers recently established with $194 million over the next five years from the Semiconductor Research Corporation (SRC) and the Defense Advanced Research Projects Agency (DARPA). The funding supports the continued growth and leadership of the U.S. semiconductor industry.

The other five centers will be located at UC Berkeley, University of Michigan, University of Notre Dame, University of Illinois at Urbana-Champaign and University of Minnesota.

The University of Minnesota center is called the Center for Spintronic Materials, Interfaces and Novel Architectures (C-SPIN). Three UC Riverside researchers – Roland Kawakami, Ludwig Bartels and Cengiz Ozkan – received a total of $3 million as part of that center.

The goal of the FAME center is to create and investigate new nonconventional atomic scale engineered materials and structures of multi-function oxides, metals and semiconductors to accelerate innovations in analog, logic and memory devices for the semiconductor and defense industries.

The center includes 35 faculty researchers from 16 universities: UCLA, Columbia, Cornell, UC Berkeley, MIT, UC Santa Barbara, Stanford, UC Irvine, Purdue, Rice, UC Riverside, North Carolina State, Caltech, Penn, West Virginia and Yale.

Balandin, Lau and Liu will focus on van der Waals materials – a broad range of crystalline solids with layer structures. The van der Waals materials include graphene, topological insulators and charge-density wave materials. It is expected that this class of materials can be used in future information processing.

Thomas Edison invented the first incandescent light bulb 130 years ago, which greatly contributed to the advancement of civilization. However, that technology is antiquated, economically inefficient to operate, and fragile.

Fluorescent lights are energy efficient but they are bulky and have to ‘warm-up’ when turned on. Their bulbs contain phosphorus and mercury, which are toxic to the environment. Today’s LED lights are also energy friendly but are expensive and difficult to manufacture. The process to make conventional LEDs is very complicated, as it involves the growth of single crystal layers on the single crystal substrate. Each layer has to contain low defects for it to work. The cost of LED lights is usually ten times the cost of the incandescent bulb, because the equipment to produce them is expensive, the raw materials are expensive, and the environmental and safety issues are critical. Another disadvantage of the current LEDs is they do not produce white light from a single chip. This requires extra manipulation, such as using a set of 3 chips emitting different lights or adding a phosphors material to the blue or UV chip to produce the white light. 

Professor Yue Kuo of the Artie McFerrin Department of Chemical Engineering at Texas A&M University has fabricated a new type of LED, capable of producing a wide spectrum light while operating for long periods of time at atmospheric conditions. This device is based on a new concept of light emission from an ultra-thin amorphous dielectric layer.     

Figure (left) Low- and (right) high-magnification photos of light emission from the new LED.

An article published in Applied Physics Letters, describes the light emission mechanism, characteristics of the emission spectrum, fabrication method, and the operation parameter effects on this type of LED. The device was fabricated with the room-temperature sputter deposition method on a silicon wafer. The light emission intensity could be enhanced with a nanocrystal layer embedded in the dielectric film. Most importantly, the complete process and materials are compatible with the existing IC fabrication facility.

“There is a need for a new type of LED that is: low cost, long operation life, small in size, emits white light, and easy to fabricate with environmentally friendly materials and process.” Dr. Kuo says. “ What makes this new LED unique is it meets all of these requirements plus it is extremely easy to fabricate with the existing equipment in all semiconductor fabs.” 

The light emitted is composed of small bright dots evenly distributed across the electrode surface.  The input voltage controls the intensity or brightness of the LED.  Dr. Kuo is very optimistic with the results of his findings. “We have discovered this phenomenon and studied this kind of LED for more than a year. It can be operated continuously for more than ten hours. A longer operation time is expected.”

Kuo‘s discovery has larger implications than just lighting. These LEDs could potentially be integrated into a computer processor; dramatically increasing the speed by transporting signals optically rather than by electrons through copper lines.  They could have use in various industries, entertainment, medical, commercial, and military areas due to the compact size and low cost. 

January 15, 2013 – The semiconductor industry is undergoing massive transformation as the rise in mobile computing, changes to the fabless-foundry model, uncertainties in technical innovation, and global macroeconomic trends become the dominant forces in 2013 and beyond, according to industry leaders speaking at the SEMI Industry Strategy Symposium (ISS), opening this week in Half Moon Bay, CA.

Ajit Manocha, CEO of GlobalFoundries, during his keynote presentation discussed the dynamic technology and economic needs of mobile computing that is driving new approaches to the chip design-to-production cycle. Calling it "Foundry 2.0," he sees outsourced semiconductor manufacturing moving toward a more IDM-like model, creating new collaboration models and techniques to close the gap between process teams at foundries and design teams at the fabless companies. With daunting technical challenges like 3D stacking, 450mm fabs, new transistor architectures, multi-patterning, and the uncertainties to lithography-based scaling, product development paths with virtual teams will evolve and adapt rapidly in the coming months and years.

With new fabs now costing upwards of $8 billion and leading-edge manufacturing investments expected to exceed $40 billion this year alone, global economic trends and forces — increasingly influenced by uncertain consumer spending in both developed and emerging markets — have never been more important to the semiconductor ecosystem. Dr. John Williams, president and CEO of the Federal Reserve Bank of San Francisco, said "Many businesses are locked into a paralyzing state of anxiety."

Williams used the ISS conference to lessen uncertainty and anxiety in the capital markets, pledging to keep interest rates near zero until the unemployment rate drops to 6.5%, as long as inflation expectations do not climb above 2.5%.

Bruce Kasman, chief economist and managing director of global research at JP Morgan, shared a positive economic outlook, especially in the second half of the year, that is "bumpy, better and less risky." He sees Asia leading the economic rebound, as China demand accelerates with the change in leadership and improved access to credit. University of Texas Austin Churchill scholar, Matthew Gertken, however, discussed the simmering "Asian cold war" developing as territorial disputes with China generate an emerging "containment policy" by many of China’s neighbors.

How these macroeconomic dynamics are impacting the semiconductor industry was discussed by speakers who saw both perils and opportunities. Andy Oberst, senior VP, strategy and corporate development at Qualcomm, looked at what mobile phones would likely look like in 2020, but also pointed out how disruptive changes — not incremental changes — have always driven the mobile phone market.

Satya Kumar, vice president at Credit Suisse, discussed how original equipment makers like phone and computer manufacturers have always benefitted from the declining cost of transistors and pondered, "Could stopping Moore’s Law be a good thing?"

As the world’s largest semiconductor company, Intel’s view is different. Michael Bell, vice president and general manager, mobile and communications group at Intel, brought the audience up to date on the company’s mobile strategy, offering confidence that Intel’s portfolio of RF baseband technologies, leading-edge scaling performance, and supply chain excellence will ultimately deliver significant success.

Conference speakers on Day 2 and Day 3 of ISS will discuss how these and other mega-trends are specifically impact the R&D, product development, manufacturing, investment, and supply-chain challenges impacting various sectors of IC and microelectronics industry.

The SEMI Industry Strategy Symposium (ISS) examines global economic, technology, market, business and geo-political developments influencing the semiconductor processing industry along with their implications for your strategic business decisions. For more than 35 years, ISS has been the bellwether semiconductor conference for senior executives to acquire the latest trend data, technology highlights and industry perspective to support business decisions, customer strategies and the pursuit of greater profitability.

By Rebecca Howland, Ph.D., and Tom Pierson, KLA-Tencor.

Is it time for high-brightness LED manufacturing to get serious about process control?  If so, what lessons can be learned from traditional, silicon-based integrated circuit manufacturing?

The answer to the first question can be approached in a straight-forward manner: by weighing the benefits of process control against the costs of the necessary equipment and labor.  Contributing to the benefits of process control would be better yield and reliability, shorter manufacturing cycle time, and faster time to market for new products. If together these translate into better profitability once the costs of process control are taken into account, then increased focus on process control makes sense.

Let’s consider defectivity in the LED substrate and epi layer as a starting point for discussion. Most advanced LED devices are built on sapphire (Al2O3) substrates. Onto the polished upper surface of the sapphire substrate an epitaxial (“epi”) layer of gallium nitride (GaN) is grown using metal-organic chemical vapor deposition (MOCVD).

Epitaxy is a technique that involves growing a thin crystalline film of one material on top of another crystalline material, such that the crystal lattices match—at least approximately. If the epitaxial film has a different lattice constant from that of the underlying material, the mismatch will result in stress in the thin film. GaN and sapphire have a huge lattice mismatch (13.8%), and as a result, the GaN “epi layer” is a highly stressed film. Epitaxial film stress can increase electron/hole mobility, which can lead to higher performance in the device. On the other hand, a film under stress tends to have a large number of defects.

Common defects found after deposition of the epi layer include micro-pits, micro-cracks, hexagonal bumps, crescents, circles, showerhead droplets and localized surface roughness. Pits often appear during the MOCVD process, correlated with the temperature gradients that result as the wafer bows from center to edge. Large pits can short the p-n junction, causing device failure. Submicron pits are even more insidious, allowing the device to pass electrical test initially but resulting in a reliability issue after device burn-in. Reliability issues, which tend to show up in the field, are more costly than yield issues, which are typically captured during in-house testing. Micro-cracks from film stress represent another type of defect that can lead to a costly field failure.

Typically, high-end LED manufacturers inspect the substrates post-epi, taking note of any defects greater than about 0.5mm in size. A virtual die grid is superimposed onto the wafer, and any virtual die containing significant defects will be blocked out. These die are not expected to yield if they contain pits, and are at high risk for reliability issues if they contain cracks. In many cases nearly all edge die are scrapped. Especially with high-end LEDs intended for automotive or solid-state lighting applications, defects cannot be tolerated: reliability for these devices must be very high.

Not all defects found at the post-epi inspection originate in the MOCVD process, however. Sometimes the fault lies with the sapphire substrate. If an LED manufacturer wants to improve yield or reliability, it’s important to know the source of the problem.

The sapphire substrate itself may contain a host of defect types, including crystalline pits that originate in the sapphire boule and are exposed during slicing and polishing; scratches created during the surface polish; residues from polishing slurries or cleaning processes; and particles, which may or may not be removable by cleaning. When these defects are present on the substrate, they may be decorated or augmented during GaN epitaxy, resulting in defects in the epi layer that ultimately affect device yield or reliability (see figure).

Patterned Sapphire Substrates (PSS), specialized substrates designed to increase light extraction and efficiency in high-brightness LED devices, feature a periodic array of bumps, patterned before epi using standard lithography and etch processes. While the PSS approach may reduce dislocation defects, missing bumps or bridges between bumps can translate into hexes and crescent defects after the GaN layer is deposited. These defects generally are yield-killers.

In order to increase yield and reliability, LED manufacturers need to carefully specify the maximum defectivity of the substrate by type and size—assuming the substrates can be manufactured to those specifications without making their selling price so high that it negates the benefit of increased yield. LED manufacturers may also benefit from routine incoming quality control (IQC) defect measurements to ensure substrates meet the specifications—by defect type and size.

Substrate defectivity should be particularly thoroughly scrutinized during substrate size transitions, such as the current transition from four-inch to six-inch LED substrates. Historically, even in the silicon world, larger substrates are plagued initially by increased crystalline defects, as substrate manufacturers work out the mechanical, thermal and other process challenges associated with the larger, heavier boule.

A further consideration for effective defect control during LED substrate and epi-layer manufacturing is defect classification. Merely knowing the number of defects is not as helpful for fixing the issue as knowing whether the defect is a pit or particle. (Scratches, cracks and residues are more easily identified by their spatial signature on the substrate.) Leading-edge defect inspection systems such as KLA-Tencor’s Candela products are designed to include multiple angles of incidence (normal, oblique) and multiple detection channels (specular, “topography,” phase) to help automatically bin the defects into types. For further information on the inspection systems themselves, please consult the second author.

Rebecca Howland, Ph.D., is a senior director in the corporate group, and Tom Pierson is a senior product marketing manager in the Candela division at KLA-Tencor.

Check out other Process Watch articles: “The Dangerous Disappearing Defect,” “Skewing the Defect Pareto,” “Bigger and Better Wafers,” “Taming the Overlay Beast,” “A Clean, Well-Lighted Reticle,” “Breaking Parametric Correlation,” “Cycle Time’s Paradoxical Relationship to Yield,” and “The Gleam of Well-Polished Sapphire.”

By Adrienne Downey, Director of Technology Research, Semico Research

In February 2012, Semico forecast 2012 semiconductor capex to reach $59.8 billion.  In December 2012, that forecast was virtually unchanged at $59.9 billion, down 5.6% from 2011.  After two years of double-digit growth (98% in 2010 and 26.2% in 2011), the semiconductor industry needed to back off and regroup.  Most concerning is that the gap between the big spenders and the small has expanded.  The top ten spenders for 2012 made up 81% of the total; this figure is up from the 76% of the total in 2011.  Overall, the top ten combined spent $48.2 billion, which is only 0.3% up from 2011.  Meanwhile, the rest of the companies went from spending $15.3 billion in 2011 to $11.7 billion in 2012, a decline of 24%.  Some of the decline can be attributed to companies like SanDisk, which, along with its partner Toshiba, delayed fab expansion projects until 2013.  Other companies like ST and TI made capacity improvements over the past few years, so spending in 2012 was mainly for maintenance.

In December 2012, most companies have still not announced capex plans for the following year.  This year is no different.  However, a handful of companies have given some indication of what they might spend next year.  For example, TSMC is forecasting 2013 capex to be slightly up compared to 2012.  Most of the other companies that have given a hint of 2013’s capex have indicated flat to down spending compared to 2012.  These companies include GLOBALFOUNDRIES, Avago, Fairchild, Micron, ON Semiconductor, SMIC, Spansion, and STMicroelectronics.  GLOBALFOUNDRIES announced its “Vision 2015” initiative to expand 300mm capacity in Singapore, but no budget was announced for the project. 

That being said, there are several construction projects that may give some indication of spending in 2013.  Samsung is retrofitting its Austin fab to switch from NAND to logic production, with mass production beginning in the second half of next year.  This is a $4 billion project spread out over 2012-2013.  Intel’s D1X and Fab 42 construction will wrap up in 2013; the company will also begin production at 14nm by the end of this year.  Samsung, TSMC, and GLOBALFOUNDRIES are also working on the 14nm and 20/22nm nodes.  UMC has Fab 12A Phases 5 and 6 under construction, with production schedule to begin in 2014.  SanDisk and Toshiba will probably increase their spending to complete the ramp of Fab 5, which they said would be complete by the end of 2013. 

Based on current indications, capital spending would seem to be flat in 2013.  However, Semico predicts healthy revenue growth this year, which may encourage more spending, particularly in the second half of the year.  This may bring total capex for 2013 into the positive range. 

By Mario M. Pelella, VP of Engineering, sp3 Diamond Technologies

Interest in diamond continues to grow within traditional thermal and wear applications (packaging, tool coating) and beyond into new applications (semiconductor, MEMS/NEMS, optical, interposers, electrodes, sensors, wastewater treatment, acoustic) that were previously difficult to exploit.

Diamond’s unique physical and electrical properties, which include the highest known thermal conductivity, highest Young’s modulus (diamond is the hardest substance man has ever discovered), a wide band gap, excellent electrical insulator properties, very low thermal expansion, very high breakdown voltage, very high carrier mobility, high radiation hardness, chemical and biochemical inertness and the broadest electromagnetic transmission spectrum, makes this remarkable technology a key enabler to break through current limitations and extend the performance and scalability of existing products well into the future.

For the currently available diamond-deposition systems, hot-filament chemical vapor deposition (HFCVD) growth technology provides the most reliable, safest and most cost effective solution that enables high throughput and good uniformity, control, repeatability and ease of scaling over large areas. Although current deposition areas are in the 350 mm x 375 mm range, scaling the HFCVD technology deposition area to 1000mm x 1000mm is viable, unlike other diamond-growth technologies.

The next step in the evolution of the semiconductor industry is to establish an SOD (silicon-on-diamond) substrate platform that mitigates the thermal impact of ever increasing power densities and suppresses local hot spots that influence peak performance and reliability (FIT rates) specifications, especially for RF power circuits and 3D-ICs. Moreover, incorporating diamond solutions into the MtM (more-than-Moore) technology roadmap will help extend electronic device and sensor performance metrics for a broad array of applications. All the process integration pieces to fully embrace SOD technology have been demonstrated, although productizing a 200mm (or larger) SOD substrate platform for high volume is still an elusive goal for the industry. Government agencies and corporate research and development funding continue to champion the maturity and advancement of diamond technology, which will help shorten the commercialization cycle of this exceptional material.

Recent advances in diamond applications (diamond-on-silicon, MEMS, optical), including record folded-beam RF resonator performance with a Q value of 146,580 at 232.4 kHz, IR transmission values nearing the theoretical limit of 71 percent, brighter, more energy-efficient LED lamps, exceptional figure-of-merit for RF power devices that are 40-50 times better than Si substrates, and demonstrated diamond-based diodes, BJTs, FETs, SAW filters, and field-emission devices, suggest that its utilization into a broader scope of commercial products is not far away.

By Christian Gregor Dieseldorff, director, SEMI Industry Research & Statistics, San Jose, CA USA  

Despite difficult times, growing demand for mobile devices (such as tablets and phones) inspires an improved outlook for chip sales in 2013.  Various forecasts range from 4% to 16% revenue growth for 2013 (average of forecasts 7%). As observed in the past, chip sales and capex typically ride the same roller coaster; however, 2013 appears to be another year of uncertainty. While chip sales may rise in 2013, expectations for equipment range from timid 5% growth down to double-digit decreases — definitely not the same roller coaster.

The largest spenders on fab equipment are Samsung, TSMC and Intel.  As of mid-December 2012, some of these companies still have not made any official announcement about 2013 capex plans.

The SEMI Consensus Forecast and the SEMI World Fab Forecast, with data collected from two different methodologies, point to the same conclusion.  The year-end Consensus Forecast for wafer processing predicts 0% growth (flat) for 2013.  Meanwhile, the World Fab Forecast report for Front End Fabs (published November 2012) also shows 0% growth (flat) for 2013 and total fab equipment spending hovering at US$ 32.4 billion (including Discretes and LEDs, used equipment and in-house equipment).  The projected number of facilities equipping will drop, from 212 in 2012 to 182 in 2013. Fab equipment spending saw a drastic dip in 2H12 and, accounting for seasonal weakness and near-term uncertainty, will be even lower in 1Q13.  Examining equipment spending by product type, System LSI is expected to lag in 2013. Spending for Flash declined rapidly in 2H12 (by over 40%) but is expected to pick up by 2H13. The foundry sector is also expected to increase in 2013, led by major player TSMC, as well as Samsung, Globalfoundries and UMC.

While fab construction spending slowed in 2012, at -15%, SEMI data projects an increase of 3.7% in 2013 (from $5.6 billion in 2012 to $5.8 billion in 2013).  The World Fab Forecast tracks 34 fab construction projects for 2013 (down from 51 in 2012).  An additional 10 new construction projects (with various probabilities) may start in 2013. The largest increase for construction spending in 2013 is expected to be for dedicated foundries and Flash-related facilities.

In 2012, many device manufacturers stopped adding new capacity due to declining average selling prices and high inventories. This is most pronounced in the Flash sector, as seen with Sandisk since the beginning of 2012, and both Samsung and Toshiba starting 3Q12.

Breaking down the industry by product type, capacity growth for System LSI is expected to decrease in 2013. Flash capacity additions dragged in 2H12. But more activity is expected for Flash by mid-2013, with nearly 6% growth. The data also point to a rapid increase of installed capacity for new technology nodes, not only for 28nm but also from 24nm to 18nm and first ramps for 17nm to 13nm in 2013.

If the global economy and GDP begin to improve, and chip sales actually do increase in the higher single-digit range, equipment spending is expected to ride the same roller coaster, going even higher for 2013.