Category Archives: LEDs

(September 27, 2010)Thermoelectric devices convert heat to electricity and vice versa, harnessing otherwise wasted energy. Researchers at the California Institute of Technology (Caltech) have developed a new type of material made out of silicon, that could lead to more efficient thermoelectric devices. The material — a type of nanomesh — is composed of a thin film with a grid-like arrangement of tiny holes.

Thermoelectric devices are touted for use in new and efficient refrigerators, and other cooling or heating machines. But present-day designs are not efficient enough for widespread commercial use or are made from rare materials that are expensive and harmful to the environment.

James Heath, the Elizabeth W. Gilloon Professor and professor of chemistry at Caltech, led the work. A paper about the research will be published in the October issue of the journal Nature Nanotechnology.

A major strategy for making thermoelectric materials energy efficient is to lower the thermal conductivity without affecting the electrical conductivity, which is how well electricity can travel through the substance. Heath and his colleagues had previously accomplished this using silicon nanowires, which work by impeding heat while allowing electrons to flow freely. This nanomesh design makes it difficult for heat to travel through the material, lowering its thermal conductivity to near silicon’s theoretical limit. At the same time, the design allows electricity to flow as well as it does in unmodified silicon.

In any material, heat travels via phonons, which deliver heat from one point to another. Nanowires, because of their tiny sizes, have a lot of surface area relative to their volume. And since phonons scatter off surfaces and interfaces, it is harder for them to make it through a nanowire without bouncing astray. As a result, a nanowire resists heat flow but remains electrically conductive.

Creating narrower and narrower nanowires is effective only up to a point. If the nanowire is too small, it will have so much relative surface area that even electrons will scatter, causing the electrical conductivity to plummet and negating the thermoelectric benefits of phonon scattering.

To get around this problem, the Caltech team built a nanomesh material from a 22nm-thick sheet of silicon. The silicon sheet is converted into a mesh with a highly regular array of 11- or 16nm-wide holes that are spaced just 34 nanometers apart. Instead of scattering the phonons traveling through it, the nanomesh changes the way those phonons behave, essentially slowing them down.

The properties of a particular material determine how fast phonons can go. In silicon, the mesh structure lowers this speed limit. As far as the phonons are concerned, the nanomesh is no longer silicon at all. "The nanomesh no longer behaves in ways typical of silicon," says Slobodan Mitrovic, a postdoctoral scholar in chemistry at Caltech. Mitrovic and Caltech graduate student Jen-Kan Yu are the first authors on the Nature Nanotechnology paper.

When the researchers compared the nanomesh to the nanowires, they found that — despite having a much higher surface-area-to-volume ratio — the nanowires were still twice as thermally conductive as the nanomesh. The researchers suggest that the decrease in thermal conductivity seen in the nanomesh is indeed caused by the slowing down of phonons, and not by phonons scattering off the mesh’s surface. The team also compared the nanomesh to a thin film and to a grid-like sheet of silicon with features roughly 100 times larger than the nanomesh; both the film and the grid had thermal conductivities about 10 times higher than that of the nanomesh.

Although the electrical conductivity of the nanomesh remained comparable to regular, bulk silicon, its thermal conductivity was reduced to near the theoretical lower limit for silicon. And the researchers say they can lower it even further. The researchers are now experimenting with different materials and arrangements of holes in order to optimize their design. "One day, we might be able to engineer a material where you not only can slow the phonons down, but you can exclude the phonons that carry heat altogether," Mitrovic says.

The other authors on the paper, "Reduction of thermal conductivity in phononic nanomesh structures," are Caltech graduate students Douglas Tham and Joseph Varghese. The research was funded by the Department of Energy, the Intel Foundation, a Scholar Award from the King Abdullah University of Science and Technology, and the National Science Foundation.

Follow Small Times on Twitter.com by clicking www.twitter.com/smalltimes. Or join our Facebook group

(September 24, 2010) — SEMICON Europa will take place October 19-21 in Dresden, Germany. The SEMI Europe team is closely working with their supporting committees and the manufacturing and R&D organizations to tailor the SEMICON Europa programs. Program development is matched to the specific needs of the European semiconductor industry in the current environment.

  • 12 Technology conferences
  • 13 Free technology and standardization session
  • 4 Executive and networking events
  • 12 Courses

The Advanced packaging and test track of SEMICON Europa will deal with the industry shift away from high-lead solders, digital test and testing integrated analog/mixed-signal packages, package design in the electronics design workflow, and LEDs, among other topics.

The theme of the Advanced Packaging Conference in 2010 will be "Enabling Packaging Technologies for System Integration."

The 12th European Manufacturing Test Conference (EMTC) is set to cover "Mapping Digital Test and Diagnosis Approaches on the Emerging Integrated Analog Mixed Signal Arena." Test will also be the focus of the 2nd CAST Workshop – Collaborative Alliance for Semiconductor Test, which will target docking and mounting.

Keynote speakers include Peter Robinson, Package Design and Development Director, CSR, presenting "System Design, Drives Package Design, Drives Silicon Design;" Raimund Schwarz, Senior Director, Osram Opto Semiconductors, who will deliver "High Brightness Phosphor Converted White LEDs — Challenges and Solutions;" and Andreas Fischer, Automotive Electronics, Development ASIC & Power Packages, Robert Bosch GmbH, giving the talk "Substitute material(s) for High-Lead Solders," about different ways to bond high-power packages in the increasingly lead-free electronics arena.

For the semiconductor packaging and test track agendas, including speakers and times, visit http://www.semiconeuropa.org/ProgramsandEvents/TestPackaging/index.htm

Program tracks (Click on the links to view a track overview):

Subscribe to Solid State Technology/Advanced Packaging.

Follow Advanced Packaging on Twitter.com by clicking www.twitter.com/advpackaging. Or join our Facebook group

(September 23, 2010) — RJR Polymers, developer of high-performance semiconductor packaging, debuted a new generation of Liquid Crystal Polymer (LCP) quad flat-pack no-lead (QFN), air-cavity packages that will support finer lead pitches, thinner leadframes and shorter wire bond lengths in a near hermetic, ROHS-compliant solution.

Able to withstand three non-lead reflows while remaining leak tight, these new MSL III packages will support leadframes as thin as 0.008in (0.20mm) and greater.

In early testing the new QFN packages have repeatedly passed over 500 thermal cycles from -65° to +150°C with no gross leak failures. The packages have also been successfully tested with a variety of plating types including NiAu and NiPdAu finishes. The packages can be tailored to address specific conditions and requirements of any assembly process.

RJR Polymer’s line of LCP QFN solutions offers a number of advantages over traditional ceramic QFN packaging options. These air cavity packages support high frequency performance up to 38 GHz, and demonstrate a return loss (S11) of more than -15 dB and insertion loss (S21) of less than -0.5 dB in the Ku-band. At the same time the technology’s use of a solid metal die pad delivers significantly better thermal management capabilities than traditional ceramic solutions. The technology’s 0.02% moisture absorption rate enables the development of near-hermetic packages. The LCP process is said to have a relatively low cost of entry for a proven platform.

“Over the last few years or so our LCP QFN packages have offered a highly attractive solution for commercial microwave and millimeter wave applications, but have been limited by lead pitch and package frame dimensions,” noted Dave DeWire, director of sales and marketing. “With finer lead pitches and thinner lead frames, LCP-based QFN solutions can reach a wider array of applications.”

RJR Polymers, Inc. is a developer of LCP semiconductor packaging, epoxies, epoxy-coated lids and sealing equipment for a wide variety of applications in the RF, cellular, automotive, optical, imaging, avionics and sensor markets as well as emerging applications in solar power, high-power LEDs and system-level solutions that require extremely high levels of integration. For more information, visit the company’s website at www.rjrpolymers.com.

Subscribe to Solid State Technology/Advanced Packaging.

Follow Advanced Packaging on Twitter.com by clicking www.twitter.com/advpackaging. Or join our Facebook group

Also read: Wafer-level Microbumping for Flip Chips, by JEAN-CHARLES SOURIAU, JEAN BRUN, RÉMI FRANIATTE, LYDIE MATHIEU, GÉRARD PONTHENIER, AND NICOLAS SILLON
and Wafer-level Hermetic Cavity Packaging by George A. Riley

(September 21, 2010) — Laird Technologies Inc. released its new Tflex XS400 Series thermal gap filler. The product is a compliant elastomer gap filler for moderate thermal performance with a thermal conductivity of 2.0W/mK. This soft interface pad conforms with minimal pressure, resulting in minimal thermal resistance even at low pressure with little or no stress on mating parts.

Available in thicknesses from 0.020 through 0.200 inch in 0.010 inch increments, the Tflex XS400 thermal material is naturally tacky for easy assembly and no adhesive coating is required. Due to its TG (Tgard) liner on the other side, it is electrically insulating, stable from -40 to +160°C, and is certified to UL 94V0 flammability rating; complying with the limits of RoHS Directive 2002/95/EC and its subsequent amendments.

The Tflex XS400 gap filler is an easy-to-handle thermal pad that possesses low outgassing properties, suiting telecom, IT, consumer, automotive, LED, and power supply applications that require a gap pad between heat-generating components and heatsinks.

Laird Technologies provides high-performance and cost-effective thermal management solutions for applications in the medical, analytical, telecom, industrial, and consumer markets. For more information, visit www.lairdtech.com.

Subscribe to Solid State Technology/Advanced Packaging.

Follow Advanced Packaging on Twitter.com by clicking www.twitter.com/advpackaging. Or join our Facebook group

(September 17, 2010) — The Asian growth story is not new. Already commanding almost 30% of the world’s GDP in 2009, Asian growth momentum remains strong at about 4% per annum [1]. Asia has achieved this on the back of becoming the manufacturing base of the world — from textiles to electronics to automotives.

As of 2009, global R&D spending is split almost evenly between Americas, Asia (excluding Japan) and the rest of the world (including EU and Japan). However, with a 7.5% growth rate in R&D spending, [2] coupled with the influx of engineering talent from all over the globe, Asia today is well positioned to be the at the forefront of the next technology revolution.

For technology businesses, an Asian strategy is imperative.

Singapore: Gateway to Asia

While Asia presents opportunities, it also presents challenges for businesses needing to navigate through its diverse and complex cultural, social and political environments. Asian customers will also require customized solutions developed with an in-depth understanding of their specific needs.

Many companies that want to succeed in this varied environment have come to realize that, to balance between increasing their topline growth and protecting their financial and intellectual investments, they need a strategic base in Asia with a stable business environment to locate their key activities and key decision makers who can oversee and grow their business network.

This realization has led a large number of multinational companies (MNCs) to set up a base in Singapore, out of which a majority conduct regional operations. As a global city in the heart of Asia, Singapore offers a stable pro-business environment for financial and legal protection, highly skilled work-force for corporate R&D activities, world class infrastructure for supply chain management and a strong manufacturing base (about 20% of GDP in 2009) for fabrication of key products.

Shaping the R&D landscape for nanotechnology

Recognizing R&D as a driver for growth, Singapore has developed an extensive R&D infrastructure and talent pool, which was further augmented by attracting and retaining a world-class talent pool of scientists and engineers, who bring a wealth of skills and experience from around the globe.

The focus on R&D was given a boost in 2005 with the debut of the Research, Innovation and Enterprise Council (RIEC) headed by the Prime Minister. By 2008, the total number of research scientists and engineers in Singapore per 10,000 workforce was 104, among the highest in the world. Going forward, the government has announced its aspiration to increase Singapore R&D spending to 3.5% of the national GDP by 2015, up from the current level of about 3%.

One of the major initiatives championed by RIEC is the Campus for Research Excellence And Technological Enterprise (CREATE), which will house research collaborations between elite universities like MIT, ETH, and Technion labs, and their Singapore counterparts.

This joins an existing base of 14 public research institutes (RI) under the Agency of Science, Technology, and Research (A*STAR), of which 7 are dedicated to research in the physical sciences and engineering. A Nanofabrication and Characterization facility, which includes a clean room with the full range of state-of-the-art nanofabrication equipments, was also set up to support researchers of all backgrounds, fostering a culture of interaction and innovation.

Nanotech industry development

Having drawn a strong pool of foreign talent and businesses to conduct research, extend important business units, and grow new businesses, Singapore aims to build nanotechnology as the horizontal technology foundation upon which many of the industry verticals in Singapore can leverage. Singapore also recognize that, to achieve nanotechnology’s full potential, close partnerships between R&D, industry, and consumers are not just desirable but crucial.

RELATED LINKS:

Economic Development Board of Singapore: http://www.edb.gov.sg/edb/sg/en_uk/index.html

Research, Innovation and Enterprise Council (RIEC) of Singapore: http://www.nrf.gov.sg/nrf/default.aspx

Campus for Research Excellence And Technological Enterprise (CREATE): http://www.nrf.gov.sg/nrf/otherProgrammes.aspx?id=188

Agency of Science, Technology, and Research (A*STAR): http://www.a-star.edu.sg/

BASF Global Research Centre in Singapore: http://www.basf.com/group/pressrelease/P-10-350 

Bilcare Technologies: http://www.bilcaretech.com/ 

Industrial Consortium on Nanoimprint (ICON): http://www.imre.a-star.edu.sg/nil/flyer.pdf 

NanoStart Asia Pte Ltd: http://www.nanostart.de/index.php/en/company/nanostart-asia-pte-ltd 

NanoFrontier Pte Ltd: http://www.nanofrontier.com.sg/

German chemical and plastics manufacturing company, BASF AG, operates a Global Research Centre in Singapore. The center’s 40 employees investigate nanostructured surfaces for anti-microbial applications such as in coatings, preventing the build up of organism deposits. BASF’s research leverages partnerships with NTU, A*STAR’s Institute of Materials Research and Engineering (IMRE), and local companies such as Nanomaterials Technology Pte Ltd.

The Bilcare group, global provider of clinical trial materials, recently acquired Singular ID (a spin off from A*STAR) to form Bilcare Technologies. Using a blend of micro and nanotechnology, Bilcare Technologies developed a range of products for brand protection and security applications, and high output equipment for producing large quantities of anti-counterfeiting tags. These and specialized readers, as well as sophisticated data management software form Bilcare’s “nonClonable” system, allows brand owners to track, trace and authenticate their products in real time.

To further collaborations between industry and public research institutes, Singapore launched the Industrial Consortium on Nanoimprint (ICON) in August 2010. ICON’s focus is to enhance the commercial readiness and adoption of nanoimprint technologies through collaboration between RIs and industry at the pre-competitive stage. This initiative was well received with six companies participating in the first project in anti-reflection surfaces. Other project being planned includes engineered anti-bacterial surfaces.

Collaborations allow firms to tap capabilities from outside their organization and to stretch their finite R&D funds to achieve greater outcome in less time. ICON highlights Singaporean support for such partnerships. By working closely on such public/private collaborations, we hope to reduce the time to market for new technologies.

Building an infrastructure for nanotech commercialization

As with most industries, R&D requires financial and business support to sustain its growth. Singapore has also grown a pool of supporting companies and private funding sources such as venture capitalists (VCs) and incubators, to bridge the gap between technology and market.

In 2008, Nanostart AG, a Germany-based nanotechnology investment company, incorporated its Asian subsidiary, NanoStart Asia Pte Ltd in Singapore. Shortly after, NanoStart Asia made its first investment deal with a Singapore company, Curiox Biosystems Pte Ltd, a locally grown bioinstrumentation company that enabled the miniaturization and automation of bioassays for research in life sciences, drug discovery, and diagnostics.

An incubator dedicated to nanotech start-ups, NanoFrontier Pte Ltd, was established in 2004 to engage innovative companies around the world in the development of nanotechnology-enabled products and services, provide intellectual property (IP) resources, nanotechnology R&D infrastructure, and technical expertise. A first in the region, NanoFrontier houses over 25 research scientists and engineers, and has access to over US$150 million premium R&D facilities and equipment at the Nanyang Technological University. It also works closely with industry through contract R&D work, joint development projects, and industrial consortiums.

To encourage test-bedding and commercialization, Singapore has also opened up large-scale integrated public infrastructure as ‘living labs’ for companies to test and demonstrate innovative nano-materials and applications such as nano-enhanced cement or coatings on self-cleaning windows. This created a path for companies to use Singapore as a reference site to launch into global markets.

Conclusion

Going forward, an integration model of continual partnership among private sector companies, consumers, research institutions, and the government will be the key in shortening the R&D cycle and bringing products to markets more efficiently while reducing risk for stakeholders. This also makes sense given the high capital expenditure for R&D at the nano scale.

With projected worldwide CAGR of 20% until 2013, and Asia-Pacific region experiencing a 52% growth in the nanotechnology-enabled goods market [3], the future of Nanotechnology is certainly bright. The question just remains, How do you want to position yourself for this technology revolution?

References:
1. World economic outlook database, April 2010. International Monetary Fund.
2. 2010 Global R&D Funding Forecast; R&D Magazine; Dec 2009, pp.3-24; available at http://www.rdmag.com
3. Market intelligence report by RNCOS, published in March 2010

All information in this article is understood as accurate by author at time of writing (August 2010)

Bernard Nee received his MSc in Management from MIT and an MSc in Electrical Engineering from the University of Illinois at Urbana-Champaign. He is the Executive Director for New Technologies at the Singapore Economic Development Board; http://www.sedb.com; [email protected].

Follow Small Times on Twitter.com by clicking www.twitter.com/smalltimes. Or join our Facebook group

by Michael A. Fury, Techcet Group

September 17, 2010 – About 40 fellow techno-geeks attended the Sept.15 meeting of the NCCAVS CMP Users Group at SEMI headquarters in San Jose. The agenda comprised seven topics for a combination of technical, technical marketing, and marketing presentations, with the overall theme of chemical mechanical planarization (CMP) for the hard-disk drive (HDD) industry. The group will post proceedings and presentations in the coming weeks.

Opening the meeting with a HDD market overview was John Kim of Trend Focus. Growth in the HDD sector has dropped from 15% CAGR in 1998-2007 to 10% for 2008-2014, with seasonal stability provided by strong markets in the BRIC region (Brazil, Russia, India, China). By 2014, the majority of drives will be in the 1Tb-2Tb range. At the same time, solid-state drives (SSD) will comprise 5%-6% of the market, even though the upper size will still be in the range of 128Gb. The consumer appetite for larger and larger drives has shown no evidence yet of an upper limit.

Sungpyo Jung of Western Digital talked about "consumables challenges in magnetic head CMP." Production uses 150mm AlTiC substrates, a wafer size not actively supported by all equipment manufacturers. Slurries use alumina abrasive with different chemistries to planarize features of Al2O3, magnetics (NiFe, CoNoFe, CoFe), metals (Au, Cu, CoPt, Ta, Ti, Cr, Ru, and others), and photoresist. Performance metrics are familiar to semiconductor CMP engineers, but their rank importance is different for HDD. Within-wafer uniformity improvement is an unmet need that ranks high on his list.

Kristan Bhatten of Dionex introduced a new-generation ion chromatography tool with a 0.4mm capillary and 0.4μL sample injection volume. The tool is expected to be useful for characterizing substrate surface contamination down to ppt levels, but specific data sets to showcase the tool for HDD and semiconductor CMP are still being developed.

Haijing Peng of KLA-Tencor showed a non-contact eddy current alternative to a four-point probe for measuring sheet resistance and polishing rates. The non-contact characteristic makes it possible to monitor processes on product wafer, eliminating the expense and throughput overhead of monitor wafers.

Sarah Okada of Strasbaugh gave an overview of the company’s STB P300 polisher, touted as a customized solution for GMR polishing needs. The platform supports all substrate sizes from 125mm to 300mm. One GMR-unique feature is an option for rapid grinding of thick Al2O3 with 800 or 1200 grit abrasive as a rapid removal step before polishing the final 1-2μm.

Vamsi Velidandla of Zeta Instruments described a new 3D imaging and metrology microscope that builds up topographical images with 70nm vertical resolution using a broadband white-light LED source. Sample scans of polishing pads and pad conditioners showed a level of detail superior to other methods I’ve seen. The data sets included a black felt carrier pad, which is often impossible to measure by other optical methods because the reflection intensity is so low.

Denise Hunter of Cabot Microelectronics wrapped up the meeting with a description of their mixed abrasive slurry for HDD substrates. The NiP plated platters are typically smoothed in a two-step process, alumina abrasive coarse polishing followed by silica abrasive final polish. The irregularly shaped alumina particles can leave embedded fragments in the NiP grain boundaries, resulting in defects on the platter. The HDD mixed abrasive slurry combines alumina with much smaller colloidal silica abrasive. The silica is thought to envelop the alumina particles and decrease the incidence of fragmentation. Removal rate of the mixed abrasive slurry is ~10% lower than alumina slurry, but defect levels are significantly improved, to the extent that several HDD fabs are qualifying the new material for volume production.


Michael A. Fury, Ph.D, is senior technology analyst at Techcet Group, LLC, P.O. Box 29, Del Mar, CA 92014; e-mail [email protected].

(September 14, 2010) — Professor Mark Lundstrom of Purdue University is the 2010 recipient of the Aristotle Award given by SRC and presented at its TECHCON technology conference. Professor Li-C Wang, University of CA at Santa Barbara, received the Technical Excellence Award.

The Aristotle Award recognizes the recipient’s accomplishments in preparing hundreds of students for research leadership in nanotechnology.

 

 

In a podcast interview with Debra Vogler, senior technical editor, Lundstrom discusses some of the research projects in which his students have participated over the years that have had an impact on furthering nanotechnology. Looking ahead, researchers are being asked to find out how small a MOSFET can be made — with channel lengths below 8nm. Alternative devices are sought by researchers to complement a CMOS platform. Podcast: Download or Play Now

The Technical Excellence Award was given to Professor Li-C Wang of the University of California at Santa Barbara, along with his former research assistants, Pouri Bastani and Benjamin Lee. This award recognizes key contributions to technologies that significantly enhance the productivity of the semiconductor industry.

 

Wang and his group conducted research in data mining and learning for test and validation, which led to the development of practical tools and methodologies used to solve several current problems faced by a number of SRC members. In a podcast interview, Dr. Wang describes a number of applications of the group’s findings, which represents a new data mining paradigm. Podcast: Download or Play Now

Read more about the TECHCON research and presenters.

Follow Small Times on Twitter.com by clicking www.twitter.com/smalltimes. Or join our Facebook group

Sunnyvale, CA–After heading the optoelectronic semiconductor business for 22 years at OSRAM Opto Semiconductors, Rüdiger Müller is bidding farewell upon reaching retirement age. As of October 1, 2010, Aldo Kamper, a proven LED expert and time-tested executive, is succeeding Müller. Martin Goetzeler, CEO of the parent company OSRAM said, "Down to this very day, Dr. Rüdiger Müller has been one of the driving forces worldwide in the development of LED technology, which now reaches far into our everyday lives. With Aldo Kamper, we have been able to win a successor from our own ranks–someone who will advance OSRAM Opto Semiconductors and make his own mark."

Kamper started his professional career at OSRAM in 1994 after completing his business administration studies. Between 1999 and 2006, he held executive positions at OSRAM Opto Semiconductors in the fields of automotive and visible LEDs. Since 2006, he has held the post of executive VP & GM, Specialty Lighting at OSRAM Sylvania in the U.S.

Müller headed the optoelectronic semiconductor business at Siemens from 1988 and, in 1999, was also founding CEO of OSRAM Opto Semiconductors, in which Siemens’ LED and infrared business was pooled with OSRAM’s lighting competence. Besides strong growth and the continuous expansion of production capacities in Regensburg and in Penang, Malaysia, OSRAM says his name is most closely linked with technological advances in optoelectronic semiconductor technology. Crucial innovations, such as thin-film technology, direct blue or green semiconductor laser diodes, the first OLED product, and the first surface-mountable LED (SMT-LED)–innovations that set standards to this very day–emerged under his leadership.

SOURCE: Macrovision; www.macrovis.com/nr/oos-190.html

Posted by: Gail Overton

Follow us on Twitter

Subscribe now to Laser Focus World magazine; It’s free!

(September 10, 2010) — CEA-Leti designed and developed a prototype of the new-generation scalar magnetometer in partnership with CNES. The ASM passed the qualification step en route to being deployed in the SWARM space mission.

SWARM, a project of the European Space Agency, is scheduled for launch in 2011 or 2012. The mission’s objective is to provide the best survey of the Earth’s magnetic field and its temporal evolution, and gain new insights that will improve scientists’ understanding of the Earth’s interior and climate.

The new absolute scalar magnetometers (ASM) are designed to overcome the limits of the nuclear magnetic resonance (NMR) magnetometers, the first magnetometers designed to be placed in orbit. Those instruments, which were used in the Oersted mission launched in 1999 and the CHAMP mission launched in 2000, also were developed by Leti in partnership with CNES.

Onboard the three-satellite Swarm mission, the new magnetometers will provide measurements over different regions of the Earth simultaneously.

The SWARM mission will produce a precise cartography of the magnetic field and measure its evolution. From three different polar orbits, the satellites must be operated simultaneously to distinguish the temporal variations — interactions between magnetosphere and the solar wind — from the local ones. To guarantee the required availability during the mission, two backup ASMs operating in cold redundancy will be onboard each satellite.

The absolute scalar magnetometer is based on laser-pumped helium to amplify the signal-to-noise ratio, which gives it exceptional sensitivity and performance. A condensed technology, the main difficulty is the qualification of its components for the space environment, in particular a fiber-laser source, one of the components of the magnetometer.

The tested prototype matches the orbiting magnetometers that will be delivered to ESA by the end of 2010. It underwent complete tests designed to guarantee functioning in an orbiting environment.

The magnetic field models resulting from the SWARM mission also will further scientists’ understanding of atmospheric processes related to climate and weather and will have practical applications in many different areas, such as space weather and radiation hazards.

Earlier this year, CEA-Leti’s ASM magnetometer was onboard Jean-Louis Etienne’s balloon for the Generali Arctic Observer mission. Although a strong magnetic storm reduced the value of the collected data, the magnetometer successfully accomplished its mission. This performance underscores the close collaboration between the teams of CEA-Leti and CNES, which work together to meet the demands of challenging projects on Earth and in space.

CEA is a French research and technology public organisation, with activities in four main areas: energy, information technologies, healthcare technologies and defence and security. CEA-Leti is focused on micro and nanotechnologies and their applications, from wireless devices and systems, to biology and healthcare or photonics. Nanoelectronics and microsystems (MEMS) are at the core of its activities. For more information, visit www.leti.fr.

The SMARM mission has been approved as an Earth Observation Mission and led by the ESA. It’s constituted by a constellation of three similar satellites designed to study the magnetic field.

A public center with industrial and commercial purpose (Etablissement Public à Caractère Industriel et Commercial – EPIC), the National Center for Spatial Mission (CNES – Centre National d’Etudes Spatiales) is in charge of proposing the French spatial policy to the government in Europe and to put it in place. For more information, visit www.cnes.fr 

Follow Small Times on Twitter.com by clicking www.twitter.com/smalltimes. Or join our Facebook group

(September 10, 2010) — Speaking at the MEPTEC Forecast Luncheon (Santa Clara, CA 9/8/10), Gartner VP of semiconductor manufacturing research, Jim Walker, noted that equipment spending is mostly on technology, foundry and memory. And for the first time, 2 SATS companies (ASE and SPIL) joined the top 20 capital spenders in 2010. He also predicts solid growth for advanced packaging tooling with memory ATE and copper wire bonders being the top performers. Walker told attendees that the conversion to copper wire from gold is a wise move for the industry — with even some high-end packaging joining the conversion.

Podcast: Download or Play Now

Overall, Gartner sees a 31.5% semiconductor growth in 2010, with PCs, cell phones, and LEDs being the key drivers. (Also listen to an interview with Bob Johnson, Gartner, here)

Hear additional comments on the forecast and the overall economic outlook in the podcast interview with Walker, including his thoughts on how the memory cycle will impact capex.