The study, led by Federico Capasso, Robert L. Wallace Professor of Applied Physics at Harvard’s School of Engineering and Applied Science (SEAS), is the cover story of the January 8 issue of the journal Nature.
January 8, 2009: Lu Papi & Associates was honored for its nanotech-enabled “Freedom Wheelchair” at the Australian Engineering Excellence Awards in late 2008.
Arthur W. Zafiropoulo, Chairman & CEO, Ultratech, Inc., San Jose, CA USA
To successfully maneuver in today’s restless economic waters, companies must possess a stellar balance sheet with a strong cash position, and provide leading-edge technology.
While corporate and existing markets drove the recovery from the last several downturns, today, consumers are the driving force behind the entire economic cycle and responsible for both the ups and the downs. Already, we are beginning to see increased inventories on store shelves. As a result, chip companies will not buy tools to increase capacity. Instead, increased implementation of next-generation technologies will take a greater percentage of their budgets, and chip makers will purchase equipment with leading-edge technology. This is confirmed by the escalating interest from advanced logic manufacturers for laser spike anneal (LSA) systems and packaging lithography tools driven by 45nm and below manufacturing. Companies will spend money on breakthrough technology that enables them to manufacture devices at advanced nodes when the recovery arrives.
As companies continue to look for ways to reduce costs, conserving energy will become a more prominent focus. A truly bright spot in energy conservation is advanced LED devices. Today, lighting utilizes ~20% of global energy. As a result, the industry is transitioning to white light and high-brightness LEDs (HBLEDs), which have a long life and use only a fraction of energy compared to incandescent and fluorescent lighting. As conservation efforts intensify, I believe this market has the potential for significant growth. LED lighting technology dramatically enables energy conservation and Ultratech has an active part in this effective solution by providing leading technology in our lithography steppers for advanced LED device manufacturing.
I believe the first half of 2009 will be difficult. However, companies that have a strong cash balance are ideally positioned for potential growth and possible strategic and accretive acquisitions. As the industry undergoes further consolidation, I feel there will be a small recovery in the second half of the year.
Erik Smith, President, Qcept Technologies, Atlanta, GA USA
The semiconductor industry will be challenged in 2009. The economic crisis in the U.S. and around the globe has led to weakened demand for PCs and consumer electronic products, as well as corporate IT investments, all of which fuel IC consumption. Amid the gloomy outlook on IC demand in the coming quarters, many chip manufacturers are cutting back on their investments to build capacity. However, it is at this time — when demand is at its softest — that the wisest of chip manufacturers are continuing to make strategic investments in new manufacturing technologies and methodologies in order to position themselves to quickly ramp up on new chip designs when semiconductor demand inevitably swings upward once again.
In past downturns, the nature of these technology investments skewed heavily toward design shrinks as the primary driver for device performance improvements. Now however, we are seeing the escalating cost of lithography pushing the leading chip manufacturers toward the integration of new materials into their manufacturing processes as an important lever. These new materials, such as high-k and low-k dielectrics, metal gates and advanced photoresists, improve the performance of their devices and increase average selling prices (ASPs) on their shipped products. As always, each new material and the added process steps associated with its introduction requires yield learning in order to bring the new process into maturity. Thus, yield management remains an investment priority for the top semiconductor manufacturers regardless of the stage of the cycle in which the industry finds itself.
However, in the same way that there is a rethinking of how to drive performance improvements, a rethinking of traditional yield management strategies is also underway. These new materials and processes rely on very tight tolerances on surface condition in order to reap their performance benefits. This increases the importance of controlling non visual defects, such as submonolayer organics and metallics, and process-induced charge, which arise from repeated surface prep and cleaning process steps, and which cannot be detected through traditional inspection methods.
Just as we are seeing “out of the box” thinking in terms of how to drive device performance, we are seeing the same in terms of yield management. By making technology investments now, the industry will have the infrastructure required to raise volume yields in this new era of materials and process innovation that will fuel performance growth in 2009 and beyond.
Franklin Kalk, CTO, Toppan Photomasks Inc., Round Rock, TX USA
Every semiconductor downturn raises two key questions: How long will it last, and who will survive? For answers, we must look at the causes of these cyclical events, and hazard some crystal-ball gazing into the current crisis.
These downturns are always characterized by oversupply stemming from overbuilding, reduced demand, or both. In 2001, the last serious downturn, irrational expectations fostered by the dot.com boom and “the Internet as killer app” led companies to install excess manufacturing capacity. But the dot.com bust and 9/11 precipitated dramatic reduction in demand. As a result, global semiconductor sales plunged from a record $204 billion in 2000 to $139 billion in 2001 — a 32% drop.
This time, a volatile mix of extreme leverage and the collapse of credit markets are pulling the global economy into a downturn that will reverberate globally in 2009, and perhaps beyond. Meanwhile, consumers account for about two-thirds of the U.S. Gross Domestic Product, and they cut back when they are worried about the economy. Because semiconductor sales now are so dependent on consumer electronics (versus the past’s PC focus), the industry is more vulnerable to consumer emotion than it was in 2001.
On the positive side, this landscape differs from 2001 because, with the exception of NAND flash, overbuilding is not a significant factor. So, we are primarily in a demand-driven downturn, and consumer spending might begin to pick up when lenders get back into business — this will affect how long this crisis lasts.
As for the second question, there will be consolidation: size will matter. Availability and efficient use of capital will be paramount. The survivors will have the cash to ride out the downturn, gain market share, and make strategic acquisitions. They’ll drive efficiencies as customers and suppliers align business models and develop strategies and products to support existing and new markets. This inevitable evolution will be painful for some, but it will position the industry better for the continually changing global economy.
The MLSC awarded a grant of $250,000 per year for three years to David Weitz, Mallinckrodt professor of physics and applied physics at Harvard’s School of Engineering and Applied Sciences and Physics Department, and RainDance Technologies of Lexington, Mass., to develop and demonstrate the use of a new form of fluorescence activated cell sorter (FACS) used to collect biochemical information about individual cells. The researchers hope to explore new applications of FACS that have not yet been feasible, from basic biology and medical studies to drug development.
January 7, 2009: Energetiq Technology, Inc., a developer and manufacturer of specialized short-wavelength light products that enable nano-scale structures, has raised additional capital in its Series C round of financing. The financing was led by a new investor, Ushio Inc. , and supported by existing investors including Intel Capital and Shea Ventures.
It is a place where efforts are under way to invest millions in resources to capture a portion of the projected $1 trillion U.S. nanoelectronics industry, especially research emerging from the Midwest Institute for Nanoelectronics Discovery (MIND) at Notre Dame, the newest of four national research centers funded by the nation’s leading computer chip makers.
January 6, 2009: Strasbaugh, a manufacturer of surfacing technology for the semiconductor, silicon, data storage, MEMS, LED, telecommunications and optics industries, has begun trading common stock on the OTC Bulletin Board under the symbol “STRB.”
The team, led by David Cumming and Tim Drysdale, from the university’s department of electronics and electrical engineering, will take advantage of a phenomenon called plasmon resonance in their efforts to create a microchip for cameras and other imaging equipment that will produce sharper, more colorful images.
January 6, 2009: FEI Co., which provides high-resolution imaging and analysis systems, has acquired substantially all of the assets of Intellection Holdings Pty. Ltd. of Brisbane, Australia, FEI announced in a news release.
December 22, 2008: Research done by scientists in Italy and Switzerland has shown that carbon nanotubes may be the ideal “smart” brain material. Their results, published December 21 in the advance online edition of the journal Nature Nanotechnology, are a promising step forward in the search to find ways to “bypass” faulty brain wiring.
The research shows that carbon nanotubes, which like neurons are highly electrically conductive, form extremely tight contacts with neuronal cell membranes. Unlike the metal electrodes that are currently used in research and clinical applications, the nanotubes can create shortcuts between the distal and proximal compartments of the neuron, resulting in enhanced neuronal excitability.
The study was conducted in the Laboratory of Neural Microcircuitry at EPFL in Switzerland and led by Michel Giugliano (now an assistant professor at the University of Antwerp) and University of Trieste professor Laura Ballerini.
“This result is extremely relevant for the emerging field of neuro-engineering and neuroprosthetics,” explains Giugliano in a statement, hypothesizing that the nanotubes could be used as a new building block of novel “electrical bypass” systems for treating traumatic injury of the central nervous system. Carbon nano-electrodes could also be used to replace metal parts in clinical applications such as deep brain stimulation for the treatment of Parkinson’s disease or severe depression. Furthermore, they show promise as a whole new class of “smart” materials for use in a wide range of potential neuroprosthetic applications.
“There are three fundamental obstacles to developing reliable neuroprosthetics: stable interfacing of electromechanical devices with neural tissue; understanding how to stimulate the neural tissue; and understanding what signals to record from the neurons in order for the device to make an automatic and appropriate decision to stimulate,” according to Henry Markram, head of the Laboratory of Neural Microcircuitry and an author on the paper. “The new carbon nanotube-based interface technology discovered together with state of the art simulations of brain-machine interfaces is the key to developing all types of neuroprosthetics — sight, sound, smell, motion, vetoing epileptic attacks, spinal bypasses, as well as repairing and even enhancing cognitive functions.”
December 22, 2008: Formalizing progress in nanoscience and nanotechnology, engineering researchers at the University of Arkansas have published a textbook on the emerging field of nanomedicine.
Nanomedicine: Design and Application of Magnetic Nanomaterials, Nanosensors and Nanosystems presents a comprehensive treatment of a rapidly developing field that is changing the way biologists, physicists, chemists and medical researchers address a variety of health conditions, including cancer and neurological disorders such as Parkinson’s disease and Alzheimer’s disease.
“Nanomedicine, which is generally defined as the biomedical applications of nanoscience and nanotechnology, stands at the boundaries of physical, chemical, biological and medical sciences,” said Vijay Varadan, distinguished professor of electrical engineering and primary author. “Advances in nanomedicine have made it possible to analyze and treat biological systems at the cell and sub-cell levels, providing revolutionary approaches for the diagnosis, prevention and treatment of some fatal diseases.”
The book provides an introduction to nanomedicine and explains the technological and scientific forces that led to the development of the field. It focuses on the physical and chemical properties of the materials and particles used in nanomedicine and discusses the working principles for biomedical applications for various types of magnetic nanomaterials, some of which have already improved human health and quality of life. The book pays specific attention to magnetic nanomaterials, magnetic nanoparticles and the development of biosensors, biochips and magnetic thin films.
Varadan said the volume may be used as a textbook for beginners and research students, as well as a reference book by working professionals. He hopes the book will facilitate more systematic training in the field.
by Dick James, senior technology adviser, Chipworks
Editor’s Note: Each day during IEDM, Chipworks’ Dick James will share his thoughts on what he saw as the best presentations.
Dec. 18. 2008 – The morning was an endurance test, with nine consecutive papers on 22, 32, and 45nm devices. A lot of strained silicon, and not a few strained attendees! So it’s a bit tedious, but rather than cherry-pick, let’s run through the list from Session 27:
27.1
The IBM Alliance kicked off the day again with the 0.1 μm2 SRAM cell that was announced back in the fall, fabbed at the Albany Nanofab. With a 90nm contacted gate pitch and gate length of 25nm, a suite of different techniques were used to create the test chips.
Not least the wet lithography; the active SOI areas were patterned using crossed quadrupole illumination; the gates used double exposure, double etch (DEDE, or DE2, or LELE — acronyms are taking over again) with dipole illumination; the contacts used DE2 with a tri-layer resist; and M1 was patterned with double masking using dipole illumination and a single etch.
Other process elements are 45nm thin SOI, dual high-k metal gates (HK+MG), co-implants at the SDE/halo, and copper contacts with Ru liners. As this was a proof-of-concept exercise, stress techniques were not used, although in answer to a question the presenter implied that they were being introduced.
27.2
Next up was TSMC with a 32nm gate-first HK+MG process, with a 9Å EOT, 30nm Lg and 130nm contacted gate pitch, with an SRAM cell size of 0.15 μm2. The usual suite of stress tools was used, SMT, e-SiGe, and dual stress liners (DSL), and junction profiles were optimized with co-implants. The BEOL has ten layers of copper, and 2nd generation low-k dielectric (k~2.55) at the lower levels (Black Diamond 2?).
27.3
IBM were back up again, this time the Common Platform et al, with a 32nm, single gate-first HK+MG bulk technology with 126nm contacted gate pitch and 0.157 μm2 SRAM cell. The usual stress trio of SMT+DSL+e-SiGe is present, and thin-barrier copper with ELK (extreme low-k, k~2.4) in the BEOL.
27.4
Intel’s turn this time, with tweaks to their 45nm process to add low-power and RF/mixed signal elements to the designer toolbox. After running through the base process, we had a shopping list of new features. Some were obvious — the super-thick 8μm redistribution layer is ideal for inductors, for example — but others need new process modules.
High voltage I/O transistors with a thicker SiO2 layer have been added, as have low-power transistors with slightly longer gate lengths and tuned S/Ds to reduce junction leakage (co-implants?). Add in capacitors, varactors, one-time programmable fuses, and RF transistors and you have quite a shopping bag. At the end of the paper someone asked if there were poly devices (the replacement gate has not been replaced), which was met by the usual stony “I can’t answer that” response — which makes us all think that it’s at least being looked. I must admit that at Chipworks we have thought about that possibility, at least for fuses.
Figure 1: TEMs of nMOS and pMOS logic (left top/bottom) and I/O transistors (right top/bottom). Note the thicker oxide layer in I/O devices. (Source: Intel)
27.5
Now the NEC/Toshiba consortium; a 40nm high-k dielectric (but not metal gate) technology, with 40nm gate length, 168nm contacted gate pitch, 0.195μm2 SRAM cell, and a thicker EOT of 1.75nm. A couple of years ago NEC announced a 55nm process with a hafnium-based gate dielectric, and it looks like this is a shrink.
They went into quite a lot of detail about the source/drain engineering, reducing junction leakage by using a Ge + N pre-amorphization implant before the SDE and halo implants, and putting a lot of work into the activation anneal sequence to co-optimize it with the SMT stress application (nitride stress is also used, no mention of DSL).
The gate litho is single exposure to keep costs down, and the BEOL has the choice of low-k dielectric, k~2.75 or 2.55, depending on cost requirement (Black Diamond 1 or 2?). This paper is worth going through in detail, as it discusses stuff usually described with a phrase or two.
Figure 2: 40nm transistors with HfO dielectric. Note the lack of thick dark metal layer. (Source: NEC/Toshiba)
27.6, 27.7
I took a pass on these — I needed a break!
27.8
Now we’re into the late news papers — NEC/Toshiba again, but 32nm this time, again with a cost conscious emphasis — the target was to reduce per-function cost by 50% from the 45nm node. They claimed that this was achieved with a standard cell gate density of 3650K gates/mm2; it sounds impressive!
They achieve this by using single-pass lithography and gate-first HK+MG transistors. Contacted gate pitch is 120nm, and SRAM cell size is 0.124μm2, but no other details were available. By the litho images below, it looks like the full suite of OPC and dipole/quadrupole illumination tricks is being used.
Figure 3: [Top] 0.124 μm2 SRAM cell, (A) gates, (B) contacts, (C) Metal 1. [Bottom] D-type flip-flop, (left) active area, gates, and contacts, (right) Metal 1. (Source: NEC/Toshiba)
27.9
This was the Intel 32nm paper that got the pre-publicity back in the fall. EOT is down a smidge to 9Å, gate length is 30nm, SRAM cell 0.171μm2, we have 4th-generation strain, and the BEOL is 9 metal levels with slight tweaks to the low-k package, but still low-k/SiCN.
It struck me when we took apart the 45nm part that the technology had legs, and was scalable to 32nm; I think what we’re seeing here is essentially a shrink (except, of course, with wet litho); we’ll find out at the backend of next year when the chips appear on the market.
So as you can see the morning session was very intense, and there were other papers in other sessions that I wanted to get to. In the afternoon session 37 was more focused on source/drain engineering, so I wound down by sitting on a couple of those.
37.2
Samsung has been trying out different co-implants and anneal cycles on their 45nm base process. Ge is used as a pre-amorphization implant before both n- and pMOS SDE and halo implants, and this was modified to Ge + C or F, and cluster carbon (C16H10) was tried to replace both.
In nMOS the cluster-C seems to give the best results, sharpening up the halo profile, and reducing junction leakage. PMOS it was not quite so positive, since the halo profile was sharpest with the Ge + F combination; but overall the clusters seemed to do best. Boron clusters were also tried in pMOS, but that led to an increase in Vt variation.
37.4Toshiba did an interesting analysis by atom probe of platinum doping in nickel silicide. This is an ongoing trend that we have seen in our analyses, almost the majority of 65nm parts have Pt-doped silicides (Intel is an exception); it is claimed to reduce contact resistance. Atom probe is a relatively new technique, but it has much better resolution than SIMS, since it counts individual atoms (check www.Imago.com).
The analyses showed that the platinum segregated both at the surface and the silicide interface in the source/drains, which actually jives with an atom probe analysis we did of a UMC-fabbed Xilinx part; we saw the same feature in the gate polysilicon. And it did help contact resistance.
Phew! That’s it for IEDM ’08. Maybe I’ll see you next year… If the industry’s still around. — D.J.
DICK JAMES is a 30-year veteran of the semiconductor industry and the senior technology analyst for Chipworks, an Ottawa, Canada-based specialty reverse engineering company that gets inside technology and takes apart ICs and electronics systems in order to provide engineering information for its customers. Contact him at 3685 Richmond Road, Suite 500, Ottawa, ON, K2H 5B7, Canada; ph 613/829-0414, fax 613/829-0515, [email protected], www.chipworks.com.