Category Archives: Packaging

Dr. Deepak Sekar is a senior principal engineer at Rambus Labs. He is the author or co-author of a book, two invited book chapters, 30 publications and 100 issued or pending patents (50 issued). He is a program committee chair at the International Interconnect Technology Conference, has received two best paper awards and serves on the committee of the International Technology Roadmap for Semiconductors. 

 In a keynote at the IEEE International Interconnect Technology Conference (IITC), Douglas Yu from TSMC talked about Moore’s Law scaling becoming increasingly difficult. The solution, he said, is to supplement VLSI with what he called a Wafer Level System Integration (WLSI) paradigm. Advances in wafer level packaging and through-silicon via technology could allow systems to scale and reduce the dependence on transistor/chip scaling, according to Yu.

Figure 1: Douglas Yu of TSMC talked about WLSI

Techniques for WLSI

Yu then described TSMC’s efforts towards WLSI.

Fan-in wafer level packages, where the package is the same size as the chip, were shown with sizes as high as 52 sq. mm (see Figure 2(a)). These could be used for low pin count applications such as WiFi.

Fan-out wafer level packages, where individual die are embedded in a molding compound, could be used for higher pin count applications, said Yu. These allow placing one or more die within the same package. TSMC has qualified large 225 sq. mm fan-out wafer level packages with tight 20um pitch redistribution layer wiring (see Figure 2(b)). These fan-out wafer level packages could be used for medium to high pin count applications and also for multi-chip packages.

Figure 2: (a) A 52 sq. mm fan-in wafer level package (b) A 225 sq. mm fan-out wafer level package where the die is surrounded by a molding compound

Yu then showed TSMC’s silicon interposer and 3D-TSV technology, called CoWoS (chip-on-wafer-on-substrate). Figure 3 depicts the process flow for CoWoS and finished systems built with the technology. It is just a matter of time before TSV technologies are prevalent, he said.

Figure 3: Chip-on-Wafer-on-Substrate technology used for interposer and 3D systems

How WLSI could allow system scaling despite the increasing challenges with Moore’s Law

Significant reductions in system size are possible with wafer level packaging, interposer and 3D stacking technologies, said Yu. This is particularly beneficial to mobile applications, which show the fastest growth in the industry today. This would allow packing more and more functionality within the same form factor, something Moore’s Law is finding increasingly difficult to do.

Smart system partitioning with WLSI can benefit electronic products quite a bit, said Yu. He gave an example of partitioning digital and analog components. With finFETs moving to production, designing analog components on the same chip as logic becomes difficult due to high parasitic capacitance. Analog blocks take up more and more percentage of the chip area since they don’t scale well. In this scenario, placing analog components on a separate chip and using fan-out wafer level packaging or TSV technology to build competitive systems is beneficial, he said. This allows systems to combine analog at a trailing edge node (eg. 65nm) and logic at a leading edge node (eg. 14nm). IP blocks can be reused, time-to-market can be accelerated with smart system partitioning and yields can be improved due to the lower die size, said Yu.

System performance per watt improvement, one of the benefits of Moore’s Law scaling, can also be obtained with WLSI, according to Yu. Memory (access) power is now a key component of total system power and this is increasing with every generation. By using fan-out wafer level packaging or TSV technology, memory power can be significantly reduced due to the shorter wire lengths (Figure 4).

Figure 4: WLSI could reduce logic to DRAM wire lengths from 20mm to 0.03mm.

During the question and answer session, Yu mentioned that all of the technologies he described used pure wafer-based processes, which allowed larger packages and lower cost. Audience members, when asked about the keynote, mentioned that cost will determine how prevalent the technologies presented in Yu’s talk will become. 3D chip technologies are still considered a few years away from mass adoption.

The International Interconnect Technology Conference, held in Kyoto this year, is IEEE’s flagship conference in the interconnect field.

At this week’s VLSI 2013 Symposium in Kyoto, Japan, imec highlighted new insights into 3D fin shaped field effect transistors (finFETs) and high mobility channels scaling for the 7nm and 5nm technology node.         

At the VLSI 2013 symposium, imec presented the first strained Germanium devices based on a Si-replacement process, where a Ge/SiGe quantum-well heterostructure is grown by epitaxially replacing a conventional Si-based shallow trench isolation (STI). The technique allows for highly-versatile means of heterogeneous material integration with Si, ultimately leading the way to future heterogeneous finFET/nanowire devices.  The device shows dramatically superior gate reliability (NBTI) over Si channel devices due to a unique energy band structure of the compressively-strained Ge channel.

 “We are facing significant challenges  to scale the MOSFET architecture towards 7nm and 5nm. Besides dimension scaling, enhancing the device performance, in the face of rising parasitics and power, is a major focus of the logic device research at imec,” said Aaron Thean, logic devices program director at imec. “Among the key activities are R&D efforts investigating both high-mobility channel material and new methods of enhancing Si-based finFET.” 

With options to introduce heterostructure into next-generation finFET, quantum-well channels based on a combination of materials that enhance both mobility and electrostatics, can be engineered. At VLSI 2013, imec also presented comprehensive simulation work that investigated material combinations of Si, SiGe, Ge and III-V channels to enhance device electrostatics, providing important process guidance to extend finFET scalability.

Moreover, imec presented novel highly scalable engineering approaches to tune gate workfunction and improve mobility, noise and reliability in Si nMOS finFETs. The impact on the performance of layout-induced stress effects in scaled finFETs and the impact of random telegraph noise (RTN) fluctuation in lowly doped devices was shown.

Imec’s research into next-generation finFETs is performed in cooperation with imec’s key partners in its core CMOS programs including GLOBALFOUNDRIES, INTEL, Micron, Panasonic, Samsung, TSMC, Elpida, SK hynix, Fujitsu and Sony.

Multitest, a designer and manufacturer of final test handlers, contactors and load boards used by integrated device manufacturers (IDMs) and final test subcontractors worldwide, today announced that it will hold its annual Open House Week July 9-11, 2013. Daily tours of the Multitest Santa Clara, CA facility, located at 3021 Kenneth Street, will be held at 10 a.m. and 2 p.m.

The tours will include live demos of fully installed handling equipment, a factory tour of Multitest’s board fabrication, as well as expert discussions about the company’s innovative test solutions to fully support the opportunities of mobility. Mobile devices such as smartphones, tablets and notebooks allow connecting anywhere at any time. Semiconductors for mobile applications need to meet dedicated requirements. Semiconductor design and production implement new approaches. Advanced packaging technologies need to be supported by cost-efficient test solutions.

Multitest’s handling equipment, contactors and load boards fully support the special electrical and mechanical requirements of mobility. Mobility drives new package types, advanced IC functionalities and integration. Multitest offers the ideal test setup to leverage the optimum features from each test cell element, harmonize the elements, and offer a cost-efficient, high-performance solution. For more information or to register for the event, visit http://multitest.com/openhouse

senior vp and general manager of spansionSpansion Inc., a provider of flash memory solutions for embedded markets, today announced the appointment of Robin J. Jigour as senior vice president and general manager of the company’s Flash Memory Business Group.

"Robin brings deep memory product expertise to Spansion and will play an instrumental role in continuing to drive new product innovation with our NOR and NAND Flash memory solutions," said John Kispert, president and CEO of Spansion. "He has a track record of new product development that translates into new market opportunities and revenue growth."

Jigour has over 35 years of experience in the semiconductor industry with companies such as Intel, ICT, Nexcom, ISSI and NexFlash. In the mid-1990s, Jigour pioneered the industry’s first Serial Flash memories, a market segment with annual sales of over $1.3 billion and growing. In the mid-2000s, he defined and introduced the market’s first Multi-I/O (Dual and Quad) Serial Flash memories, setting the standard that is widely used in the industry today. Most recently, Jigour was vice president of Flash Memory marketing at Winbond, where he played a key role in starting the company’s Serial Flash memory business in 2005 and growing it to approximately $370 million in 2012.

"Building upon Spansion’s industry-leading technology brings forth an exciting opportunity to accelerate the use of Flash memory and continue to deliver the solutions our customers need for next-generation, high-performance memory intensive systems," said Robin Jigour. "I am thrilled to join an organization such as Spansion with unparalleled focus and execution in the embedded market."

SEMI, the global industry association for companies that supply manufacturing technology and materials to the world’s chip makers, today reported that worldwide semiconductor manufacturing equipment billings reached US$ 7.31 billion in the first quarter of 2013. The billings figure is 8 percent higher than the fourth quarter of 2012 and 32 percent lower than the same quarter a year ago. The data is gathered jointly with the Semiconductor Equipment Association of Japan (SEAJ) from over 100 global equipment companies that provide data on a monthly basis.

Worldwide semiconductor equipment bookings were $7.78 billion in the first quarter of 2013. The figure is 23 percent lower than the same quarter a year ago and 14 percent higher than the bookings figure for the fourth quarter of 2012.

The quarterly billings data by region in billions of U.S. dollars, quarter-over-quarter growth and year-over-year rates by region are as follows:

The Equipment Market Data Subscription (EMDS) from SEMI provides comprehensive market data for the global semiconductor equipment market. A subscription includes three reports: the monthly SEMI Book-to-Bill Report, which offers an early perspective of the trends in the equipment market; the monthly Worldwide Semiconductor Equipment Market Statistics (SEMS), a detailed report of semiconductor equipment bookings and billings for seven regions and over 22 market segments; and the SEMI Semiconductor Equipment Consensus Forecast, which provides an outlook for the semiconductor equipment market.

SEMATECH announced today that Applied Seals North America (ASNA) has joined SEMATECH’s Manufacturing Technology Center, which is designed to improve semiconductor equipment manufacturing productivity, yield and cost. 

The Manufacturing Technology Center is working on particle management solutions to reduce the number of particle excursions that are found in vacuum process tools. As a part of this project, fab participants identified chemical vapor deposition (CVD) systems as the largest contributor to the failure rate and shallow trench isolation (STI) gap fill as the most problematic process application within the CVD tool group.

As a member of SEMATECH’s Manufacturing Technology Center, ASNA will collaborate with SEMATECH engineers to reduce the number of particle excursions by identifying seal designs and materials for STI gap fill process tools that are used in both 200 mm and 300 mm semiconductor manufacturing facilities. Additionally, ASNA and SEMATECH will work together to develop and introduce new material solutions that will help to significantly extend the life of the seals and reduce the number of particles that are shed from them.

“We are excited to collaborate with SEMATECH on innovative technology development to help address current and future technology challenges for sealing of vacuum systems,” said Dalia Vernikovsky, CEO of ASNA. “This project will help spearhead initiatives and collaborative efforts to drastically improve sealing performance while significantly decreasing defects that are attributed to seals. As the complexity of the technology increases, innovations in materials, seal design and particle control is essential for successful manufacturing.” 

“Particle excursions are a major cost-of-ownership issue for vacuum tools and there is a technology gap that ASNA can help address to enable fabs to squeeze additional productivity from their very expensive vacuum tools,” said Julian Richards, Manufacturing Technology project manager. “We look forward to working closely with ASNA in a collaborative effort to engineer sealing solutions that reduce the number of down events caused by particle excursions.”

ISORG and Plastic Logic have co-developed the first conformable organic image sensor on plastic, with the potential to revolutionize weight/power trade-offs and optical design parameters for any systems with a digital imaging element. First mechanical samples will be publicly unveiled at LOPE-C 2013 (ISORG / CEA booth B0-509) from June 12 to 13 in Munich, Germany.

The collaboration is based on the deposition of organic printed photodetectors (OPD), pioneered by ISORG, onto a plastic organic thin-film transistor (OTFT) backplane, developed by the technology leader, Plastic Logic, to create a flexible sensor with a 4×4 cm active area, 375um pitch (175um pixel size with 200um spacing) and 94 x 95 = 8 930 pixel resolution.

organic image sensor

The backplane design, production process and materials were optimized for the application by Plastic Logic to meet ISORG’s requirements. The result, a flexible, transmissive backplane, represents a significant breakthrough in the manufacture of new large area image sensors and demonstrates the potential use of Plastic Logic’s unique flexible transistor technology to also move beyond plastic displays. Combined with ISORG’s unique organic photodetector technology, it opens up the possibilities for a range of new applications, based around digital image sensing, including smart packaging and sensors for medical equipment and biomedical diagnostics, security and mobile commerce (user identification by fingerprint scanning), environmental, industrial, scanning surfaces and 3D interactive user interfaces for consumer electronics (printers, smartphones, tablets, etc.).

ISORG’s CEO, Jean-Yves Gomez stated: “We are extremely pleased to showcase our disruptive photodiode technology in a concrete application for imaging sensing. The ability to create conformal and large area image sensors, which are also thinner, lighter and more robust and portable than current equipment is of increasing importance, especially in the medical, industrial and security control sectors.”

Indro Mukerjee, CEO Plastic Logic said: “I am delighted that Plastic Logic can now demonstrate the far-reaching potential of the underlying technology. Our ability to create flexible, transmissive backplanes has led us not only to co-develop a flexible image sensor, but is also key to flexible OLED displays as well as unbreakable LCDs.”

Altera Corporation today introduced its Generation 10 FPGAs and SoCs, offering system developers breakthrough levels of performance and power efficiencies. Generation 10 devices are optimized based on process technology and architecture to deliver the industry’s highest performance and highest levels of system integration at the lowest power. Initial Generation 10 families include Arria 10 and Stratix 10 FPGAs and SoCs with embedded processors. Generation 10 devices leverage the most advanced process technologies in the industry, including Intel’s 14-nm Tri-Gate process and TSMC’s 20 nm process. Early access customers are currently using the Quartus II software for Generation 10 product development.

Altera said its Stratix 10 FPGAs and SoCs are designed to enable the most advanced, highest performance applications in the communications, military, broadcast and compute and storage markets, while slashing system power. Leveraging Intel’s 14nm Tri-Gate process and an enhanced high-performance architecture, Stratix 10 FPGAs and SoCs have an operating frequency over one gigahertz, 2X the core performance of current high-end 28nm FPGAs. For high-performance systems that have the most strict power budgets, Stratix 10 devices allow customers to achieve up to a 70 percent reduction in power consumption at performance levels equivalent to the previous generation.

Altera is announcing the technology details of Stratix 10 FPGAs and SoCs today as part of the Generation 10 portfolio introduction, and will disclose more details on the product at a later date. Stratix 10 FPGAs and SoCs provide the industry’s highest performance and highest levels of system integration, including:

  • More than four million logic elements (LEs) on a single die
  • 56-Gbps transceivers
  • More than 10-TeraFLOPs single-precision digital signal processing
  • A third-generation ultra-high-performance processor system
  • Multi-die 3D solutions capable of integrating SRAM, DRAM and ASICs

Arria 10 FPGAs and SoCs are the first device families to roll out as part of the Generation 10 portfolio. Leveraging an enhanced architecture that is optimized for TSMC’s 20nm process, Arria 10 FPGAs and SoCs deliver higher performance at up to 40 percent lower power compared to the previous device family.

Early access customers are currently using the Quartus II software for development of Arria 10 FPGA and SoCs. Initial samples of Arria 10 devices will be available in early 2014. Altera will have 14 nm Stratix 10 FPGA test chips in 2013 and Quartus II software support for Stratix 10 FPGAs and SoCs in 2014.

CEA-Leti announced today that researchers Dominique Vicard and Jean Brun received the Avantex Innovation Prize for the use of the E-Thread technology in textiles.

The award was presented June 10 during the award ceremony at the opening of the Techtextil and Avantex Symposia in Frankfurt, Germany.

According to Avantex, the “innovation awards go to outstanding achievements in research, new materials, products, technologies and applications.”

E-Thread is a microelectronic packaging technology developed by Leti that allows for a direct connection of a chip to a set of two conductors, which can provide the functions of antenna, power and/or data bus. This allows a 10x improvement in size, assembly time and reliability compared to classic microelectronic packaging. The E-Thread assembly can then be incorporated inside a yarn and used by the textile and plastic industries using standard production tools. Electronics such as LEDs, RFIDs or sensors can then be truly integrated in materials and objects.

In choosing this technology for the innovation award, the Avantex jury said “electronics integrated in textiles during the textile processing and not simply by adding the components in a last step will be a significant step forward.” The jury also said the prize was awarded to “this development, as it shows that research and development is also for the textile industry of vital importance and that it can lead to the creation of new companies.”

E-Thread is one of the technologies used within the European FP7 PASTA project (Platform for Advanced Smart Textile Application), and is the key technology asset of the Primo1D startup company, that will be created by Leti during the second half of 2013.

Vicard previously won a 40,000-euro startup award from OSEO, the French organization committed to supporting entrepreneurship, for proposing embedding electronic functions in textile yarns using the E-Thread technology.

Samples of E-Thread will be on display during the symposia, Hall 3.1, stand B11.

Silicon Labs, a provider of high-performance, analog-intensive, mixed-signal ICs, today announced that it has signed a definitive agreement to acquire Energy Micro AS. Based in Oslo, Norway, the late-stage privately held company offers the industry’s most power-efficient portfolio of 32-bit microcontrollers (MCUs) and is developing multi-protocol wireless RF solutions based on the industry-leading ARM Cortex-M architecture. Energy Micro’s energy-friendly MCU and radio solutions are designed to enable a broad range of power-sensitive applications for the Internet of Things (IoT), smart energy, home automation, security and portable electronics markets.

The growth of the IoT market, coupled with continued deployment of smart grid and smart energy infrastructure, is driving strong demand for energy-efficient processing and wireless connectivity technology to enable connected devices in which low-power capabilities are increasingly important. Industry experts predict that the number of connected devices for the IoT will top 15 billion nodes by 2015 and reach 50 billion nodes by 2020.

“Silicon Labs and Energy Micro share a complementary vision of a greener, smarter, wirelessly connected world, and the foundation for this combined vision is ultra-low-power technology enabled by each company’s innovative mixed-signal design,” said Tyson Tuttle, president and CEO of Silicon Labs. “This acquisition combines two proven leaders in nano-power MCU and wireless SoC design into a formidable force that will accelerate the deployment of energy-friendly solutions across the Internet of Things and smart energy industries.”

The company expects the addition of Energy Micro’s EFM32 Gecko MCUs and EFR Draco Radios, ultra-low-power technology expertise, energy-aware Simplicity development tools, and world-class design and applications teams will drive the rapid expansion of its Broad-based business. Silicon Labs intends to apply these complementary embedded technology platforms and expertise to enable the industry’s most energy-efficient solutions for the burgeoning IoT and smart energy markets, as well as the proliferation of battery-powered portable electronics devices. In addition, both companies’ 32-bit MCU and wireless products leverage the same ARM Cortex-M architecture, which is expected to accelerate the combined roadmap and support rapid adoption among the existing customer base.

“The Energy Micro team is excited to join Silicon Labs,” said Geir Førre, president and CEO of Energy Micro, who after the closing, is expected to become vice president and general manager of Silicon Lab’s Energy-Friendly Microcontroller and Radio business unit, based in Oslo. “Silicon Labs’ excellent resources and technology will help the combined company develop new products and gain market share more quickly.”