Category Archives: Packaging

Advanced packaging technology is undergoing dramatic changes as the smart phones and new sensor technologies demand continued improvements in form and function.  To address these massive changes, SEMICON West will feature a number of programs on new packaging technologies and processes with speakers from leading chip makers, equipment manufacturers, and material suppliers.

According to IDC, forecasts semiconductor revenues will log a compound annual growth rate (CAGR) of 4.1 percent from 2011-2016, but revenues for 4G phones will experience annual growth over 100 percent for the same period. NanoMarkets estimates that the global market for “Internet of Things” sensors will reach $1.6 billion this year and grow to a value of $17.6 billion by the end of the decade as sensors become increasingly connected to the Internet directly or through hubs.  Both trends will significantly impact semiconductor and microelectronics packaging.  Demand for equipment and related tools in the 3D-IC and wafer-level packaging area alone is forecasted to grow from approximately $370 million in 2010 to over $2.5 billion by 2016, according to Yole Developpment.

To address these changes, SEMICON West 2013 (register at www.semiconwest.org/registration), held on July 9-11 in San Francisco, will feature a number of programs on new packaging applications, requirements, technologies, and products, including:

  • Generation Mobile:  Enabled by IC Packaging Technologies — Speakers from ASE, UBM Tech Insights, Amkor Technology, SK Hynix, and Universal Scientific Industrial will present on the latest advances in wafer-level packaging, new materials, and multi-die integration, including new System-in-Package (SiP) and Package-on-Package (PoP) methods. Location: Moscone Center (North Hall), TechXPOT North, Tuesday, July 9, 10:30am-12:30pm.
  • “THIN IS IN": Thin Chip & Packaging Technologies as Enablers for Innovations in the Mobility Era — IEEE/CPMT will hold a technical workshop on the overall trend of maximum functional integration in the smallest and thinnest package with lowest packaging costs with speakers from Intel, Cisco, ASE, Micron, SK Hynix, Nanium, Kyocera and more. Location: San Francisco Marriott Marquis, Tuesday, July 9, 1:30-4:45pm.
  • Advancing 2.5D and 3D Packaging through Value Engineering — Speakers from Altera, Amkor, ASE, ASET, KPMG, UMC, STATS ChipPAC and more will take a critical look at 2.5D implementations and the current outlook for 3D packages, including tools and technologies for heterogeneous stacks. Location: Moscone Center (North Hall), TechXPOT North, Wednesday, July 10, 1:00-3:30pm.
  • MEMS & Sensor Packaging for the Internet of Things— This session will feature speakers from all parts of the ecosystem to address how future visions of a pervasive interconnected world will be realized through the heterogeneous integration of MEMS and ICs.  The program will feature keynote speaker Janusz Bryzek from Fairchild Semiconductor, and speakers from VTT Research, Fraunhofer IZM, Robert Bosche, EV Group, Dai Nippon Printing, and more. Location: Moscone Center (North Hall), TechXPOT North, Thursday, July 11, 10:30am-1:00pm.

In addition to the packaging programs, SEMICON West 2013 will also feature over 560 exhibitors with the latest innovation on microelectronics manufacturing, including over 150 exhibitors with equipment and technology solutions for advanced packaging.  Other programs and exhibitors at West will address lithography, advanced materials and processes, silicon photonics, test, LED and MEMS manufacturing, and other subjects.  For more information on SEMICON West and to register, visit www.semiconwest.org

CEA-Leti will present recent advances and a preview of future developments in micro- and nanotechnologies, followed by workshops on key technical fields, during Leti Innovation Days, June 25-28, on the MINATEC campus.

The gathering incorporates Leti’s two-day Annual Review, now in its 15th year. That event provides an update of developments from Leti’s labs and its success in transferring technology to industry.

The 15th Annual Review kicks off on June 25th with two plenary sessions:

  • Envisioning the Future, chaired by Leti CEO Laurent Malier, will include insights from industry leaders into the technological innovations that will shape the future.
  • Enabling the Future, chaired by Pierre-Damien Berger, Leti VP of business development and communication. Presentations will include Leti’s latest developments and the key enabling technologies that will drive advancements in a broad range of sectors.

June 26th presentations by Leti specialists and partners will cover security and safety, environment and health, green IT and nanoelectronics.

“This year’s review powerfully highlights the wide-ranging strengths of Leti’s offer, from continuous innovation to technology transfer and support for SMEs,” said Leti CEO Laurent Malier. “Leti last year demonstrated a new FD-SOI solution that offers a 40 percent improvement in power consumption and a 30 percent frequency improvement, at lower costs. Transferred to manufacturing, it delivered the first application processor product dedicated to smartphones exceeding 3 GHz. We also particularly expanded our actions for SMEs, with a specific initiative allowing them to benefit from the expertise of our researchers and engineers and to access our state-of-the-art equipment.”

The Annual Review will be followed on June 27-28 by five in-depth workshops on design for 3D, memory, photonics, imaging and nanopackaging.

Leti Innovation Days participants will include international and European decision-makers: CEOs, CTOs, marketing and strategy directors, R&D managers, IT and semiconductor companies, innovative SMEs, end-user companies, research institutes, startups and international press. Represented industries include advanced microelectronics, green IT, memory, imaging, LEDs and lighting, safety and security, and healthcare and the environment.

 

The smartphone is a subset of the total cellphone handset marketplace. One basic difference between an enhanced cellphone and a smartphone is the ability of the smartphone to incorporate third-party applications. Smartphones also typically connect to leading-edge cellular network services and are at the forefront of the convergence of data, telecom, and consumer-oriented functions (such as video games, camera, music player, mobile TV, etc.) in a single handheld device.  Most smartphones include touchscreens with built-in wireless modems and GPS/GNSS, and are capable of Web browsing, sending and receiving e-mail, voice recognition, video and audio streaming, running office applications, and over-the-air synching with a PC.

Many in the cellphone industry believe new smartphone designs are reaching the point where they have enough performance to become the primary computing device for many consumers.  If so, the market could be on the verge of entering into “the post-PC era,” as previously identified by the late Steve Jobs, who stirred up controversy with his provocative prediction in June 2010.

The new consumer/Web emphasis in the cellphone market has been a challenge for a number of top-ranked smartphone suppliers (e.g., RIM, Nokia, etc.), which have struggled to refocus their handset designs, software platforms, and business strategies to address the current phase of the fast-growing smartphone segment.

Figure 1 shows that total smartphone shipments grew 47% in 2012 to 712 million units, after surging by 67% to 485 million in 2011.  Moreover, smartphone shipments are forecast to grow by another 37% in 2013 and fall only 25 million units shy of 1.0 billion.  Smartphones are expected to account for over 50% of quarterly shipments for the first time ever in 2Q13.  In fact, smartphone shipments are forecast to reach 300 million units in 4Q13 and represent 60% of total cellphones shipped that quarter.  Smartphones are expected to surpass the 50% penetration level on an annual basis this year and hold 85% of total cellphone shipments in 2016.

In contrast to smartphones, total cellphone unit shipments grew only 1% in 2012 and are forecast to grow only 3% in 2013 (Figure 2).  As shown, non-smartphone cellphone sales were flat in 2011 but showed a 17% decline in 2012.  Moreover, IC Insights expects another 20% drop in non-smartphone handset sales in 2013.

 

Between 2011 and 2016, smartphone shipments are expected to rise at a very strong CAGR of 29% to 1,760 million units in the final year of the forecast period (the 2011-2016 CAGR for non-smartphone unit shipments is -24%).  Overall, the smartphone 2011-2016 unit shipment CAGR is greater than 7x the expected CAGR for total cellphone unit shipments in that same five-year timeframe (4%).

Competition in smartphones intensified in 2012 as suppliers rolled out new handset designs with larger touch-screen displays, more powerful processors, better operating systems, higher-resolution cameras, and new radio-modem connections to the faster “4G” cellular networks, which were quickly spreading in the U.S., South Korea, Europe, and Japan.  In the next few years, new high-speed “4G” networks are planned for China, India, Brazil, the Middle East, and other fast-growing developing markets.

Samsung and Apple dominated the smartphone market in 2012 and are expected to do so again in 2013.  In total, these two companies shipped 354 million smartphones (218 million for Samsung and 136 million for Apple) and held a combined 50% share of the total smartphone market last year.  For 2013, these two companies are forecast to ship 480 million smartphones (300 million for Samsung and 180 million for Apple) and see their combined smartphone unit marketshare slip only one percentage point to 49%.

In 2012, smartphone sales from China-based ZTE, Lenovo, and Huawei surged.  Combined, the three top-10 China-based smartphone suppliers shipped about 80 million smartphones in 2012, more than a 3x increase from the 24 million smartphones these three companies shipped in 2011.  Moreover, these three companies are forecast to ship 142 million smartphones in 2013 and together hold a 15% share of the worldwide smartphone market.  In contrast to the success of the large China-based smartphone suppliers, IC Insights expects RIM and HTC to continue to struggle in the smartphone marketplace in 2013 with both companies forecast to show a double-digit decline in smartphone unit shipments as compared to 2012.

Smartphone suppliers under pressure include Nokia, RIM, and HTC, each of which registered steep double-digit year-over-year declines in smartphone sales in 2012.  Until several years ago, Nokia held a 50% marketshare in smartphones, but in 2008 and 2009, the company saw its share fall below 40% due to increased competition from suppliers targeting consumers with interactive touch-screen handsets that are capable of running multimedia applications.  In 2012, Nokia’s smartphone shipments declined by 55% (to only 35 million units) and represented only a 5% share of the total smartphone market.  Other smartphone producers that have fallen on hard times recently include RIM and HTC.  While each of these companies had about a 10% share of the 2011 smartphone market, IC Insights forecasts that each of them will have only about a 3% share of the 2013 smartphone market.

 Report Details:  IC Market Drivers 2013

IC Market Drivers 2013—A Study of Emerging and Major End-Use Applications Fueling Demand for Integrated Circuits examines the largest, existing system opportunities for ICs and evaluates the potential for new applications that are expected to help fuel the market for ICs.

IC Market Drivers is divided into two parts.  Part 1 provides a detailed forecast of the IC industry by system type, by region, and by IC product type through 2016.  In Part 2, the IC Market Drivers report examines and evaluates key existing and emerging end-use applications that will support and propel the IC industry through 2016.  Some of these applications include the automotive market, cellular phones (including smartphones), personal/mobile computing (including tablets and Ultrabooks), wireless networks, digital imaging, and a review of many applications to watch—those that may potentially provide significant opportunity for IC suppliers later this decade.  The 2013 IC Market Drivers report is priced at $3,190 for an individual-user license and $6,290 for a multi-user corporate license.

GLOBALFOUNDRIES plans to unveil a comprehensive set of certified design flows to support 2.5D IC product development with its most advanced manufacturing processes at next week’s 50th Design Automation Conference (DAC) in Austin, Texas. The sign-off ready flows, jointly developed with the leading EDA providers, offer robust support for implementing designs using sophisticated multi-die packaging techniques, leveraging through-silicon vias (TSVs) in 2.5D silicon interposers and new bonding approaches.

Multi-vendor support is available, with full implementation flows from Synopsys and Cadence Design Systems. Physical verification with Mentor Graphics’ suite of tools is included in the flow.

The GLOBALFOUNDRIES 2.5D technology addresses the challenges of multi-die integration with solutions for front-end steps such as via-middle TSV creation, and flexibility for the backend steps, like bonding/debonding, grinding, assembly, and metrology.

“Our 2.5D technology provides designers with a path to enable heterogeneous logic and logic/memory integration, offering increased performance and reduced power consumption, without the need for additional packages,” said Andy Brotman, vice president of design infrastructure at GLOBALFOUNDRIES. “These benefits can now be realized very efficiently with certified design flows that provide support for the additional steps and design rules involved in the design process. By working closely with our EDA partners, we can greatly reduce the development time and time-to-production using the most advanced multi-die approaches.”

The flows allow designer to quickly and reliably address the additional requirements of 2.5D design, including top-level interposer design creation and floor planning, as well as the increased complexity of using TSVs, front-side and back-side bumps, and redistribution layer (RDL) routing. The flows support the need for additional verification steps brought on by 2.5D design rules.

The design flows work with GLOBALFOUNDRIES’ process design kits (PDKs) to provide real examples that demonstrate the entire flow. The user can download the design database, the PDK, detailed documentation and multi-vendor scripts to learn how to set up and use the GLOBALFOUNDRIES design flow. The flows use open source examples and provide the customer with working, executable and customizable flows.

The flows come with a CPU core and memory IP and all the scripts and settings to execute a Synopsys Galaxy Implementation Platform-based flow or Cadence Encounter-based implementation flows with the GLOBALFOUNDRIES PDK. Similarly, the Mentor Calibre 3DSTACK tool is exercised in the flow to verify DRC, LVS and extraction within and between the various die stacks leveraging the same golden design kits as used inside of GLOBALFOUNDRIES .

At next week’s 50th Design Automation Conference (DAC) in Austin, Texas, GLOBALFOUNDRIES will unveil a comprehensive set of certified design flows to support its most advanced manufacturing processes. The flows, jointly developed with the leading EDA providers, offer support for implementing designs in the company’s 20nm low power process and its 14nm-XM FinFET process. Working closely with Cadence Design Systems, Mentor Graphics and Synopsys, GLOBALFOUNDRIES has developed the flows to address the most pressing design challenges, including support for analog/mixed signal (AMS) design, and advanced digital designs, both with demonstration of the impact of double patterning on the flow.

The GLOBALFOUNDRIES design flows work with its process design kits (PDKs) to provide real examples that demonstrate the entire flow. The user can download the design database, the PDK, detailed documentation and multi-vendor scripts to learn how to set up and use the GLOBALFOUNDRIES design flow. The flows use open source examples and provide the customer with working, executable and customizable flows.

“As the developer of the industry’s first modular 14nm FinFET technology and one of the leaders at 20nm, we understand that enabling designs at these advanced process nodes requires innovative methodologies to address unprecedented challenges,” said Andy Brotman, vice president of design infrastructure at GLOBALFOUNDRIES. “By working with a new level of collaboration with EDA partners, we can provide enhanced insight into our manufacturing processes in order to fully leverage the capabilities of 20nm and 14nm manufacturing. This provides our mutual customers with the most efficient, productive and risk-reduced approach to achieving working silicon.”

Production ready AMS flow from specification to verification

To address the unique requirements of analog/mixed signal (AMS) design at advanced processes, GLOBALFOUNDRIES has enhanced its design flows to provide production quality scripts and packaged methodologies. The new reference flow establishes a working flow from specification to physical verification that has been taped out to be verified on working silicon.

The AMS reference flow provides comprehensive double pattern design guidelines. It gives overview of decomposition flow for both block level and chip level. The flow also addresses decomposition for different design styles. Recommendations for color balancing, hierarchical decomposition, ECO changes are discussed. The flows also present decomposition impact on DRC run time and resulted database size.

Notably, the reference flow includes support for efficiency and productivity improvements in the Cadence Virtuoso environment specifically for designing in a double patterned process. The flow includes support for Virtuoso Advanced Node 12.1 and provides efficient access to the tool’s productivity benefits for physical design with real-time, color-aware layout. Circuit designers can assign “same net” constraints in the schematic, and the layout designers can meet these requirements as they create the physical view. Additionally, layout designers can take advantage of Virtuoso tool support for local interconnect, and advanced layout dependent effect management.

The flow also features interoperability with Mentor’s Calibre nmDRC, nmLVS, and extraction products which address multipatterning requirements for both double and triple patterning. In addition special settings for analog design; auto-stitching and when to use it; and fill and color balancing are described in detail.

The AMS flow provides detailed information on parasitic extraction and layout dependent effects, both of which introduce new challenges at 20nm and 14nm. For parasitic extraction, the flows are described in detail and customizable scripts and examples demonstrate OA and DSPF back annotation. In addition the flows illustrate methodologies to predict layout-dependent effects during schematic design and methods to include full models in post layout extraction. PEX flows for Synopsys StarRC extraction, Cadence QRC and Mentor CalibrexRC are supported.

These flows serve as references to validate the correctness of the accompanying PDK as well as the vendor tools setup.

Sign-off ready RTL2GDSII flows that address double patterning

GLOBALFOUNDRIES is also making available new flows that support a complete RTL-to-GDSII design methodology for targeting its 20nm and 14nm manufacturing processes. The company worked with EDA vendors to certify the flows in their respective environments and provide a platform for optimized, technology-aware methodologies that take full advantage of the performance, power and area benefits of the processes.

The result is a set of fully executable flows containing all the scripts and template files required to develop an efficient methodology. The flows serve as a reference to validate the correctness of the accompanying PDK as well as the vendor tool setup. In addition the flows offer access to other critical and useful information, such as methodology tutorial papers; guidelines and methodologies for decomposition of double patterned layouts; PEX/STA methodology recommendations and scripts; and design guidelines and margin recommendations.

A critical aspect of manufacturing at this level is the use of double patterning, an increasingly necessary technique in the lithographic process at advanced nodes. Double patterning extends the ability to use current optical lithography systems and the GLOBALFOUNDRIES flows provide comprehensive double pattern design guidelines. They address design for double patterning and the added flow steps for different design styles and scenarios.

This includes support for odd cycle checking, a new type of DRC rule that must be met to allow for legal decomposition of the metals into two colors. This check is detailed in the flow and guidelines are provided to make sure it is met.

Synopsys and GLOBALFOUNDRIES worked together to minimize the impact of changes associated with the 3-D nature of FinFET devices as compared to planar transistors.  The two companies focused on making FinFET adoption transparent to the design team.  The collaboration on Synopsys’ RTL to GDSII flow includes 3-D parasitic extraction with the Synopsys StarRC tool, SPICE modeling with the Synopsys HSPICE product, routing rules development with the Synopsys IC Compiler tool and static timing analysis with the Synopsys PrimeTime tool.

Cadence contributed a complete RTL-GDSII flow, including physical synthesis, and planning and routing developed with the Encounter Digital Implementation (EDI) System foundation flow. The seamless implementation flow, using Cadence Encounter RTL Compiler and EDI System, supports double patterning and advanced 20- and 14-nm routing rules.

Mentor’s Olympus-SoC place and route system is supported in the flow, providing support for new DRC, double patterning, and DFM rules. The Olympus-SoC router has its own native coloring engine along with verification and conflict resolution engines that detect and automatically fix double patterning violations. Expanded features include DP-aware pattern matching, coloring aware pin access, pre-coloring of critical nets, and DP aware placement. The Calibre InRoute product allows Olympus-SoC customers to natively invoke Calibre signoff engines during design for efficient and faster manufacturing closure.

Double patterning also impacts LVS and other DRC issues, and the flows provide methodology details to address these areas, including hierarchical decomposition to reduce data base explosion. Parasitic extraction methodologies and scripts are provided as well, offering ways to address double patterning-induced variations via DPT corners or with maskshift PEX features.

Peregrine Semiconductor Corporation, a fabless provider of high-performance radio frequency integrated circuits (RFICs), today announced the signing of a collaborative agreement with Murata Manufacturing Company on a multi-sourcing arrangement for RF switches based on Peregrine’s proprietary UltraCMOS technology. Under the collaboration agreement, Murata agrees to source a majority of its RF switching requirements from Peregrine in exchange for being granted a license to purchase or manufacture RF CMOS switches utilizing Peregrine’s technology and intellectual property (IP). The parties expect this agreement to result in an expanded source of supply for these critical RF components and to assure global OEMs broad access to RF CMOS products.

Peregrine Semiconductor pioneered RF CMOS-based devices with its UltraCMOS technology, a form of silicon-on-insulator (SOI) process, and more than 20 years of research and development have resulted in 150 patents issued and pending. With this strong IP portfolio, Peregrine has established its position in the RF front-end section of mobile devices for RF switches and tunable RF components.

Murata is a supplier of RF front-end (RFFE) modules for the global mobile wireless marketplace. RF front-end modules are products that incorporate RF switches and tuning devices with SAW filters, passive components, and advanced packaging techniques.

“Global OEM customers of both Peregrine and Murata have for some time requested that the companies implement an independent source of supply for the critical switching elements that are widely utilized in today’s smart phones and other wireless-communications products,” said Jim Cable, Peregrine’s president and CEO. “This agreement marks the first license of Peregrine’s switch-based intellectual property to a third party; we look forward to working collaboratively with Murata to expand the deployment of UltraCMOS technology.”

Aptina’s board of directors yesterday announced that Phil Carmack has joined Aptina as chief executive officer and as a member of the board of directors. Aptina is a provider of CMOS image sensor solutions.

“We are extremely pleased that Phil is joining Aptina. Phil’s impressive industry experience and leadership skills will unleash Aptina’s potential and take the company to the next level,” said Nicholas Brathwaite, chairman of the board of Aptina.

Carmack most recently served as the senior vice president for NVIDIA’s Mobile Business Unit, which he established in 2003. Prior to his 13 years at NVIDIA, Carmack was the executive vice president of Research and Development at 3DFX Interactive, Inc. which was acquired by NVIDIA. His professional experience also includes leadership positions with innovative Silicon Valley companies including senior vice president and COO for Gigapixel and chief executive officer and founder of Raydiant, Inc. Carmack earned a Bachelor of Science degree in Electrical Engineering at Brigham Young University and a Master of Science degree in Electrical Engineering from Stanford University.

Carmack succeeds Nicholas Brathwaite who has been Aptina’s interim CEO since August 2012. Brathwaite will continue in his role as the chairman of the board of directors for Aptina, a position he has held since July 2009.

Aptina is a global provider of CMOS imaging solutions that enable Imaging Everywhere.

The semiconductor industry’s march toward broader 3D IC integration marked an important milestone this week at the 2013 Electronic Components & Technology Conference (ECTC), with the report of an advanced new temporary bonding solution for 3D Through-Silicone-Via (TSV) semiconductor packaging. The breakthrough was unveiled during ECTC’s 3D Materials and Processing session, when Ranjith John, materials development and integration engineer at Dow Corning, presented a paper co-authored by Dow Corning, a developer of silicones, silicon-based technology and innovation, and SÜSS MicroTec, a supplier of semiconductor processing equipment.

The paper, titled Low Cost, Room Temperature Debondable Spin on Temporary Bonding Solution:  A Key Enabler for 2.5D/3D IC Packaging, details the development of a bi-layer spin-on temporary bonding solution that eliminates the need for specialized equipment for wafer pretreatment to enable bonding or wafer post-treatment for debonding. Thus, it greatly increases the throughput of the temporary bonding/debonding process to help lower the total cost of ownership. 

“This advance underscores why Dow Corning values collaborative innovation. Combining our advanced silicone expertise with SÜSS MicroTec’s knowledgeable leadership in processing equipment, we were able to develop a temporary bonding solution that met all critical performance criteria for TSV fabrication processes. Importantly, the spin coat-bond-debond process we detailed in our co-authored paper takes less than 15 minutes, with room for further improvement,” said John. “Based on these results, we are confident that this technology contributes an important step toward high-volume manufacturing of 2.5D and 3D IC stacking.”

Both 2.5D and 3D IC integration offer significant potential for reducing the form factor of microelectronic devices targeting next-generation communication devices, while improving their electrical and thermal performance. Cost-effective temporary bonding solutions are a key enabler for this advanced technology by bonding today’s ultra-thin active device wafers to thicker carrier wafers for subsequent thinning and TSV formation. However, in order to be competitive, candidate temporary bonding solutions must deliver a uniformly thick adhesive coat, and be able to withstand the mechanical, thermal and chemical processes of TSV fabrication. In addition, they must subsequently debond the active and carrier wafers without damaging the high-value fabricated devices.

Through their collaboration, Dow Corning and SÜSS MicroTec were able to develop a temporary bonding solution that met all of these application requirements. Comprising an adhesive and release layer, Dow Corning’s silicon-based material is optimized for simple processing with a bi-layer spin coating and bonding process. Combined with SÜSS MicroTec equipment, the total solution offers the benefits of simple bonding using standard manufacturing methods. In their co-published paper, the collaborators report a solution exhibiting a total thickness variation of less than 2 µm for spin-coated films on either 200- or 300-mm wafers. The bonding material exhibited strong chemical stability when exposed to phosphoric acid, nitric acid, organic solvents and other chemicals familiar to TSV fabrication. In addition, the bonding solution and paired wafers showed good thermal stability when exposed to the 300°C temperatures common to the TSV process.

Dow Corning builds on a long history of silicon-based innovation and collaboration in semiconductor packaging. From die encapsulants for stress relief, to adhesives for sealing and bonding, to thermal interface materials for performance and reliability, Dow Corning’s well-established global infrastructure ensures reliable supply, quality and support, no matter where you are in the world.

OMRON Corporation today announced that they have finished development work on the world’s first infrared sensor manufactured with wafer-level vacuum packaging technology to create a 16×16 element MEMS non-contact infrared thermal sensor capable of highly precise 90-degree area detection. OMRON says it will ship test samples beginning in October 2013.

In recent years, the demand for human presence sensors has been growing in tandem with the demand for energy-efficient "smart home" and "smart office" environments, in which lighting, heating, etc. is automatically controlled according to where people are positioned. Since conventional pyroelectric human presence sensors (motion sensors) are only able to detect people when they are in motion, they are not as suitable for detecting the number of people in a certain space or their relative positions as Omron’s new thermal sensor.

MEMS non-contact thermal sensors measure temperature by converting infrared energy radiated from target objects into heat with MEMS thermopiles and then measuring the thermoelectromotive force resulting from temperature differences that occur across the contact points of two different types of metal. However, up till now it has not been possible to create large temperature differences across the metal contact points because much of the heat generated by the thermopiles dissipates into the surrounding air, meaning that the resulting thermoelectromotive force is reduced thereby limiting sensitivity. Omron believes they solved this heat dissipation problem by vacuum sealing the thermopiles inside the chip – the first time this has been achieved. The reduction in heat dissipation leads to a greater temperature difference across the metal contacts thereby increasing sensitivity.

How non-contact thermal sensors work

MEMS thermal sensor wafer level packaging

Thermal sensors utilize the Seebeck effect in which thermoelectric force is generated due to the temperature difference at the contact points between two different kinds of metal. Thermopiles are created by serially connecting thermocouples consisting of N+ poly Si, P+ poly Si, and Al. By creating hot junctions on highly heat-resistant dielectric membranes, and cold junctions on highly heat-conductive silicon, it is possible to achieve high-energy conversion efficiency. Sealing thermopiles in a vacuum prevents the heat they create from dissipating into the air thereby increasing sensitivity. 

Omron will now also work on commercializing stand-alone human presence sensor modules by combining non-contact thermal sensors with algorithms that can accurately distinguish the number of people and their positions within a detected space.

Model versions of Omron’s new human presence sensors will be displayed at the "Nanomicro Biz" Exhibition at Tokyo Big Sight on July 3, 4, and 5.

The development of this new sensor was the result of research carried out in collaboration with Japan’s New Energy and Industrial Technology Development Organization.

 

Element Six today announced it has acquired the assets and intellectual property of Group4 Labs, Inc. (Group4), a semiconductor wafer materials company that manufactured gallium nitride (GaN) on-diamond semiconductor technology for RF and high-power devices. The asset acquisition will expand Element Six’s semiconductor portfolio for defense and commercial applications.  The assets were acquired through an assignment for the benefit of creditors from Group4 LLC.

Group4 developed the first commercially available composite semiconductor wafer that includes GaN and diamond. Designed for manufacturers of transistor-based circuits with high power, temperature and frequency characteristics, the first-ever GaN-on-diamond system enables rapid, efficient and cost-effective heat extraction. This process reduces the operating temperatures of packaged devices, addressing heat issues that account for more than 50 percent of all electronic failures. Synthetic diamond dissipates heat up to five times better than existing materials, such as copper and silicon carbide, enabling device manufacturers to produce smaller, faster and higher power electronic devices, with longer lifespans and improved reliability.

When implemented within power amplifiers, microwave and millimeter wave circuits, GaN-on-diamond systems pose numerous benefits and applications within the defense and commercial sectors. This includes deployment in cellular base stations, radar sensing equipment, weather and communications satellite equipment, and inverters and converters typically used in hybrid and electronic vehicles.

The Group4 GaN-on-diamond technology was a critical element of TriQuint Semiconductor’s device, which won the Compound Semiconductor Industry Award in March. TriQuint demonstrated its new GaN-on-diamond, high electron mobility transistors (HEMT) in conjunction with partners at the University of Bristol, Group4 and Lockheed Martin under the Defense Advanced Research Projects Agency’s (DARPA) Near Junction Thermal Transport (NJTT) program. TriQuint has designed devices using this technology to achieve up to a three-fold improvement in heat dissipation, the primary NJTT goal, while preserving RF functionality. This would translate into a potential reduction of the power amplifier size or increasing output power by a factor of three.

“GaN-on-diamond wafers are poised to take a center seat in many of our customers technology roadmaps, as new developments demonstrate its ability to dramatically reduce device temperatures, while maintaining output performance,” said Adrian Wilson, head of technologies for Element Six. “With the acquisition of the GaN-on-diamond process developed by Group4, we plan to continue to support the market’s growth trajectory, ramping up manufacturing capabilities to deliver innovative synthetic diamond solutions to meet emerging market demands.”

Founded as a startup in 2003, Group4 has partnered with Element Six since 2008.

“The scaling up of GaN-on-diamond wafer manufacturing volumes will need the unique heft, skill, and synergy of Element Six to make it possible,” said Felix Ejeckam, Chairman and CEO of Group4.  “We believe that our customers will benefit enormously from this GaN-on-diamond process acquisition.”

Element Six’s Technologies division continues to experience strong market success, growing 20 percent per annum.