Category Archives: Packaging

Despite facing five consecutive quarters of decline and a slowdown in consumption in smartphones and tablets, the global market for NAND flash memory pulled off a surprise growth spurt during the last three months of 2012, causing sales to reach a record high.

NAND industry revenue in the October to December period of 2012 amounted to $5.6 billion, up an impressive 17% from $4.8 billion in the third quarter, according to an IHS iSuppli Flash Dynamics Market Brief from information and analytics provider IHS. Samsung Electronics, with more than a third of total revenue, led the field. NAND flash revenue for the entire year of 2012 amounted to $20.2 billion.

NAND flash growth

 

“The NAND flash market’s expansion in the fourth quarter was significant in two ways,” said Ryan Chien, analyst for memory and storage at IHS. “Not only did the increase defy the recent trend of sales sliding during the last quarter of a year, the expansion also resulted in the period having the largest revenue results in industry history. Major contributors to NAND strength in the fourth quarter included smartphones and tablets, even though density growth is projected to slow in 2013 for each smartphone, and has been negative for tablets since 2010. For these markets, rising volumes trumped the trend of slower growth in memory usage in the fourth quarter.”

Also playing a notable role in driving NAND growth during the period were solid state drives, along with retail flash products like flash drives and flash cards that likewise continue to attract significant consumer attention.

Flash bang

The 17% sequential growth in the fourth quarter last year was in stark contrast to the average 6% drop in revenue that had occurred during fourth-quarter periods for the previous five years. This time, growth was the result of solid product demand relative to preceding periods of weakness, coupled with a return to health for flash manufacturers. An important factor also was strength in component pricing, which fueled similar vigor in product pricing, stock pricing and—ultimately—revenue.

Overall, the revitalized state of the industry is attracting many new entrants, even though their presence is small in what is especially a scale-intensive space.

Samsung and Toshiba remain biggest players

The market share picture in the fourth quarter was similar to what it was a year earlier, with Samsung Electronics and Toshiba as the top two suppliers of NAND flash memory for the industry.

Samsung had fourth-quarter NAND revenue of approximately $2.0 billion, ending the year with a total of $7.5 billion or 37 percent market share. Samsung’s quarterly revenue since 2009 has hovered between $1.7 and $2.1 billion, helped by integration with its booming mobile device business, particularly smartphones.

Solid State Technology is pleased to announce Subu Iyer, IBM Fellow, will be giving the keynote address at The ConFab 2013 in Las Vegas on Tuesday, June 25, 2013. Iyer will speak on orthogonal scaling to fill today’s fabs in the future.

“Semiconductor technology development is at an inflection point where the historical expectations for node-to-node productivity are difficult to maintain,” Iyer writes in his abstract. “This slowing down of classical scaling is an opportunity to explore alternatives ways of leveraging both our technology and existing fab infrastructure. This talk will ask some tough questions on what we can really expect from recent technological innovations such as Hi K gate dielectrics and FINFETs in the future and what some other constraints are. We will explore the addition of orthogonal features to existing technologies that will enhance them significantly. Fabs of the future will be more diverse, offer a variety of novel capabilities, be more intimately tied to their clients whether they are captive or not, and will have to be a bigger part of the overall systems’ supply chain.”

Subramanian S. Iyer is an IBM Fellow at the Systems and Technology Group, and is responsible for technology strategy and competitiveness, embedded memory and three-dimensional Integration. He obtained his B.Tech at IIT-Bombay, and Ph.D. at UCLA. His key technical contributions have been the development of the world’s first SiGe base HBT, electrical Fuses, eDRAM and 45nm technology used at IBM and IBM’s development partners. His current technical interests and work lie in the area of 3-dimensional integration for memory sub-systems and the semiconductor roadmap. He is a Distinguished Alumnus of IIT Bombay and received the IEEE Daniel Noble Medal for emerging technologies in 2012.

For more information on The ConFab 2013 or to register, visit The ConFab section of our website.

A new undergraduate program approved this week at the University of Central Florida (UCF) will help the U.S. stay competitive in global technology as well as broaden the path for students seeking rewarding careers in the important field of optics and photonics, say leaders of SPIE, the international society for optics and photonics.

UFC photonics undergrad program
Photo: UCF

The UCF Board of Trustees yesterday announced a new Bachelor of Science degree program in photonics science and engineering, in partnership between the College of Optics and Photonics (CREOL) and the College of Engineering and Computer Science, said CREOL Director Bahaa Saleh. Students will receive their degrees from both colleges. The first classes of the new program will be offered this fall.

The curriculum is designed to prepare students for a wide variety of jobs in optics and photonics and to satisfy the requirements of ABET accreditation based on the criterion established by SPIE and IEEE for degrees in the field recently, Saleh said. ABET is a nonprofit, non-governmental organization that accredits college and university programs in the disciplines of applied science, computing, engineering, and engineering technology.

“I am personally excited to see this announcement because it serves as another indicator that optical and photonics engineering is finally coming of age as a discipline, providing a distinct program choice and career path for students to follow,” said Barry Shoop, professor and head of the Department of Electrical Engineering and Computer Science at the U.S. Military Academy in West Point, New York. Shoop leads the SPIE/IEEE team to develop ABET program criteria for optical and photonics engineering.

Shoop said that establishment of the new program also is “further evidence of the growth, influence, and importance of optical and photonics engineering as a discipline. This program joins a growing number of optical engineering programs across the country that are attracting some of the best and brightest students to serve the growing needs of industry, government and academia.”

“The program will help ensure that the U.S. has a chance to participate at all levels in the coming growth in photonics,” said SPIE CEO Eugene Arthurs. “As ABET moves to accredit programs in optics and photonics, UCF, long a leader in technology transfer programs and photonics education, is again showing its innovative drive. This timely new undergraduate program reflects the growing awareness of a vital field that has already changed the world in multiple ways – the Internet, laser surgery, and 3D imaging, to name a few — and that will continue to change the world many times over.”

Students in the new UCF program will study geometrical optics, physical optics, optical materials, and photonics devices and systems, striking a balance between general engineering breadth and basic knowledge and practical skills for solving problems and designing and building working optical systems, Saleh said. Along with core courses, the program will provide hands-on training in laboratories and a capstone senior design project, and participation in a summer internship program with local industry will be encouraged.

As UCF faculty were instrumental in the development of the new ABET program criteria for optical, photonics and similarly named engineering programs, this new program is anticipated to become ABET accredited, which will directly serve the growing need for photonic engineers and further increase the visibility and recognition of optical and photonics engineering as a discipline.

What else should the U.S. be considering to stay technologically competitive? Tell us in the comment section below. Comments will won’t be posted to your social media accounts unless you select to share.

The Institute of Microelectronics (IME), a research institute of the Agency for Science, Technology and Research (A*STAR) in Singapore, has launched the Copper (Cu) Wire Bonding Consortium II. The consortium which rides on the successes of Phase I launched in 2010 aims to improve the reliability of semiconductor devices by tackling copper wire bonding issues related to corrosion and stress. Members of this consortium span across the semiconductor supply chain including Atotech S.E.A., GLOBALFOUNDRIES, Heraeus Materials and Infineon Technologies.

Copper, which offers favorable cost, performance, quality and reliability benefits over gold, has become one of the preferred materials for wire bonding interconnects in microelectronics. Today, however, the industry still faces many technical challenges in developing copper as the best choice for chip-to-package interconnection. One of the key technical issues is related to copper’s hardness relative to gold, which requires bonding parameters to be very well controlled in order to eliminate the risk of damaging bond pads and underlying structures. Another daunting challenge of using copper is its reactivity with oxygen in the surrounding air which causes corrosion-related problems. These two issues can affect the reliability and quality of semiconductor devices.

Against this background, the IME Cu Wire Bonding Consortium II will conduct a study on corrosion and the mechanisms on the effect of various packaging materials. To understand the effects of copper wire hardness when bonding on different materials, the consortium will carry out modeling and characterization of copper wire bonding stress using stress sensors developed under the scope of Phase I of the Cu Wire Consortium to provide an improved technique of measuring wire bonding stress. The outcome of this work will enable semiconductor manufacturers as well as test and packaging houses to develop solutions to improve product reliability, especially those targeted at high reliability applications.

"IME has been dominant in the R&D of advanced packaging technologies and remains focused on developing solutions to help the industry reduce manufacturing costs,” said Prof. Dim-Lee Kwong, Executive Director of IME. “We are excited to begin a new phase of the Cu Wire Bonding Consortium to enable the development of robust, high reliability and low cost interconnection solutions."

“GLOBALFOUNDRIES is pleased to be in this consortium as the first phase of our partnership has successfully resulted in optimizing 0.7 mil in copper wire bonding on our 40nm product and passed the JEDEC reliability test,” said Mr. K. C. Ang, Senior Vice President and General Manager for GLOBALFOUNDRIES Singapore. “The success has brought us to the next phase of collaboration where the process will be tested on our advanced 28nm product. We see this industry collaboration truly augmenting the value proposition we have on offering quality and cost effective wafer manufacturing to our customers.”

“Infineon has been part of the Copper Wire Bonding Consortium since it first launched in 2010,” said Mr. Guenter Mayer, Senior Director, Package Technology and Innovation, Infineon Technologies Asia Pacific. “Today, our interest lies in copper wire bond interconnect performance and reliability in semiconductors that can meet the stringent quality requirements of Automotive and Industrial applications.”

“Being a member of the consortium enables Heraeus to work with strong industry partners and research institutes in order to have more in-depth understanding of wire bond reliability. The consortium members are of various backgrounds, such as wafer manufacturers, mold compound manufacturers and end users. The wafer manufacturers design pad structures that cater for the harder copper wire which created challenges on 1st bond mechanical stress during bonding and package reliability due to corrosion. Other partners are mold compound manufacturers and end users who can equally contribute to materials and assessment on best combination of package design, materials and application solution,” said Mr. Bernd Stenger, Executive Vice President, Contact Materials Division, Heraeus Materials Technology.

North America-based manufacturers of semiconductor equipment posted $1.07 billion in orders worldwide in February 2013 (three-month average basis) and a book-to-bill ratio of 1.10, according to the February Book-to-Bill Report published today by SEMI.  A book-to-bill of 1.10 means that $110 worth of orders were received for every $100 of product billed for the month.

The three-month average of worldwide billings in February 2013 was $975.3 million. The billings figure is 0.8 percent higher than the final January 2013 level of $968.0 million, and is 26.3 percent lower than the February 2012 billings level of $1.32 billion.

book-to-bill ratio semiconductor industry Feb 2013

“Three-month average bookings and billings posted by North American semiconductor equipment providers remain above parity and consistent with prior month levels," said Denny McGuirk, president and CEO of SEMI. "We expect modest investment by semiconductor makers in the first half of the year with foundry and advanced packaging technology among the near-term spending drivers.”

The SEMI book-to-bill is a ratio of three-month moving averages of worldwide bookings and billings for North American-based semiconductor equipment manufacturers. Billings and bookings figures are in millions of U.S. dollars.

The data was compiled by David Powell, Inc., an independent financial services firm, without audit, from data submitted directly by the participants. SEMI and David Powell, Inc. assume no responsibility for the accuracy of the underlying data.

The data is contained in a monthly Book-to-Bill Report published by SEMI. The report tracks billings and bookings worldwide of North American-headquartered manufacturers of equipment used to manufacture semiconductor devices, not billings and bookings of the chips themselves. The Book-to-Bill report is one of three reports included with the Equipment Market Data Subscription (EMDS).

SEMI is the global industry association serving the nano- and micro-electronic manufacturing supply chains. SEMI maintains offices in Bangalore, Beijing, Berlin, Brussels, Grenoble, Hsinchu, Moscow, San Jose, Seoul, Shanghai, Singapore, Tokyo, and Washington, D.C.

 

Zvi Or-Bach, President & CEO of MonolithIC 3D Inc. and Benjamin S. Louie of Zeno Semiconductor blog about dimensional scaling as it relates to EUV and future per transistor device cost.

At the IEEE International Solid-State Circuit Conference, the issue of dimensional scaling as it relates to EUV and future per transistor device cost was an important topic in the plenary session. One important, and perhaps overlooked, aspect of the industry’s scaling issue relates to the future of the SRAM bit-cell within this framework of dimensional scaling. We would like to shine some light on this impending issue.

As widely reported in the industry and articulated by ASML’s Executive VP & CTO Martin van den Brink at ISSCC 2013, there is substantial evidence that without EUV the cost of logic transistors is most likely going up with scaling. One slide he used to illustrate this is below:

Source: ASML

The above slide arrived after Martin had presented another non-encouraging slide, showing the same view from three companies: a Broadcom chart of increasing cost per gate correlated with dimensional scaling, together with the now famous Nvidia chart of no more crossover of transistor cost below 28nm, and third a GlobalFoundries chart showing some limited value for EUV.

 

 

 

We may attribute Martin statements to ASML interest in promoting EUV, but since ASML has already received significant EUV participation from INTEL, Samsung and TSMC, it might indicate further bumps are on the road to bringing EUV to market. We don’t know if EUV will ever become real, but we do know very well that it is been delayed, and delayed again, and delayed again. It was made public recently that EUV has probably already missed the 10nm process node -“10nm will be optical,” said Ajit Manocha, chief executive of GlobalFoundries.

An even more interesting slide was presented by van den Brink:

This chart brings up an important aspect of dimensional scaling that has not been discussed much before – the scaling of the SRAM bit-cell.  According to this chart, the SRAM bit-cell size might not be reduced from the 20nm to 10 nm node, and might even get larger at 7nm as it may need more than 8 transistors. (Sound familiar? Fabs are doing the same with BEOL metallization scaling…little or none).

Modern logic devices demand a significant amount of embedded SRAM. In fact, more than 50% of the typical logic device area is allocated for these SRAM as illustrated by the following chart of Semico (June, 2010).

The dominant embedded SRAM bit-cell architecture has been the 6 transistor cell (6T). And for many years this very cell has been hand-crafted using special design rules independently developed by foundries for every new technology node. It makes sense: the SRAM cell is a unique structure that does not obey normal logic design rules as it drives output against output anytime a write cycle is being performed. In many cases it is the SRAM cell that is the most sensitive portion of the logic device to process parameter variations and this sensitivity greatly impacts end device yield.

It well known that scaling the SRAM bit-cell has become harder and harder. Some vendors have already moved away from the 6T bit-cell in preference to the 8T (eight transistors) bit-cell.  ISSCC 2013 had a significant number of papers that were presented using 8T SRAM.  The few papers who kept the 6T SRAM embedded in their logic devices were forced to add read/write support circuits and additional overhead to enable the 6T bit-cell to function reliably.

Since SRAM bit scaling is now not able to keep up with logic scaling, the overall end device cost scaling could be even more disappointing than the transistor or gate cost illustrations above. 

Of course, well aware of this trend, IBM has been promoting their embedded DRAM solution for years. In the recent Common Platform Forum Dr. Gary Patton, VP, IBM Semiconductor R& D Center, was very pleased to share that in their 32nm product line the use of the embedded DRAM has given IBM the equivalent of a process node scaling benefit. Yet, as of now, most other vendors have not adopted eDRAM due to the process complexity and cost it adds to the logic process. It fair to assume that the appetite for eDRAM will not grow with dimensional scaling as the DRAM capacitor will be very hard to scale, the extra power for supporting DRAM will not be available and the cost of advance process development to add in extra complexity will be too high.

Accordingly we can learn from the recent ISSCC that dimensional scaling is facing the cost challenges we were aware of before in addition to new challenges that we might not have been aware of: the cost and the active/passive power handicaps due to the incompatibility of the 6T SRAM  bit-cell with scaling.

As we have suggested before, now that monolithic 3D is practical, we could advance and maintain Moore’s Law by augmenting dimensional scaling with 3D IC scaling. We could enjoy depreciated equipment charges for more years and much lower R&D engineering outlays that would bring down production and development costs, and also enjoy improvements to power and performance.

Another exciting option is to replace the 6T SRAM bit-cell with the 1T bi-stable floating body memory cell invented by Zeno Semiconductor.  The Zeno bit-cell provides two stable states, analogous to an SRAM while only consuming ~20% area of a traditional 6T SRAM and requires considerably less power.  The area and power savings over a traditional 6T SRAM improve further with scaling.  Most excitingly the Zeno bit-cell is compatible with existing logic processes. 

About the authors

Zvi Or-Bach is a well-known serial entrepreneur. He founded eASIC in 1999 and served as the company’s CEO for six years. eASIC was funded by leading investors Vinod Khosla and KPCB in three successive rounds. Or-Bach also founded Chip Express in 1989 (recently acquired by Gigoptix) and served as the company’s President and CEO for almost 10 years. In 2009 he founded and incorporated MonolithIC 3D Inc., a company that developed and patented a technology breakthrough for practical monolithic 3D-ICs.

Benjamin S. Louie has more than 16 years of experience in memory design including NOR Flash, NAND Flash and MRAM.  Most recently he led design efforts at Magsil, an MRAM IP company.  Prior to Magsil, Ben worked as a Design Manger at Micron Technology where he led the design development of Micron’s NAND program. 

Wafers with a diameter of 450mm enable the micro-chip industry an increase in yield of up to 80%. This leads to an enormous increase in productivity. In order to control the product quality, these wafers receive a specific marking from the manufacturer.

Promptly at the start of the year, InnoLas Semiconductor GmbH has successfully installed a second 450mm system. As an optional bridge-tool variant the system can mark 450mm and 300mm wafers on either side. The system checks the result automatically and thus reduces the process operations significantly. According to requirements the customer can choose between vacuum handling and edge-grip handling. The latter transports the wafers especially carefully and cleanly.

The company places particular emphasis on in-house developments and products in the application of high-precision components. Together with the robust further development of proven engineering this takes care of the constant high quality standard in marking and handling processes, also for the new wafer sizes.

 “The marking and handling quality will be maintained at our high level for the new wafer sizes. To achieve this we use components developed in-house whenever the requirements are of high precision. These are otherwise not available in suitable quality as required by us and our customers,” Andreas Behr, general manager of the InnoLas Semiconductor GmbH, explains the consistently high standard achieved by his wafer marking systems.

450mm wafer laser marking system

power design challenges and new product

ON Semiconductor will showcase its latest power efficient product advances at APEC 2013, March 17 – 21, 2013, in Long Beach, California. The new devices are designed for boosting performance and simplifying the design of offline power supplies, AC lighting infrastructure and motor control systems.

Targeted for high efficiency, compact, switch-mode power supplies for power adaptors, the NCP1937is a quasi-resonant (QR) flyback controller device with power factor correction (PFC).  This is the first AC-DC device utilizing a hybrid digital core architecture enabling higher efficiency, increased flexibility and easier system design implementation.  The device incorporates all the features necessary for building a robust and compact PFC stage in combination with a QR flyback stage while minimizing the number of external components.  The quasi-resonant current-mode flyback stage features a proprietary valley-lockout circuitry, ensuring stable valley switching. It has wide voltage range spanning 9 volts (V) to 30 V, plus built-in over-voltage protection, and a skip mode operation which enables higher efficiency in light load conditions.   The NCP1937 will be demonstrated in an 85 watt (W) Notebook Adapter showcasing the industry’s leading <10 milliWatt (mW) no load standby power.

The NCP1255/NCP1254 is a fixed frequency PWM controller designed for applications requiring peak power capability. Offered in SOIC-8 and TSOP-6 packages, it operates with a fixed 65 kilohertz (kHz) switching frequency with the ability to scale the frequency up to 130 kHz based on output load requirements. In light load conditions with the power on the secondary side decreasing, the IC automatically folds back its switching frequency to a minimum level (26 kHz). The inclusion of adjustable over-power protection and adjustable brown-out protection functions make this device ideal for products requiring peak-power capabilities such as printers, and ultrabooks.  The NCP1255 will be demonstrated in a 15 W nominal 55 W peak power printer adapter.

For LED power supply applications, the high functional integration of theNCL30081 PWM controller IC minimizes the number of external components required for AC powered LED lighting designs. It operates in a quasi-resonant mode to enhance overall efficiency and provides precision regulation of the LED current from the primary side. Dispensing with the need for secondary side feedback control, as well as the associated optocoupler and biasing circuitry, the device is specifically intended for very compact space efficient designs utilizing either flyback or buck-boost topologies. It supports step dimming by monitoring the AC line and detecting when the line has been toggled on-off-on by the user to reduce the light intensity in five steps down to five percent dimming.  The NCL30081 will be demonstrating the step dimming functionality and compact system solution in a standard GU10 bulb design.

The NSIC2020 is a linear constant current regulator based on Self-Biased Transistor (SBT) technology. Because these devices do not require the specification of any external components, they can serve as either high or low side regulators, thus offering a streamlined solution that makes the development process more straight forward and maximizes design flexibility. This compact SMB packaged device is capable of regulating current over a wide voltage range (from 0 V to 120 V). Its negative temperature coefficient enables protection of LED emitters from thermal runaway at extreme voltages and currents.

Also on display at the ON Semiconductor booth will be the LV8702V a high efficiency stepper motor driver IC housed in a compact SSOP package and targeted at office automation equipment applications (multi-function printers, copiers, scanners, etc.). It is capable of dramatically lowering no-load power consumption and peak motor current, thereby maximizing energy efficiency in system designs. The company’s latest 1200 V IGBTs using trench field stop topologies and 40 ampere (A) current ratings will be also be featured. Offering both low on state voltage and minimal switching loss, the IGBT is well suited for motor drive control and other hard switching applications.

Dynamic changes to R&D processes, tools, technical challenges, and funding/business models will be highlighted at SEMICON West 2013, along with product displays of the latest semiconductor manufacturing technology, components and subsystems. SEMICON West, the Western Hemisphere’s largest micro- and nano-electronics exhibition and conference, will be held July 9-11 at the Moscone Center in San Francisco. The event will feature over 500 exhibitors, 50 hours of conference programs and more than 30,000 industry attendees.  Registration is now open at www.semiconwest.org without charge until May 15; registration fees apply starting May 16.

The semiconductor industry is simultaneously addressing the most complex challenges in its history: EUV lithography, new transistor architectures, stacked 3D-ICs, and 450mm wafer transition.  At the same time, adjacent markets in LED, MEMS and printed/flexible electronics are approaching technology crossroads — and new, post-CMOS alternatives to extend Moore’s Law are in the early stages of development.  Reconciling these multiple R&D demands are transforming old R&D strategies and accelerating new organizational models, skill set requirements, consortia options, partnership strategies, global sourcing tactics, and other approaches to managed innovation.

SEMICON West addresses these new R&D approaches through a variety of keynote presentations, panel discussions, technical presentations, and collaboration sessions including:

  • Silicon Innovation Forum: Organized by the industry’s leading strategic investment groups, this first-time forum provides a platform to connect new and emerging companies with strategic investors, venture capitalists and industry leaders.
  • Consortia Views:  For the first time anywhere, leaders from the industry’s top consortia — SEMATECH, imec and CEA-Leti — will share their views on collaborative R&D and the future of semiconductor technology.
  • Keynote Perspectives:  Ajit Manocha, CEO, GLOBALFOUNDRIES
  • Essential R&D Process Sessions:  Nano-Defect Detection and Lab-to-Fab Solutions
  • Latest Technology Updates:  Industry leaders will share the latest updates on lithography scaling and productivity, processing requirements for nonplanar transistors, 2.5/3D stacked ICs, and 450mm wafer processing.
  • ITRS Public Sessions:  The most critical technology innovation targets as identified the International Technology Roadmap for Semiconductors.
  • New Technology Sessions:  Learn about the latest R&D opportunities and challenges in LEDs, MEMS, printed/flexible electronics, silicon photonics, and more.

SEMICON West is the annual tradeshow for the micro- and nano-electronics manufacturing industries. Last year, over 30,000 attended the event and over 500 companies exhibited the latest innovations and solutions for advanced manufacturing.  For the sixth year, SEMICON West will be co-located with Intersolar North America, the leading solar technology conference and exhibition in the U.S. Every major semiconductor manufacturer, foundry, fabless company, equipment and materials supplier — plus leading companies in LEDs, MEMS, displays, printed/flexible electronics, PV, and other emerging technologies — attend SEMICON West.

SEMI is the global industry association serving the nano- and microelectronics manufacturing supply chains.  SEMI maintains offices in Beijing, Bengaluru, Berlin, Brussels, Grenoble, Hsinchu, Moscow, San Jose, Seoul, Shanghai, Singapore, Tokyo, and Washington, D.C. 

Mobile energy storage is critical for everything from the phones and computers we carry, to the soldiers and weapons that protect us – and even to the cars we drive. While lithium-ion (Li-ion) batteries have established themselves as the leading technology today, exotic ideas such as lithium-air, lithium-sulfur, solid-state and zinc-air batteries offer up to 10 times better energy density. However, most are at early stages of development and none will attain parity with the Li-ion before 2024.

“The next generation of batteries remains mostly in research labs, undergoing fundamental development, and technologies led by Li-air, Li-S, and solid-state are still not yet ready for prime time,” said Cosmin Laslau, Lux Research Analyst and the lead author of the report titled, “Beyond Lithium-Ion: A Roadmap for Next-Generation Batteries.”

“However, customers will ultimately require the top-shelf performance that only technologies beyond Li-ion can provide – and leading companies like BASF, Toyota, and IBM are placing large and early bets,” added Laslau.

Lux Research analysts assessed the next-generation batteries, dispelling hype and identifying obstacles, and built a next-generation energy storage roadmap. Among their findings:

  • A roadmap for adoption. Cost-insensitive military applications will provide the entry point for next-generation batteries around 2020, while consumer electronics will follow a little later with significant adoption of solid-state batteries. However, next-generation batteries will face cost and technology hurdles in transportation.
  • Cost parity in a decade. Next-generation batteries will become cost-competitive with Li-ion in 2024. Solid-state batteries will take until 2021 to reach $409/kWh, the current cost for Li-ion batteries. By 2030, most battery cells will drop in nominal cost to below $200/kWh on the cell level.
  • Three early leaders emerging. Start-ups PolyPlus, Sion Power, and Oxis Energy have received ample funding and made technical headway. PolyPlus, funded by the U.S. Department of Energy, has developed a coating for protected lithium electrodes in Li-air and Li-S. Sion Power, backed by BASF, and Oxis Energy, financed by Sasol New Energy, own proprietary organic and polymer electrolytes for Li-S.

The report, titled “Beyond Lithium-Ion: A Roadmap for Next-Generation Batteries,” is part of the Lux Research Mobile Energy Intelligence service.

Lux Research provides strategic advice and ongoing intelligence for emerging technologies.