Category Archives: Packaging

Despite its high 19% CAGR, Flip-chip is not new – in fact, it was first introduced by IBM over 30 years ago. As such, it would be easy to consider it an old, uninteresting, mature technology, but this is far from true. Instead, Flip-Chip is keeping up with the times and developing new bumping solutions to serve the most advanced technologies, like 3D IC and 2.5D. No matter what packaging technology you’re using, a bumping step is always required at the end. In 2012, bumping technologies accounted for 81% of the total installed capacity in the middle end area. That’s big. Really big. So big that it represents 14M+ 12’’eq wafers – and fab loading rates are high as well, especially for the Cu pillar platform (88%). Flip-Chip is also big on value: in 2012 it was a $20B market (making it the biggest market in the middle-end area), and Yole Développement expects it to continue growing at a 9% clip, ultimately reaching $35 billion by 2018.

Flip-Chip capacity is expected to grow over the next five years to meet large demand from three main areas:

1) CMOS 28nm IC, including new applications like APE and BB

2) The next generation of DDR Memory

3) 3DIC/2.5D interposer using micro-bumping.

Driven by these applications, Cu pillar is on its way to becoming the interconnect of choice for Flip-Chip.

In addition to traditional applications which have used Flip-Chip for a while now (laptop, desktop and their CPUs, GPUs & Chipsets – which are growing slowly but still represent significant production volumes for Flip-Chip), Yole Développement’s analyst expects to see strong demand from mobile & wireless (smartphones), consumer applications (tablets, smart TV, set top box), computing and high performance/ industrial applications such as network, servers, data centers and HPC.

The new “Flip-Chip packaged ICs” are expected to radically alter the market landscape with new specific motivations that will drive demand for wafer bumping.

“In the context of 3D integration and the ‘More than Moore’ approach, Flip-Chip is one of the key technology bricks and will help enable more sophisticated system on chip integration than ever before,” says Lionel Cadix, Market & Technology Analyst, Advanced Packaging, at Yole Développement.

Flip-Chip is being reshaped by a new kind of demand that is hungry for Cu pillars and micro-bumps, which are on their way to becoming the new mainstream bumping metallurgy for die interconnection.

Meanwhile, Cu pillar is fast becoming the interconnect of choice for advanced CMOS (≤28nm), memory, and micro-bumping for 2.5D interposer and 3D IC.

In addition to studying mainstream bumping technologies, the Yole Développement report focuses on Cu pillar bumping, which is becoming increasingly popular for a wide variety of applications. The massive adoption of Cu pillars is motivated by a combination of several drivers, including very fine pitch, no UBM needed, high Z standoff, etc. Cu pillar Flip-Chip is expected to grow at a 35% CAGR between 2010-2018 in terms of wafer count. Production is already high at Intel – and by 2014, more than 50% of bumped wafers for Flip-Chip will be equipped with Cu pillars.

As early as 2013, micro-bumping for 2.5D & 3D IC, in conjunction with new applications like APE, DDR memory, etc., will boost Flip-Chip demand and create new challenges and new technological developments (see figure on the left). Today, Flip- Chip is available in a wide range of pitches to answer the specific needs of every application. The ultimate evolution in bumping technologies will consist of directly bonding IC with copper pads. 3D integration of ICs using this bump-less Cu-Cu bonding is expected to provide an IC-to-IC connection density higher than 4 x 105 cm-2, making it suitable for future wafer-level 3D integration of IC in order to augment Moore’s Law scaling.

Taiwan is the #1 location for Flip-Chip bumping

The major OSATs are preparing to produce fcBGA based Cu pillar packages and won’t limit the reach of cu pillar bumping to fcCSP. This will allow every company involved in CPU, GPU Chipset, APE, BB, ASIC, FPGA and Memory to access Cu pillar Flip-Chip technology. Cu pillar capacity is expected to grow rapidly over the 2010 – 2014 timeframe (31% CAGR), hitting ~9M wspy by 2014 and supporting the growing demand for micro-bumping and advanced CMOS IC bumping.

In the mutating middle-end area, CMOS foundries now propose wafer bumping services (TSMC, GLOBALFOUNDRIES, etc.), as opposed to bumping houses, which are dedicated to bumping operations (FCI, Nepes, etc.), and OSATs, which keep investing in advanced bumping technologies. In 2012, OSATs owned 31% of installed capacity in ECD solder bumping and 22% of installed capacity in Cu pillar bumping. A full overview of 2012 installed capacities for all bumping platforms is provided in this report.

Concerning geography, Taiwan has the biggest overall bumping capacity (regardless of the metallurgy), with important capacity coming from foundries and OSAT factories. Taiwan currently leads the outsourcing “solder & copper” Flip-Chip wafer bumping market. Flip-Chip market growth, spurred on by the emergence of the “middle-end” environment, has challenged traditional “IDM vs. fabless” supply chain possibilities more than ever before.

Spansion Inc. and United Microelectronics Corporation (UMC), today announced the joint development of a 40nm process that integrates UMC’s 40nm LP logic process with Spansion proprietary embedded Charge Trap (eCT)TM Flash memory technology. As part of this non-exclusive agreement, UMC is licensed to manufacture products based on this technology for Spansion.

Spansion embedded Charge Trap is a new high performance, low power, and cost- effective NOR Flash technology optimized for integration with advanced logic process in system-on-chip (SoC) products.  The technology is scalable beyond 40nm and can be integrated into High-k manufacturing process.  Spansion eCT technology is an enabler for expanding the roadmap for Spansion’s Programmable System Solutions (PSS), which combine Flash memory with configurable logic to enhance processing performance for applications that are memory, processing and MIPS intensive.

"Collaborating with UMC furthers Spansion’s licensing strategy," said John Kispert, president and CEO of Spansion. "By working with a leading foundry such as UMC, we can more effectively expand our PSS product roadmap and licensing business. In addition, we will enable others to take advantage of our Charge Trap technology, extending into new markets and bringing additional value to our customers."

"We look forward to working with Spansion to offer an industry leading logic platform that integrates our robust 40nm production process with their well-established Charge Trap memory technology,” W.Y. Chen, COO of UMC, said. “The result of the collaboration will deliver a cost-effective, innovative technology solution for customers designing into a wide range of market segments."

Spansion is a provider of the Flash memory technology at the heart of the world’s electronics systems, powering everything from the routers that run the internet to consumer and automotive electronics.

NAND flash memory tech development agreement
By Shigeru23 [CC-BY-SA-3.0 or GFDL], via Wikimedia Commons

After experiencing a slowdown in 2012, the global semiconductor market is set for growth. The World Semiconductor Trade Statistics predicts the global semiconductor market to grow by 4.5% in 2013 after declining 3.2 percent in 2012. The SPDR S&P Semiconductor ETF (XSD) has gained over 7% year-to-date. Five Star Equities examines the outlook for companies in the semiconductor industry and provides equity research on Avago Technologies Ltd. and NVIDIA Corporation.

The global semiconductor industry posted total sales of $291.6 billion in 2012, according to the Semiconductor Industry Association. The total was the third highest ever, but a decline of 2.7 from the record $299.5 billion set in 2011. The industry began to show some strength in the fourth quarter as it posted sales of $74.2 billion, which was a year-over-year increase of 3.8%.

"Despite substantial macroeconomic challenges, the global semiconductor industry outperformed forecasts and posted one of its highest yearly sales totals in 2012," said Brian Toohey, president and CEO, Semiconductor Industry Association. "Recent momentum, led by strength in the Americas, has the industry well-positioned for a successful 2013."

Avago Technologies serves three primary target markets: wireless communications, wired infrastructure, industrial and automotive electronics.

Five Star Equities provides market research focused on equities that offer growth opportunities, value, and strong potential return and was not compensated by any of the companies listed in its report.

Tensoft, an end-to-end ERP and supply chain solution provider for the semiconductor industry, announced today an agreement with GEO Semiconductor, the industry leader in high-performance, geometric processing solutions and inventor of the "eWarp" and "Realta" technology platform, to implement Tensoft’s integrated solution for the semiconductor industry, including Microsoft Dynamics and Tensoft Fabless Semiconductor Management (FSM). Tensoft’s FSM is a web-based product that supports semiconductor and related industry manufacturing processes.

GEO Semiconductor recently grew dramatically through its acquisition of Maxim Integrated’s Digital Video Processing Business. While this acquisition helps accelerate their market and corporate growth, it has also presented the need for additional infrastructure to support this growth, including an ERP and supply chain system that can be deployed very quickly.

"We needed a way to instantly scale in order to service our new customers following the Maxim product acquisition. Tensoft FSM has a known track record that we’re confident will allow us to meet this need," said Eric Erdman, GEO’s CFO. "Tensoft’s solution will enable our company to service our customers and to seamlessly manage all aspects of GEO’s production and financial operations."

"We’re really pleased to be working with Eric for a second time," said Bob Scarborough, Tensoft President and CEO. "It’s great to get the confirmation of repeat business — it’s a solid endorsement of our ability to be a trusted partner and to add value to rapidly growing companies. And, we really thrive on the challenge of delivering our products and adding our expertise in this kind of environment."

GEO Semiconductor develops programmable, high-performance geometric processor ICs, H.264 CODECS, video, audio and human interface technologies, focusing on smartphone peripherals, automotive cameras & HUDs, Smart TV, cloud and Skype communications as well as surveillance & video communication markets. The company is located in Santa Clara, CA with offices in Toronto and Orlando, and sales channels around the globe.

The adsorption of ions in microporous materials governs the operation of technologies as diverse as water desalination, energy storage, sensing and mechanical actuation. Until now, however, researchers attempting to improve the performance of these technologies haven’t been able to directly and unambiguously identify how factors such as pore size, pore surface chemistry and electrolyte properties affect the concentration of ions in these materials as a function of the applied potential.

Georgia Tech researchers
Georgia Tech associate professor Gleb Yushin (left) and graduate research assistant Sofiane Boukhalfa examine experimental results from their study of the adsorption of ions. (Credit: Gary Meek)

To provide the needed information, researchers at the Georgia Institute of Technology and the Oak Ridge National Laboratory have demonstrated that a technique known as small angle neutron scattering (SANS) can be used to study the effects of ions moving into nanoscale pores. Believed to be the first application of the SANS technique for studying ion surface adsorption in-situ, details of the research were reported recently in the journal Angewandte Chemie International Edition.

Using conductive nanoporous carbon, the researchers conducted proof-of-concept experiments to measure changes in the adsorption of hydrogen ions in pores of different sizes within the same material due to variations in solvent properties and applied electrical potential. Systematic studies performed with such a technique could ultimately help identify the optimal pore size, surface chemistry and electrolyte solvent properties necessary for either maximizing or minimizing the adsorption of ions under varying conditions.

“We need to understand this system better so we can predict the kind of surface chemistry required and the kinds of solvents needed to control the levels of ion penetration and adsorption in pores of different sizes,” said Gleb Yushin, an associate professor in the Georgia Tech School of Materials Science and Engineering. “Understanding these processes better could lead to the development of improved energy storage, water purification and desalination systems. This new experimental methodology may also give us paths to better understand ion transport in biological systems and contribute to the development of improved drugs and artificial organs.”

Georgia Tech associate professor Gleb Yushin (left) and graduate research assistant Sofiane Boukhalfa assemble a test cell used to study the adsorption of ions. (Credit: Gary Meek)

The research was supported partially by the U.S. Army Research Office, the Georgia Institute of Technology and the Oak Ridge National Laboratory (ORNL).

“The advantage of neutron scattering is that it can be used to study real systems,” said Yushin. “You can study most electrode materials and electrolyte combinations as long as they have a high sensitivity for neutron scattering.”

Yushin and his collaborators – Georgia Tech graduate research assistant Sofiane Boukhalfa, and Oak Ridge scientists Yuri Melnichenko and Lilin He – conducted the research using ORNL’s High Flux Isotope Reactor, which produces a beam of high-energy neutrons. Their experimental setup allowed them to immerse activated carbon fabric samples – each sample containing pores of different sizes – in different electrolyte materials while varying the applied electrical potential.

By measuring how the neutron beam was scattered when it passed through the carbon fabric and electrolytes, the researchers could determine how the solvent, pore size and electrical potential affected the average ion concentration in the carbon material samples.

This schematic shows the experimental setup for in-situ studies of ion adsorption on the surface of microporous carbon electrodes. (Credit: Gleb Yushin)

“You can learn whether the ions get adsorbed into small pores or large pores by simply comparing the changes in the neutron scattering,” Yushin explained. “This experimental technique allows us to independently change the surface chemistry to see how that affects the ion concentrations, and we can use different solvents to observe how the interaction between electrolyte and pore walls affects the ion adsorption in pores of different sizes. We can further identify exactly where the ion adsorption takes place even when no potential is applied to an electrode.”

Earlier work in this area had not provided clear results.

“There have been multiple prior studies on the pore size effect, but different research groups worldwide have obtained contradictory results depending on the material selection and the model used to determine the specific surface area and pore size distribution in carbon electrodes,” Yushin said. “Neutron scattering should help us clarify existing controversies. We have already observed that depending on the solvent-pore wall interactions, either enhanced or reduced ion electro-adsorption may take place in sub-nanometer pores.”

In their experiments, the researchers used two different electrolytes: water containing sulfuric acid and deuterium oxide – also known as heavy water – which also contained sulfuric acid. The two were chosen for the proof-of-concept experiments, though a wide range of other hydrogen-containing electrolytes could also be used.

Now that the technique has been shown to work, Yushin would like to expand the experimentation to develop better fundamental understanding about the complex interactions of solvent, ions and pore walls under applied potential. That could allow development of a model that could guide the design of future systems that depend on ion transport and adsorption.

“Once you gain the fundamental knowledge from SANS experiments, predictive theoretical models could be developed that would guide the synthesis of the optimal structures for these applications,” he said. “Once you clearly understand the structure-property relationships, you can use materials science approaches to design and synthesize the optimal material with the desired properties.”

Information developed through the research could lead to improvements in supercapacitors and hybrid battery-capacitor devices for rapidly growing applications in hybrid electrical vehicles, energy efficient industrial equipment, smart grid-distributed energy storage, hybrid-electric and electrical ships, high-power energy storage for wind power and uninterruptible power supplies.

GLOBALFOUNDRIES last week announced additional enhancements to the foundry’s 55nm Low-Power Enhanced (LPe) process technology platform – 55nm LPe 1V – with qualified, next-generation memory and logic IP solutions from ARM. The 55nm LPe 1V is the industry’s first and only enhanced process node to support ARM’s 1.0/1.2V physical IP library, enabling chip designers to use a single process that supports two operating voltages in a single SoC.

“The key advantage of this 55nm LPe 1V offering is that the same design libraries can be used whether you are designing at 1.0 voltage or 1.2 voltage power option,” said Bruce Kleinman, Vice President of Product Marketing at GLOBALFOUNDRIES. “What it means is that same set of design rules and models can be adopted, with no extra mask layer or special process required. This translates into cost saving and design flexibility without compromising on the power and optimization features.”

Based on ARM’s 1.0V/1.2V standard cells and memory compilers, GLOBALFOUNDRIES 55nm LPe 1V enables designers to optimize their design for speed, power and/or area and is especially beneficial for designers who are faced with power constraints in designing System-on-Chip solutions.

ARM offers a comprehensive, silicon-validated platform of 8-track, 9-track and 12-track libraries along with high-speed and high-density memory compilers for GLOBALFOUNDRIES’ advanced 55nm LPe process.

“The combination of 1V and 1.2V operation along with supporting level shifting logic provides the best combination of low power, high performance and reduced chip area,” said Dr. John Heinlein, vice president of marketing, Physical IP Division at ARM. “Dual-voltage domain characterization support coupled with Artisan next-generation memory compiler architecture reduces dynamic and leakage power by more than 35 percent, compared to previously available solutions.”

The 55nm LPe 1V is especially suited for high-volume, battery-operated mobile consumer devices, as well as a broad range of green or energy-saving products. PDK and EDA tools are available now, along with MPW shuttle availability.

Artisan memories offer flexible manufacturing options and are shipping in billions of products worldwide. Part of a broader platform of Artisan physical IP from 65nm to 20nm, these next-generation memories include low voltage and stand-by modes enabling extended battery life, ultra high-speed caches for maximum processor speed, and proprietary design techniques resulting in reduced area for low-cost SoC designs.

This week, India’s Finance Minister P Chidambaram offered incentives to chip makers to set up headquarters in India, in an effort to encourage local electronics manufacturing. However, the response from the industry has been less than positive. Many believe that it is a good start, but far from sufficient.

While presenting the Union Budget for 2013-14, Chidambaram said the Indian government will waive customs duty for plants and machinery in the semiconductor sector.

"We recognize the pivotal role of semiconductor wafer fabs in the ecosystem of manufacture of electronics. I propose to provide appropriate incentives to semiconductor wafer fab manufacturing facilities, including zero customs duty for plant and machinery," Chidambaram said, while presenting the budget.

"A company investing Rs.100 crore or more in plant and machinery during the (next fiscal) period will be entitled to deduct an allowance of 15 percent of the investment," he continued. "This will be in addition to the current rates of depreciation. There will be enormous spill-over benefits to small and medium enterprises."

While India has held its own in terms of semiconductor design, very little manufacturing is currently done in the country. Today, India has close to 4,000 electronics manufacturing units and about 300,000 units directly or indirectly supporting the electronics manufacturing industry. The Indian semiconductor design market is anticipated to grow to $14.5 billion by 2015, according to a report, but India’s electronic products manufacturing sector could shrink by as much as 7% in revenue during that same time, indicating that government efforts may not succeed.

As many in the industry know, the semiconductor industry lives and dies by Moore’s law, making fab-launching business ventures a risky move for any start-up.  With the need for constant equipment upgrades, many companies have turned to “fabless” business models, farming out their chip-making to established foundries.

“Building and running a fab is a complex business that is very sensitive to utilization and improvements in technology,” says Satya Gupta, chairman of the Indian Semiconductor Association. “Somebody who knows the fab business has to run it, not the government.”

Many experts point to India’s rising middle class as the main reason to consider India as a potential location for fabs. Much of India’s electronics are imported, meaning India is currently footing a huge import bill to meet the growing demand. As much as 65% of electronic products demand is currently met by imports, which is estimated to grow from $28 billion in 2011 to $42 billion in 2015, according to industry body Indian Electronics and Semiconductor Association, which also report that local manufacturers could lose out on nearly $200 billion of potential revenue by 2015.

But the import bill isn’t the only factor discouraging potential fab-owners.

"I wish it was as simple as offering an import duty exemption. What about availability of land, power and all other government clearances?" said a senior executive at one of the large computer manufacturers told the India Times, requesting anonymity.

What do you think of India’s efforts to encourage fabs? Let us know your thoughts in the comment section below.

At the International Semiconductor Strategy Symposium (ISS Europe), the European semiconductor industry affirmed its ability to innovate. More than 170 top industry representatives agreed on a number of joint steps and strategic measures to strengthen their competitiveness and sustainability. The controversial question whether the best way to attack future challenges will be "More Moore" or "More than Moore," ended in an expected compromise, namely that the industry should pursuit both strategies concurrently, the participants of a panel expressed. Whilst the More than Moore sector is traditionally strong in Europe, going on with More Moore is important for two to three device makers in Europe and in particular for the European equipment suppliers which export 80% of their products.

In a global scale, the semiconductor industry is approaching the move to 450mm wafer processing technology – a step that promises to greatly boost the productivity of semiconductor manufacturers. However, since the investment to build a 450mm fab easily exceeds the 10 billion dollar mark, this move is regarded as risky and, for this reason, reserved to only the very largest enterprises. In the past, this perspective divided the European industry into two camps – the "More Moore" group that advocates taking on the 450mm challenge, and the "More than Moore" group which shunned this risky investment and preferred to rely on application-oriented differentiation instead.

At the event SEMI Europe, an industry association embracing enterprises that represent the entire value chain and organizer of the ISS Europe, set up a high-ranking panel discussion on options and choices of a single European semiconductor strategy. The panel proved that entrepreneurial spirit is well alive among Europe’s chipmakers, technology suppliers and researchers.

Time is ripe to close the ranks and take on the challenges, as the speakers in the panel pointed out. Judged on the basis of its expertise and abilities, the European semiconductor and equipment industry has remarkable strengths, the experts said unanimously.

"We have to think in European terms," said Luc Van den hove, CEO of the Belgian research center Imec. "Talking in a common voice allows the European Commission to act and support this industry".

Jean-Marc Chery, Chief Manufacturing & Technology Officer of chipmaker STMicroelectronics, reminded that a holistic approach is necessary. "We have to push the full value chain cooperatively," he said.

The panel participants recognized that the European semiconductor industry possesses the necessary expertise. So far, the willingness to jointly face these challenges has been affected adversely by the macroeconomic environment and the Euro crisis, which discouraged far-reaching strategic decisions. The members of the European Commission that recently signalized understanding the needs of the semiconductor industry’s vital role for the high-tech location Europe, certainly contributed to the optimism in the industry.

"We have all the knowledge, the materials and the equipment," said Rob Hartman, Director Strategic Program for leading equipment manufacturer ASML, during the panel. "Let’s do it in the EU."

European Commissioner Neelie Kroes’ idea of creating an "Airbus for chips," a European initiative for the semiconductor industry comparable to the initiative that once led to the launch of the Airbus in the aviation industry, was strongly hailed by the panel.

"An Airbus for chips could be a very powerful tool," Van der hove said. "It does not need to be a single company, it also can be a framework of companies," added Laurent Malier, CEO of French research centre CEA-LETI.

The main concern of the industry is the slow decision process of the European institutions due to a complex political approval process inside of the European Union, the participants agreed. This industry is moving fast and so the decisions have to be taken fast, too. The strong Euro and the lack of qualified labor are further regarded as potential stumbling blocks for the technological progress and the business competitiveness.

At the panel the European Commission signalized its support for the industry as well.

“If policy instruments would be combined on EU and national levels, a critical mass of support for R&D for both More than Moore and More Moore could be achieved,” said Khalil Rouhana, Director Components & Systems at the European Commission.

brooks instruments mass flow controllerBrooks Instrument, a provider of flow measurement and control instrumentation to the microelectronics industry, will launch the GF135 pressure transient insensitive (PTI) mass flow controller at SEMICON China, March 19-21 at Shanghai New International Expo Center. In its first year at SEMICON China, Brooks will showcase the GF135 and its high-performance digital solutions for flow, vacuum and pressure measurement with partner SCH Electronics at booth 5505.

The GF135 improves yield and uptime with real-time integral rate-of-decay flow measurement and advanced diagnostic capabilities to verify accuracy, check valve leak-by and monitor sensor drift without stopping production. It provides market-leading actual process gas accuracy and ultra-fast flow settling time for reduced process cycle time. Onboard diagnostic data logging, zero stability trending and correction, and early detection of valve corrosion or clogging allow semiconductor manufacturers to achieve tighter tolerances and maintain uniformity in etch profiles and critical dimensions. The combination of these features allows the GF135 to deliver accuracy and cost savings to the semiconductor industry.

Additionally, Brooks will demo its GF81 mass flow controller, the new high-flow version of the GF80. The GF81 is the mass flow controller of choice for process engineers in solar, coatings and industrial thin-film applications. The GF81 offers flow rates up to 300 slpm, as well as a high-purity flow path. Unlike other high-flow mass flow controllers, it has a smaller footprint and offers the broadest range of communication protocols.

Based in Pennsylvania, Brooks Instrument is a multi-technology instrumentation company serving a range of markets. Brooks also owns Key Instruments, which offers precision machined acrylic flow meters, molded plastic flow meters, glass tube flow meters, and flow control valves. The company has manufacturing locations, sales, and service offices in the Americas, Europe, and Asia.

A researcher from North Carolina State University has developed a technique for creating high-density ceramic materials that requires far lower temperatures than current techniques – and takes less than a second, as opposed to hours. Ceramics are used in a wide variety of technologies, including body armor, fuel cells, spark plugs, nuclear rods and superconductors.

At issue is a process known as “sintering,” which is when ceramic powders, such as zirconia, are compressed into a desired shape and exposed to high heat until the powder particles are bound together into a solid, but slightly porous, material. But new research from Dr. Jay Narayan, John C. Fan Distinguished Chair Professor of Materials Science and Engineering at NC State, may revolutionize the sintering process.

Narayan’s new technique, selective-melt sintering, allows sintering of yttria-stabilized zirconia at 800 degrees Celsius (C) – instead of the conventional 1450 C. In addition, using the selective-melt sintering technique, it is possible to sinter zirconia at 800 C in less than a second, and create a material with no porosity at all. In contrast, traditional sintering techniques take four to five hours at 1450 C.

“This technique allows you to achieve ‘theoretical density,’ meaning it eliminates all of the porosity in the material,” Narayan says. “This increases the strength of the ceramic, as well as improving its optical, magnetic and other properties.”

The key to Narayan’s approach is the application of an electric field, at approximately 100 volts per centimeter, to the material. When this field is applied, it creates subtle changes in the material’s grain boundaries – where atoms from different crystals meet in the material. Namely, the field draws defects to the grain boundary. These defects consist of vacancies (missing atoms) which can carry charges. The defects are negatively charged and draw current from the electric field to the area – which raises the temperature along the grain boundary.

Raising the temperature along the grain boundary means that the material can be sintered at a much lower temperature, because sintering is done by selectively melting the grain boundaries to fuse the crystals together.

Normally you would have to apply enough heat to raise the mass of all the material to the melting point, even though you only need to melt the grain boundary. Pre-heating the grain boundary with an electric field is what allowed Narayan to lower the sintering temperature from 1450 C to 800 C and sinter the material much more quickly.

The work is described in two papers published online this month in Scripta Materialia. The papers are Grain growth model for electric field-assisted processing and flash sintering of materials, and an invited viewpoint paper, New mechanism for field-assisted processing and flash sintering of materials. Narayan is the sole author.