Category Archives: Packaging

STMicroelectronics (NYSE: STM) announced today another milestone in its testing of its 28nm FD-SOI Technology Platform. Following the Company’s December announcement of the successful manufacturing of System on Chip (SoC) integrated circuits, ST today announced that application-processor engine devices manufactured at the Company’s Crolles, France fab, were capable of operating at 3GHz with even greater power efficiency at a given operating frequency than alternate technologies.

This announcement follows on the heels of recent announcements from other organizations to utilize FD-SOI technologies. Moore’s Law—the observation that the number of transistors on a chip doubled about every two years—has driven the semiconductor industry over the past 50 years to shrink the size of the transistors, which are essentially miniature on/off switches. The increased density from these size reductions have given consumers the explosion of new and more exciting features at lower-cost that we’ve come to expect. In parallel, these new features are able to operate at clock speeds that allow the phones to respond to your commands—by keypad, touchpad, and now voice—almost before you finish expressing the command.

Now, as those transistors shrink to nanoscale dimensions where about 450 transistors can fit within the diameter of a human hair, physics are challenging the traditional high-speed and low-power advantages of planar CMOS technology manufactured on bulk silicon wafers. FD-SOI technology is a major breakthrough in the pursuit of miniaturization of electronic circuits, and the achievement of 3GHz operating speed for an application-processor engine presages the adoption of FD-SOI in portable equipment, digital still cameras, gaming and ASICs for a range of applications. Of the next-generation process technologies, FD-SOI alone has proven its ability to meet the industry’s highest performance and lowest power demands that are vital to delivering graphics and multimedia that amaze without sacrificing battery life.

“As we had anticipated, FD-SOI is proving to be fast, simple and cool; we had fully expected to see 3GHz operating speeds, the design approach is very consistent with what we had been doing in bulk CMOS, and, with the benefits of fully depleted channels and back biasing, the low-power requirements are also meeting our expectations,” said Jean-Marc Chery, Executive Vice President, General Manager Digital Sector, and Chief Technology and Manufacturing Officer of STMicroelectronics.

Reinforcing the point of simplicity, ST has found porting Libraries and Physical IPs from 28nm Bulk CMOS to 28nm FD-SOI to be straightforward, and the process of designing digital SoCs with conventional CAD tools and methods in FD-SOI to be identical to Bulk, due to the absence of MOS-history-effect. FD-SOI enables production of highly energy-efficient devices, with the dynamic body-bias allowing instant switch to high-performance mode when needed and return to a very-low-leakage state for the rest of the time – all in a totally transparent fashion for the application software, operating system, and the cache systems. Finally, FD-SOI can operate at significant performance at low voltage with superior energy efficiency versus Bulk CMOS.

It is a fact that semiconductor industry capital spending is becoming more concentrated with a greater percentage of spending coming from a shrinking number of companies.  As a result, IC industry capacity is also becoming more concentrated and this trend is especially prevalent in 300mm wafer technology.  The figure below lists the 300mm installed capacity leaders for 2012 and IC Insights’ forecast for 2013.  The list was compiled and included in IC Insights’ updated report titled, Global Wafer Capacity 2013—Detailed Analysis and Forecast of the IC Industry’s Wafer Fab Capacity.    As shown, Samsung was by far the leader in 2012 having about 61% more 300mm capacity than second-place SK Hynix. Intel was the only other company that held a double-digit share of 300mm capacity at the end of 2012.  Assuming Micron is successful in acquiring Elpida in 1H13, the combined 300mm wafer capacity of the two companies will make the merged company the second-largest holder of 300mm capacity in the world behind Samsung.

 Of the top 10 companies on the list, half are primarily memory suppliers, two are pure-play foundries, and one company, Intel, is focused on MPUs.  Samsung is expected to maintain its lead in installed capacity through 2017, with aggressive capital spending plans seen over the past few years continuing over the next five years.  However, in terms of growth rate, IC Insights expects the largest increase in 300mm capacity to come from the pure-play foundries—TSMC, GlobalFoundries, UMC, and SMIC.  In total, IC Insights expects these four companies to more than double their collective 300mm wafer starts per month by 2017.

 IC Insights believes that the companies listed will represent essentially all the advanced 300mm IC production and capacity in the future.  IC Insights believes that the top seven or eight companies—Samsung, “Micron-Elpida,” TSMC, SK Hynix, Intel, Toshiba/SanDisk, and GlobalFoundries—can be considered an “elite” group that is just about guaranteed to be a driving force in 300mm capacity additions.  The remaining companies are likely to participate in future 300mm capacity expansion, but all have varying degrees of risk associated with fully realizing their long-term 300mm IC production capacity goals.

Meanwhile, there is still much uncertainty as to when the industry will make the next wafer-size transition—from 300mm to 450mm—and how much it will cost to do so, but momentum continues to build and the transition can now be considered certain to happen.  IC manufacturers have yet to fully optimize the high-volume manufacturing cost structure for the 300mm wafer size.  However, the potential per-die cost savings that the larger wafer can provide is enough of a motivating factor to make the transition happen.

3-D integration with nanostructuresResearchers at North Carolina State University have developed a new type of nanoscale structure that resembles a “nano-shish-kebab,” consisting of multiple two-dimensional nanosheets that appear to be impaled upon a one-dimensional nanowire. However, the nanowire and nanosheets are actually a single, three-dimensional structure consisting of a seamless series of germanium sulfide (GeS) crystals. The structure holds promise for use in the creation of new, three-dimensional (3-D) technologies.

The researchers believe this is the first engineered nanomaterial to combine one-dimensional and two-dimensional structures in which all of the components have a shared crystalline structure.

Combining the nanowire and nanosheets into a single “heterostructure” creates a material with both a large surface area and the ability to transfer electric charges efficiently. The nanosheets provide a very large surface area, and the nanowire acts as a channel that can transmit charges between the nanosheets or from the nanosheets to another surface. This combination of features means it could be used to develop 3-D devices, such as next-generation sensors, photodetectors or solar cells. This 3-D structure could also be useful for developing new energy storage technologies, such as next-generation supercapacitors.

“We think this approach could also be used to create heterostructures like these using other materials whose molecules form similar crystalline layers, such as molybdenum sulfide (MoS2),” says Dr. Linyou Cao, an assistant professor of materials science and engineering at NC State and co-author of a paper on the research. “And, while germanium sulfide has excellent photonic properties, MoS2 holds more promise for electronic applications.”

The process, Cao says, is also attractive because “it is inexpensive and could be scaled up for industrial processes.”

To create the nano-shish-kebabs, the researchers begin by creating a GeS nanowire approximately 100 nanometers in width. The nanowire is then exposed to air, creating nucleation sites on the wire surface through weak oxidation. The nanowire is then exposed to GeS vapor, which forms into two-dimensional nanosheets at each of the nucleation sites.

“Our next step is to see if we can create these heterostructures in other materials, such as MoS2,” Cao says. “We think we can, but we need to prove it.”

The paper, Epitaxial Nanosheet–Nanowire Heterostructures, was published online Feb. 18 in Nano Letters. The lead author is Dr. Chun Li, a former postdoctoral researcher at NC State. Co-authors are Yifei Yu, a Ph.D. student at NC State; Cao; and Dr. Miaofang Chi of Oak Ridge National Laboratory. The research was supported by the U.S. Army Research Office.

ISSCC, the International Solid-State Circuits Conference, is being held on February 17-21, 2013, at the San Francisco Marriott Marquis Hotel. This year, in honor of the conference’s 60th anniversary, we have assembled highlights of the topics and trends that are being discussed. Click through to learn more about the trends and challenges facing the solid-state integrated circuits industry in 2013.

David Su, subcommittee chair of ISSCC 2013, wrote on data rates of modern wireless standards, which are increasing rapidly, as is shown in the table above. The data rate has increased 100x over in the last decade and another 10x is projected in the next five years. Read more.

MORE HIGHLIGHTS FROM ISSCC 2013   >>>

Infineon Technologies AG (FSE: IFX / OTCQX: IFNNY) has achieved a breakthrough in the manufacturing of power semiconductors on 300-millimeter thin wafers. In February, the company received the first customer go-aheads for products of the CoolMOS family produced by the 300-millimeter line at their site in Villach, Austria. The production process based on the new technology has completed qualification from start to finish and customers have given the go-ahead.

"Infineon put its faith in this manufacturing technology very early on and continued to invest even in economically difficult times. The qualification of our entire 300-millimeter line represents a veritable leap ahead of the competition," says Dr. Reinhard Ploss, CEO of Infineon Technologies AG. "300-millimeter thin-wafer manufacturing for power semiconductors will enable us, with the corresponding demand, to seize the opportunities that the market offers."

Infineon is the first and only company worldwide to produce power semiconductors on 300-millimeter thin wafers. Thanks to their larger diameter compared to standard 200-millimeter wafers, two-and-a-half times as many chips can be made from each one. Power semiconductors from Infineon feature low energy loss and compact design. Although not much thicker than a sheet of paper, the chips have electrically active structures on the front and back.

The next step is for the present manufacturing concept for CoolMOS products, qualified from start to finish, with the front-end site Villach and assembly of the thin chips at the back-end site Malacca, Malaysia, to be expanded to the front-end site Dresden. Here the focus is on high-volume production in a fully automated 300-millimeter line. The basis for the processes required and the manufacturing technology is currently being developed in research projects in Dresden. The technology transfer to Dresden is running on schedule and qualification of the first CoolMOS products will be completed in March. Shortly, in Villach more power semiconductor technologies will be transferred to the 300-millimeter line and produced. The development of the next power technology generation will focus on 300 instead of 200-millimeter technology.

"Our ability to innovate is the basis of our success – good ideas are turned into reality,” says Ploss. “In both Austria and in Saxony, we have the necessary conditions for this: technological know-how, well-educated and highly motivated specialists and exemplary support from government policy."

Last year, the independent research institute IMS Research (an IHS company) named Infineon as a market leader in power semiconductors. Infineon develops semiconductor and system solutions addressing three central challenges to modern society: energy efficiency, mobility, and security. In the 2012 fiscal year, ending September 30, the Company reported sales of Euro 3.9 billion with close to 26,700 employees worldwide.

Gas chromatograph by ShimadzuShimadzu Corporation today introduced the Tracera, a high-sensitivity gas chromatograph. Tracera is equipped with the newly developed barrier discharge ionization detector (BID), which is capable of detecting all types of trace organic and inorganic compounds, with the exception of helium (He) and neon (Ne), at the 0.1 ppm level (i.e. sub-ppm, where ppm refers to parts per million). Tracera GC is applicable for many types of high-sensitivity analyses typically performed with GC systems incorporating multiple detectors.

Background to Development

Gas chromatographs are used for research and development and quality control in a number of fields, involving petrochemistry, fine chemicals, the environment, pharmaceuticals, foods, electronics/semiconductors, and fragrances. In recent years, demands for higher sensitivity and trace quantity analyses have increased.

Thermal conductivity detectors (TCD) and flame ionization detectors (FID) are general-purpose detectors used in conventional gas chromatographs. A TCD detects a variety of inorganic and organic compounds, excluding the carrier gas component, but the sensitivity is insufficient. An FID is capable of detecting trace components at the ppm level, but can only detect organic compounds (excluding formaldehyde and formic acid). Analysis has thus required complex systems incorporating a variety of detectors to suit the target component.

With this issue in mind, Shimadzu has investigated the basics of plasma detection technology as a means for increasing sensitivity stability and the detectable concentration range. This has resulted in the barrier discharge ionization detector (BID), a new detector capable of the high-sensitivity detection of both organic and inorganic compounds, while providing excellent durability.

"The Tracera is a ground-breaking new system that combines this new type of detector, offering features not provided by conventional detectors, with the Shimadzu GC-2010 Plus high-performance capillary gas chromatograph," Said Masahito Ueda, general manager of GC & TA Business Unit, Analytical & Measuring Instruments Division. "It is expected to improve the efficiency of high-sensitivity, trace-quantity analyses, and to reduce equipment and analysis costs."

Main Features of This System

High Sensitivity—Achieves detection sensitivity over 100 times that of TCD, and over twice that of FID

The built-in barrier discharge ionization detector (BID) generates helium plasma. The extremely high photon energy of this plasma ionizes the sample components, enabling high-sensitivity detection. This system achieves at least 100 times the sensitivity of a conventional TCD, and at least twice the sensitivity of FID, enabling the detection of all types of trace components at the 0.1 ppm level.

Universal Detector—Capable of detecting both organic and inorganic compounds with no difference in sensitivity

The new BID helium plasma has an extremely high energy. It can detect all organic and inorganic compounds, with the exception of He and Ne, with no difference in sensitivity. It improves analysis sensitivity even with aldehydes, alcohols, and halides, for which sensitivity decreases with FID. A single Tracera system can perform analyses that conventionally required complicated systems equipped with multiple detectors and units. Examples include the analysis of hydrogen and organic compounds such as formic acid, generated as part of the reaction process during artificial photosynthesis, and the analysis of low concentration hydrocarbons and permanent gases generated in lithium ion rechargeable batteries.

Long-Term Stability—Adopts electrode-preserving plasma generation technology

With the new BID, the plasma is generated inside a quartz tube, so it makes no contact with the discharge electrode used for plasma generation. As a result, the detector electrode is not degraded, achieving long-term analytical stability.

Research and Markets has announced the addition of the "Global 3D IC Market 2012-2016" report to their offering.

TechNavio’s analysts forecast the global 3D IC market to grow at a CAGR of 19.7 percent over the period 2012-2016. One of the key factors contributing to this market growth is the huge demand for memory-enhanced applications. The global 3D IC market has also been witnessing the increase of multi-chip packaging. However, the thermal conductivity issues could pose a challenge to the growth of this market.

The key vendors dominating this market space are Advanced Semiconductor Engineering Co. (ASE), Samsung Electronics Co. Ltd., STMicroelectronics N.V., and Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC). Other vendors mentioned in the report include Elpida Memory Inc., IBM Corp., Intel Corp., and Micron Technology Inc.

“One of the emerging trends in the global 3D integrated circuit (IC) market is multi-chip packaging. In this type of packaging more transistors can be packed into a single 3D IC,” an analyst from TechNavio’s Hardware team said, commenting on the report.  “This type of packaging is very important for memory-enhanced applications because this approach enables improved interaction between the memory and the processor. It is expected that multi-chip packaging will be a promising approach for most applications in the future. Thus, vendors consider that multi-chip packaging is one of the crucial trends that will lead to the growth of the Global 3D IC market.’

According to the report, one of the major growth drivers is the increasing demand for 3D ICs in memory products (flash memory and DRAM). 3D ICs are able to improve the performance and reliability of memory products and can also help reduce their cost and size.

TechNavio’s report, the Global 3D IC Market 2012-2016, was prepared based on an in-depth market analysis with inputs from industry experts. The report covers the Americas, and the EMEA and APAC regions; it also covers the global 3D IC market landscape and its growth prospects in the coming years. The report also includes a discussion of the key vendors operating in this market. The study was conducted using an objective combination of primary and secondary information including inputs from key participants in the industry. The report contains a comprehensive market and vendor landscape in addition to a SWOT analysis of the key vendors.

The relentless march of process technology brings more integration and performance. IBM’s System z processor leads the charge at ISSCC 2013 clocking in at 5.7GHz and with 2.75B transistors.

The chip complexity chart below shows the trend in transistor integration on a single chip over the past two decades. While the 1 billion transistor integration mark was achieved some years ago, we now commonly see processors with beyond 2B transistors on a die.

Leveraging sophisticated strategies to lower leakage and manage voltage, variability and aging, has bolstered the continuing reduction in total power dissipation. This is helping rein in the increase in energy demands from PCs, servers, and similar systems. As power reduction becomes mandatory in every application, the trend towards maintaining near-constant clock frequencies also continues as shown below in frequency trends plot. This will yield solutions with less cost and cooling demands, resulting in greener products in the future.

Processors are choosing to trade off performance by lowering supply voltage. The performance loss of reduced voltage and clock frequency is compensated by further increased parallelism. Processors with more than eight cores are now commonplace. This year at ISSCC 2013, a 24-core processor from Fudan University will be presented as noted in the core count trend chart below.

In addition to the trend to integrate more cores on a single chip, multiple die within a single package are appearing. In ISSCC 2013, IBM will present a multi-chip module with six CPUs and two embedded DRAM cache chips. As well, dedicated co-processing units for graphics and communications are now commonly integrated on these complex systems-on-chip. Design of these SoCs requires broad collaboration across multiple disciplines including circuits, architecture, graphics, process technology, package, system design, energy efficiency and software. New performance and power-efficient computing techniques continue to be introduced at targeted, critical applications such as floating point and SIMD.

As technology continues to scale to finer dimensions, large caches are being integrated into microprocessor die.

Methods to communicate within-die as well as cross-die are becoming increasingly important. This is being driven by two trends: (1) 3D integration continues to grow in interest and (2) intra-die communications become more challenging with process scaling due increases in delay per unit interconnect length. Work on bringing package-level inter-chip transport onto the die has been gaining in popularity and we see this trend continuing.

This and other related topics will be discussed at length at ISSCC 2013, the foremost global forum for new developments in the integrated-circuit industry. ISSCC, the International Solid-State Circuits Conference, will be held on February 17-21, 2013, at the San Francisco Marriott Marquis Hotel.

SEMI, in collaboration with strategic investing groups throughout the global semiconductor industry, has announced the Silicon Innovation Forum, or SIF, to bridge funding gaps for new and early-stage companies with valuable semiconductor manufacturing and technology solutions. SIF will be held in conjunction with SEMICON West, on July 9, 2013 at the Moscone Center in San Francisco, Calif.  The event will consist of a one-half day conference highlighted by investment presentations from new and emerging companies with innovative technology solutions targeted at next generation semiconductors. The Silicon Innovation Forum is being organized by leading strategic investment groups in the industry including Applied Ventures, Dow Chemical Company, Intel Capital, Micron Ventures, TEL Venture Capital, and Samsung Ventures.

“At a time when the need for new ideas and technologies has never been greater, venture capital and private funding sources for advanced semiconductor technology development has significantly declined over the past decade, threatening the future of Moore’s Law and the economic engine of today’s connected, electronic society,” said Denny McGuirk, president and CEO of SEMI. “The Silicon Innovation Forum will address these funding gaps by providing a platform for new and emerging innovators, strategic investors, and venture capitalists to discuss the needs and requirements for next-generation technologies, and provide insights into technology, capital, partnership, and collaboration strategies necessary for mutual success.”

This unprecedented collaboration of leading strategic investor groups from throughout the world has formed to streamline and accelerate partnership opportunities for technology entrepreneurs to bridge the gap between R&D and product development funding.  The Forum will provide short-term business opportunities for early / mid-stage companies, R&D entrepreneurs from larger companies, and other industry innovators — while addressing long-term structural changes to the industry necessary to foster a healthy innovation pipeline.

New and emerging companies can showcase their innovations through table top and/or poster displays for one-on-one meetings with qualified investors, plus showcase their ideas during short pitches during the SiF Conference.  The SIF Conference will be free to all SEMICON West attendees, but the Innovation Showcase and Reception for one-on-one presentation and meeting opportunities will be restricted to qualified partnership and investor groups.

University at Buffalo engineers have created a more efficient way to catch rainbows, an advancement in photonics that could lead to technological breakthroughs in solar energy, stealth technology and other areas of research.

University of Buffalo engineerQiaoqiang Gan, PhD, an assistant professor of electrical engineering at UB, and a team of graduate students described their work in a paper called “Rainbow Trapping in Hyperbolic Metamaterial Waveguide,” published Feb. 13 in the online journal Scientific Reports.

They developed a “hyperbolic metamaterial waveguide,” which is essentially an advanced microchip made of alternate ultra-thin films of metal and semiconductors and/or insulators. The waveguide halts and ultimately absorbs each frequency of light, at slightly different places in a vertical direction, to catch a “rainbow” of wavelengths.

Gan is a researcher within UB’s new Center of Excellence in Materials Informatics. 

“Electromagnetic absorbers have been studied for many years, especially for military radar systems,” Gan said. “Right now, researchers are developing compact light absorbers based on optically thick semiconductors or carbon nanotubes. However, it is still challenging to realize the perfect absorber in ultra-thin films with tunable absorption band.

“We are developing ultra-thin films that will slow the light and therefore allow much more efficient absorption, which will address the long existing challenge.”

In their initial attempts to slow light, researchers relied upon cryogenic gases. But because cryogenic gases are very cold – roughly 240 degrees below zero Fahrenheit – they are difficult to work with outside a laboratory.

Before joining UB, Gan helped pioneer a way to slow light without cryogenic gases. He and other researchers at Lehigh University made nano-scale-sized grooves in metallic surfaces at different depths, a process that altered the optical properties of the metal. While the grooves worked, they had limitations. For example, the energy of the incident light cannot be transferred onto the metal surface efficiently, which hampered its use for practical applications, Gan said.

The hyperbolic metamaterial waveguide solves that problem because it is a large area of patterned film that can collect the incident light efficiently. It is referred to as an artificial medium with subwavelength features whose frequency surface is hyperboloid, which allows it to capture a wide range of wavelengths in different frequencies including visible, near-infrared, mid-infrared, terahertz and microwaves.

It could lead to advancements in an array of fields.

For example, in electronics there is a phenomenon known as crosstalk, in which a signal transmitted on one circuit or channel creates an undesired effect in another circuit or channel. The on-chip absorber could potentially prevent this.

The on-chip absorber may also be applied to solar panels and other energy-harvesting devices. It could be especially useful in mid-infrared spectral regions as thermal absorber for devices that recycle heat after sundown, Gan said.

Technology such as the Stealth bomber involves materials that make planes, ships and other devices invisible to radar, infrared, sonar and other detection methods. Because the on-chip absorber has the potential to absorb different wavelengths at a multitude of frequencies, it could be useful as a stealth coating material.

Additional authors of the paper include Haifeng Hu, Dengxin Ji, Xie Zeng and Kai Liu, all PhD candidates in UB’s Department of Electrical Engineering. The work was sponsored by the National Science Foundation and UB’s electrical engineering department.