Category Archives: Packaging

solid state thin film batteryVarious power factors have impacted the advancement and development of micro devices. Power density, cell weight, battery life and form factor all have proven significant and cumbersome when considered for micro applications. Markets for solid state thin-film batteries at $65.9 million in 2012 are anticipated to reach $5.95 billion by 2019, according to a new report released by ReportsnReports.com. Market growth is a result of the implementation of a connected world of sensors.

The report points out that development trends are pointing toward integration and miniaturization. Many technologies have progressed down the curve, but traditional batteries have not kept pace. The technology adoption of solid state batteries has implications to the chip grid. One key implication is a drive to integrate intelligent rechargeable energy storage into the chip grid. In order to achieve this requirement, a new product technology has been embraced: solid state rechargeable energy storage devices are far more useful than non-rechargeable devices.

Thin film battery market driving forces include creating business inflection by delivering technology that supports entirely new capabilities. Sensor networks are creating demand for thin film solid state devices. Vendors doubled revenue and almost tripled production volume from first quarter. Multiple customers are moving into production with innovative products after successful trials.

A solid state battery electrolyte is a solid, not porous liquid. The solid is denser than liquid, contributing to the higher energy density. Charging is complex. In an energy-harvesting application, where the discharge is only a little and then there is a trickle back up, the number of recharge cycles goes way up. The cycles increase by the inverse of the depth of discharge. Long shelf life is a benefit of being a solid state battery. The fact that the battery housing does not need to deal with gases and vapors as a part of the charging/discharging process is another advantage of the solid state thin film battery.

Traditional lithium-ion (Li-Ion) technology uses active materials, such as lithium cobalt-oxide or lithium iron phosphate, with particles that range in size between 5 and 20 micrometers. Nano-engineering improves many of the failings of present battery technology. Re-charging time and battery memory are important aspects of nano-structures. Researching battery micro- and nanostructure is a whole new approach that is only just beginning to be explored.

Industrial production of nano batteries requires production of the electrode coatings in large batches so that large numbers of cells can be produced from the same material. Manufacturers using nano materials in their chemistry had to develop unique mixing and handling technologies.

Cymbet millimeter scale solid state battery applications are evolving. In the case of the intra-ocular pressure monitor, it is desirable to place microelectronic systems in very small spaces. Advances in ultra-low power integrated circuits, MEMS sensors and solid state batteries are making these systems a reality. Miniature wireless sensors, data loggers and computers can be embedded in hundreds of applications and millions of locations.

wafer revenues decreaseWorldwide silicon wafer revenues declined by 12 percent in 2012 compared to 2011, according to the SEMI Silicon Manufacturers Group (SMG) in its year-end analysis of the silicon wafer industry. Worldwide silicon wafer area shipments declined 0.1 percent in 2012 when compared to 2011 area shipments.

In 2012, silicon wafer area shipments totaled 9,031 million square inches (MSI), down from the 9,043 million square inches shipped during 2011. Revenues totaled $8.7 billion down from $9.9 billion posted in 2011.

"Much like semiconductor unit shipments, semiconductor silicon shipments started out the year strong; however, shipments weakened during the second half of the year,” said Byungseop Hong, chairman of SEMI SMG and director of Global Marketing at LG Siltron. “Despite challenges in the market, 300 mm volume shipments reached record levels.”

Read more: When will the semiconductor industry recover?

Annual Silicon* Industry Trends

 

2007

2008

2009

2010

2011

2012

Area Shipments (MSI)

8,661

8,137

6,707

9,370

9,043

9,031

Revenues ($B)

12.1

11.4

6.7

9.7

9.9

8.7

*Shipments are for semiconductor applications only and do not include solar applications

Silicon wafers are the fundamental building material for semiconductors, which in turn, are vital components of virtually all electronics goods, including computers, telecommunications products, and consumer electronics. The highly engineered thin round disks are produced in various diameters (from one inch to 12 inches) and serve as the substrate material on which most semiconductor devices or "chips" are fabricated.

This report was compiled and released by the the Silicon Manufacturers Group, which acts as an independent special interest group within the SEMI association. The group’s purpose is to facilitate collective efforts on issues related to the silicon industry, including the development of market information and statistics about the silicon industry and the semiconductor market.

SEMI is the global industry association with over 2,000 members, serving the nano- and microelectronics manufacturing supply chains. 

Packaging and assembly are key segments of the growing semiconductor supply chain in China. Based on our tracking of 139 companies, and considering numerous small companies not tracked in detail, there are over 200 companies competing in the packaging and assembly market in China. Although many are small companies manufacturing low-pin count devices, all of the world’s “Top 10” OSAT, Outsourced Semiconductor Assembly and Test, players have one or more assembly and testing facilities in China as shown below. Eight of the world top 10 IDM companies have assembly and test manufacturing facilities in China, and most entered into China earlier than the OSAT players, in the mid-1990s.

Top Ten OSAT Facilities in China

1)    ASE

2)    Amkor

3)    SPIL

4)    STATS ChipPAC

5)    Powertech

6)    UTAC

7)    ChipMOS

8)    JCET

9)    KYEC

10)    Unisem

In addition to the international companies, domestic subcontractor companies are increasingly joining the global outsourcing market. The assembly of small-size optoelectronic chips like CMOS image sensors is the most mature 3D through-silicon via platform at the moment and China players occupy an important place through transferring authorized technology from oversea partners. Also, domestic semiconductor equipment suppliers that previously focused on front-end tool development are applying their products in wafer level package and TSV assembly.

With the growth of semiconductor packaging industry in China, domestic packaging material suppliers are emerging with the industry and are now starting to serve the worldwide leading packaging houses. Given the emphasis on low-cost manufacturing, packaging houses will continue to evaluate China-based suppliers to realize lower material cost. On the other hand, to enhance their competitive power, stabilize sales and marketing channels, and reduce operational risk, China-headquartered material suppliers are forming partnerships with leading packaging houses. In the China Semiconductor Packaging Market Outlook 2012/2013 report, we discuss semiconductor packaging material segment market and supply in China, and include both manufacturing facilities owned by foreign companies and domestic companies. 

In the first of two installments, we examine the global issues facing the semiconductor industry, as released by Linx Consulting in The Econometric Semiconductor Forecast. Part two predicts that semiconductor growth should recover by 2014.

United States’ economic outlook 

The January 1st “fiscal cliff” deadline in the US dominates the near term outlook for the world economy.  ANY settlement will stabilize the situation, but any politically acceptable near term agreement in Washington will not be enough to truly begin to solve the longer-term problems. The political dynamics are not yet in place to lead to a long-term solution to debt restructuring or reducing excessive growth in entitlements. The first fiscal cliff compromise, which includes higher taxes on the wealthier income-earners, elimination of the 2% social security tax reduction, and a permanent fix to the alternative minimum tax levels, gave clarity to consumers on their tax situations. Discretionary and entitlement government spending controls or cuts to reduce government debt burdens were deferred, leaving key questions about policy to later negotiations. That extension of uncertainty will dampen investment spending and government purchases of equipment at least into the first half of 2013. Economic growth will stagnate in the beginning of the year, and then bounce briefly when the new policy environment becomes clear.  Post bounce, the longer term issues will begin to re-surface, and economic growth should settle back into a sluggish trend that lags potential output. This modest growth will be slow to lower unemployment.  Without a strong labor market, businesses will plan for very modest gains in consumer spending, relatively low inflation, and no significant change in interest rates.

Europe’s economic outlook

Most economies are in mild recession, as central governments raise taxes and/or cut spending in attempt to reduce debt. Austerity measures, coupled with potential national bankruptcies in Greece, and recessions in Spain and Italy which will likely extend into early 2014, produce severe stress on euro currency. For the euro to survive, Germany and the most troubled countries will need to compromise national needs to develop an approach that will satisfy financial markets.  France introduces a growing uncertainty to the European outlook. It continues to head in the opposite direction from most countries, expanding the central government’s involvement in the economy, ignoring debt growth, and pushing income redistribution measures which could stifle growth. While the Eurozone should survive intact, the political process will likely keep markets uncertain and most countries’ fiscal budgets austere.  Overall economic activity measured by real GDP most likely will contract slightly in 2013.

Asia’s economic outlook

With key developed world markets in recession or growing weakly, Asian economies will have difficulty producing strong expansions in 2013. With the exception of Japan, however, rates of growth are likely to improve from 2012. Led by China, which moved a bit too aggressively to cool its economy in 2012, policies have become slightly more expansive across the region and should produce slightly stronger real growth rates. Growth will come more from internal regional development than export-led growth.

Risks affecting the semiconductor industry 

Negative risks dominate discussions among serious analysts. In Europe, a financial calamity from either a banking system failure or the breakup of the Eurozone would produce a severe recession with global implications. In the US, an imbalanced solution to the fiscal cliff could stifle growth and tumble the economy into a brief recession. Emerging commodity-focused or dependent economies would be negatively impacted by a weaker Asian expansion. Positive risks, which get very little discussion in popular press these days, include a much sharper boost in the US following a settlement of the “fiscal cliff” dilemma, and a slowly improving European situation (most likely led by Germany or a group of northern European economies) that stabilizes more rapidly the fiscal situation in Europe.  A number of US forecasters surveyed by the National Association for Business Economics on December 17th expect US growth to rebound sharply and exceed 3 ½% by the end of 2013 as the uncertainty “discount” is removed from markets. While an equal number expect growth to stagnate around 1%, the upside should be at least acknowledged as a possible upside risk to the current consensus.

A new econometric semiconductor industry forecast predicts semiconductor wafer area production to grow slightly less than 6% in 2013, according to Linx Consulting.

Using a macroeconomic forecasting tool that incorporates measures of economic uncertainty, global economic shocks, and regional volatility, the forecasting service, called The Econometric Semiconductor Forecast, predicts a slow first quarter in 2013 will be followed by a strong second quarter with moderate growth in the second half of the year. This modest growth forecast is believed to be demand-driven, since inventory levels have not shown a significant increase in 2012.

The Econometric Semiconductor Forecast is the first to use global GDP macroeconomic models to provide semiconductor industry forecasts at a quarterly frequency with monthly updates, allowing forecast recipients to plan for short-term fluctuations in the volatile semiconductor industry.

“An unstable global economy leads to wide variations in economic forecasts, making it difficult to develop meaningful demand-side forecasts,” said Mark Thirsk, managing partner of Linx Consulting. “Our econometric forecast model allows us to develop more accurate forecasts on a monthly and quarterly basis, which are vital for operations planning and business forecasting in the semiconductor supply chain.”

Based on a demand-driven equation that captures >98% of the long run variation in semiconductors, the economic forecast model used by Linx Consulting includes global real GDP growth from consensus forecasts, US consumer and business spending on technology goods, inventory-shipments ratio, computer and electronics, and financial crisis shock indicator to capture panic behavior in the latest cycle.

Headwinds in the Global Economy

Uncertainty surrounding government policies and ongoing fallout from the financial crisis combine to restrain growth in 2013. Protracted periods of uncertainty followed financial crises in the past, accompanied by prolonged subdued growth rates as major economic policies changed and debt restructuring dampened investment and spending.  Few of today’s policymakers or business leaders have experience dealing with this type of an environment. That lack of experience adds to the uncertainty in the current outlook, as it tends to increase cautious economic behavior by consumers and businesses. In 2013, policies should become a bit more settled in the first half of the year, improving confidence somewhat.  Global economic growth is unlikely to recover to its longer-term potential until after 2013 as fundamental structural imbalances will improve slowly at best.

In the face of these headwinds, the more than 250 forecasters surveyed in the December 2012 Consensus Forecasts produced a consensus subdued, below-trend global growth of 2.6% in 2013.  This is a slight improvement over the 2.5% now expected for 2012, but less than the 3.1% achieved in 2011 and below the long-term potential real global growth rate of around 3.5%.  While the consensus averages to 2.6% for 2013, there is a relatively wide range in individual forecasts, reflecting the uncertainty in the outlook.  Individual outlooks depend most on how forecasters see developments in the US and Eurozone.

Read more from The Econometric Semiconductor Forecast: Regional developments to affect growth of semiconductor industry

The forecasting service will provide subscribers with monthly updates of quarterly forecasts of total semiconductor production in Million Square Inches of silicon processed, as well as segmentation by device, including DRAM, flash, MPU, ASIC, analog and discrete.

 

TU DresdenTechnische Universität (TU) Dresden announced Monday the successful initial operation of a low-power test chip featuring a Tensilica Xtensa LX4 DSP equipped with RacyICs power management IP implemented in GLOBALFOUNDRIES’ advanced 28nm Super Low Power, or SLP, technology. The chip is able to operate in a wide voltage and frequency range from 0.7V to 1.1V and 90 MHz to 1 GHz. Within that range, the optimal voltage/frequency combination is determined adaptively based on a new hardware performance monitor concept. The complete baseline IP was developed by the university team, who also did logic synthesis, place and route and sign-off of the test chip.

"Our ability to successfully realize microchips in advanced technologies is a result of a long-term strategy to build an experienced team, which covers all aspects of analog, digital and mixed-signal IC design," stated Professor René Schüffny, TU Dresden. "This accumulated engineering competence is one key enabler for TU Dresden’s leading-edge research in the field of complex systems based on advanced electronics."

The chip has been developed within the frame of the CoolRF28 project. This project is part of the Leading-Edge Cluster "Cool Silicon," which is sponsored by the German Federal Ministry of Education and Research, or BMBF, within the scope of its Leading-Edge Cluster Competition. In the "Cool Silicon" cluster, universities, research institutes, small and medium enterprises, or SMEs, and big corporations closely cooperate in numerous projects on the next generation of energy-efficient electronics.

"We’re very impressed by the high research and engineering competence of the TU Dresden team," stated Frank Dresig, GLOBALFOUNDRIES’ European Field Engineering Manager. "The chip directly shows the capabilities of our advanced 28nm SLP process for implementation of ultra low-power SoCs for consumer applications."

The test chip’s power management is based on an IP for adaptive voltage and frequency scaling provided by RacyICs, a start-up company offering design and implementation services.

"The close cooperation with TU Dresden and GLOBALFOUNDRIES helps us to develop world-class services and IP products in advanced technology nodes," stated Holger Eisenreich, RacyICs’ Managing Director. "Because of high risks and costs, it is almost impossible for SMEs to enter this market without such cooperation."

With assistance from Tensilica, the university team integrated an Xtensa LX4 DSP core to demonstrate the overall power reduction benefits from the combination of a 28nm low-power technology, adaptive power management and an advanced processor IP core.

"Tensilica has had a long-standing relationship with the researchers at TU Dresden and congratulates them on this successful design effort," stated Chris Rowen, Tensilca’s CTO. "Tensilica’s Xtensa processor is a fundamental building block in TU Dresden’s wireless communications architecture, and we are working together to proliferate know-how on configurable architectures to the worldwide design community."

Technische Universität Dresden, founded in 1828, is a full-scale university with 14 faculties, covering a wide range of fields in science and engineering, humanities, social sciences and medicine. TU Dresden has about 36,500 students and almost 5,319 employees with 507 professors among them, and is the largest university in Saxony today. 

ISMI to partner with Araca


February 6, 2013

SEMATECH announced today that Araca Inc., a leading provider of products and services for chemical mechanical planarization (CMP) research and development, and the International SEMATECH Manufacturing Initiative (ISMI) are partnering to deliver CMP processing and productivity solutions to help chip manufacturers increase yields, reduce equipment downtime and lower consumables costs.

“Leading-edge device designs and materials are introducing more complexity into planarization processing for manufacturers. This is increasing wafer costs and impacting die yields,” said Dr. Ara Philipossian, president and founder of Araca, Inc. "Partnering with ISMI allows us to validate our CMP Slurry Injector System (SIS-x) and other innovations in high-volume manufacturing facilities across the industry. This technical collaboration with the industry’s leading device manufacturers is vital to our success as we develop and commercialize high-performing and cost-effective CMP solutions.”

As a part of ISMI’s Manufacturing Technology program, Araca and ISMI will evaluate Araca’s CMP SIS-x system on varying consumable set-ups on select types of CMP equipment at ISMI members’ manufacturing locations to help increase removal rates while reducing polishing defects and slurry consumption for CMP processes.

“Cost and productivity are major obstacles in CMP, in addition to eliminating process variables that arise from equipment generated variation. While this applies equally to new and legacy processes, this is especially true for sub-20 nm high-volume manufacturing,” said Boyd Finlay, ISMI project manager.

ISMI is working cooperatively with the semiconductor industry to provide solutions to common high-volume productivity and cost detractors. ISMI’s Manufacturing Technology Program leads various equipment productivity improvement projects including CVD/PVD/etch particle elimination, CVD pump failures and chamber dusting prevention, electrostatic chuck cost-of -ownership, equipment variation and control, and defect source and root cause analysis.

ISMI also provides industry leadership through the ESH Technology Center, focusing on sustainability and green initiatives, addressing regulatory issues, and resource conservation in manufacturing operations.

ISMI membership is open to all semiconductor manufacturers and suppliers. ISMI and its members collaborate with a broad network of companies, consortia, universities, national laboratories, and associations from around the world to tackle manufacturing and ESH technology challenges.

Microchip Technology Inc. introduced three new SPI Flash memory devices yesterday. The devices, named the SST25PF020B, SST25PF040B and SST25PF080B, offer two, four and eight Mbit of memory and are manufactured with Microchip’s high-performance SuperFlash technology, a split-gate, NOR Flash design with thick-oxide tunneling injector for superior quality and reliability.

“With their extended voltage, smaller footprint and low power consumption, this SST25PFXXXB SPI Flash family provides designers with even simpler, more economical and more innovative memory solutions for their embedded designs.”

With their extended operating voltage range from 2.3 to 3.6V, extremely low power consumption, small-footprint packaging, and fixed super-fast program and erase times, these SPI Flash memory devices excel in a variety of applications. The memory is partitioned into uniform 4 Kbyte sectors, and 32 and 64 Kbyte blocks, offering flexible erase capabilities and seamless partitioning for program and data code in the same memory block. All three devices enable designers to reduce their overall product design cycles and total system costs while improving product performance. The extended voltage range provides designers with a wider set of options on the power-supply voltage for their chipsets and board designs, and reduces overall power consumption, making these memory devices especially well-suited for battery-operated accessories, sensors and equipment.

The SST25PF020B, SST25PF040B and SST25PF080B SPI Flash devices offer flexible erase and program performance, including erasing sectors and blocks as fast as 18 ms, erasing the entire Flash memory chip in 35 ms, and a word-programming time of 7 µs using Auto Address Increment (AAI). The devices also offer superior reliability of 100,000 endurance cycles, typical, and greater than 100 years of data retention. The active read current of these devices is only 10 mA, typical, at 80 MHz, and standby current is only 10 µA, typical.

All three devices excel in a broad range of applications, including those in the consumer-electronics and industrial markets. Examples of ideal end applications include smart meters, wireless products for sports/fitness/health monitoring, digital radios, low-power Wi-Fi® products, GPS, and a wide array of battery-operated products. Additionally, these SPI Flash memory devices are well suited for use in medical applications, such as glucose meters, hearing aids and wireless sensors.

“Newer designs requiring greater mobility, along with more compact form factors, are driving lower-power and extended-voltage requirements,” said Randy Drwinga, vice president of Microchip’s SuperFlash Memory Division. “With their extended voltage, smaller footprint and low power consumption, this SST25PFXXXB SPI Flash family provides designers with even simpler, more economical and more innovative memory solutions for their embedded designs.”

Pricing & Availability

The SST25PF020B starts at $0.53 each, in 8-lead 150 mil SOIC, 8-contact USON (3×2 mm), or 8-contact WSON (6×5 mm) packages, in 10,000-unit quantities. The SST25PF040B starts at $0.66 each, in 8-lead 150 mil SOIC, 8-lead 200 mil SOIC, or 8-contact WSON (6×5 mm) packages, in 10,000-unit quantities. The SST25PF080B starts at $0.81 each, in 8-lead 150 mil SOIC, 8-lead 200 mil SOIC, or 8-contact WSON (6×5 mm) packages, in 10,000-unit quantities.

Image by IBM ResearchDow Corning and IBM scientists unveiled a major step in photonics yesterday at the Photonics West conference, using a new type of polymer material to transmit light instead of electrical signals within supercomputers and data centers. This new silicone-based material offers better physical properties, including robustness and flexibility, making it ideal for applications in Big Data and for the development of future exascale computers, which are capable of performing a billion billion computations per second.

With exabytes of structured and unstructured data growing annually at 60 percent, scientists have been researching a range of technological advancements to drastically reduce the energy required to move all that data from the processor to the printed circuit board within a computer. Optical interconnect technology offers bandwidth and power efficiency advantages compared to established electrical signaling.

“Polymer waveguides provide an integrated means to route optical signals similar to how copper lines route electrical signals,” said Dr. Bert Jan Offrein, manager of the Photonics Research Group at IBM Research. “Our design is highly flexible, resistant to high temperatures and has strong adhesion properties – these waveguides were designed with no compromises.”

In a collaboration with Dow Corning, the scientists fabricated thin sheets of optical waveguide that show no curling and can bend to a 1 mm radius and is stable at extreme operating conditions including 85 percent humidity and 85°C. This new polymer, based on silicone materials, offers an optimized combination of properties for integration in established electrical printed circuit board technology. In addition, the material can be fabricated into waveguides using conventional manufacturing techniques available today.

“Dow Corning’s breakthrough polymer waveguide silicone has positioned us at the forefront of a new era in robust, data-rich computing, especially as we continue to collaborate with outstanding industry leaders like IBM,” said Eric Peeters, vice president, Dow Corning Electronic Solutions. “Optical waveguides made from Dow Corning’s silicone polymer technology offer customers revolutionary new options for transmitting data substantially faster, and with lower heat and energy consumption. We are confident that silicone-based board-level interconnects will quickly supersede conventional electronic signal distribution to deliver the amazing speeds needed for tomorrow’s supercomputers.”

A presentation, entitled Stable and Easily Processable Optical Silicones for Low-Loss Polymer Waveguides, given here by Brandon Swatowski, application engineer for Dow Corning Electronics Solutions, reported that fabrication of full waveguide builds can be completed in less than 45 minutes, and enable a high degree of process flexibility. Silicone polymer material, which is dispensed as a liquid, processes more quickly than competitive waveguide materials such as glass and does not require a controlled atmosphere chamber.

Swatowski’s presentation went on to say that waveguide builds based on the silicone polymer showed excellent adhesion to polyimide substrates. It also discussed how optical characterization of the new polymer waveguides silicones showed losses as low as 0.03 dB/cm, with environmental stability extending past 2,000 hours exposure to high humidity and temperature, and good performance sustained over 500 thermal cycles between -40°C and 120°C.

Spending on research and development by semiconductor companies grew 7% in 2012 to a record-high $53.0 billion, even though the semiconductor market declined 1% to $317.6 billion, according to the 2013 edition of IC Insights’ McClean Report.  The increase lifted R&D spending by chip companies to 16.7% of total semiconductor sales in 2012, the highest level since the peak of 17.5% was reached in both 2008 and 2009.

For more than three decades, R&D spending as a percentage of total semiconductor sales has trended higher due to increasing costs associated with developing complex IC designs and creating next-generation process technologies to manufacture these circuits.  In the late 1970s and early 1980s, R&D spending as a percent of semiconductor sales by chip companies was typically 7-8%.  R&D-to-sales ratios grew to 10-12% of revenues by the early 1990s and then jumped to over 15% during the last decade, reaching a record 17.5% in 2008.

However, as shown in Figure 1, not all companies have seen a growing portion of sales consumed by R&D.  For example, Samsung’s R&D-to-sales ratio fell from a peak of 25% in 2001 to 8% in 2010 and has remained there since.  

Samsung’s semiconductor business is more capital-intensive than it is R&D-intensive because of the commodity nature of the DRAM and flash memory businesses in which it mainly participates.  As a result, since 2001, Samsung’s semiconductor sales have grown an average of 16% per year, while its R&D spending has increased at about one-third the rate (5%) and it’s capital expenditures have grown by an average of 19% annually.  The main focus of Samsung’s investments is in adding new fab capacity for large-diameter wafers (currently 300mm but heading toward 450mm later this decade).

Intel’s business is also capital-intensive.  Its spending on new fabs and equipment in each of the past two years was about $11 billion, which was only about $1 billion shy of what Samsung spent in each of those years.  Intel’s advanced microprocessors and other incredibly complex logic devices have very short life cycles.  Spending large amounts of money on research and development is part of its business model.  Intel’s $10.1 billion in semiconductor R&D spending in 2012 was more than 7x the amount spent by second-place Qualcomm!  In fact, Intel spent more than one-third of the combined $28.7B spent by the top-10 R&D spenders in 2012, according to the 2013 McClean Report.

Figure 1 also shows how much the industry’s largest pure-play foundry, TSMC, has been spending on R&D as a percent of sales over the past decade-and-a-half.  As the process technology needed for each new generation of ICs has become increasingly difficult to develop, fabless companies and the growing number of fab-lite companies have come to rely on TSMC not only for fabricating their wafers, but also for helping to bring their IC designs into existence.  As a result, TSMC’s R&D spending-to-sales ratio has been gradually climbing over the past 6-8 years.  TSMC’s spending ratio reached 8% in 2001, but that had a lot to do with the fact that its sales were hit hard by the industry recession that year.  Aside from a small dip in 2009, TSMC’s spending on R&D has grown every year since 1998 and at an average annual rate of 25%!  Over that same 1998-2012 timeperiod TSMC’s sales grew an average rate of 19% per year.