Category Archives: Packaging

Facing a relentless onslaught from tablets, smartphones and solid state drives (SSD), global hard disk drive (HDD) market revenue in 2013 will decline by about 12 percent this year, according to an IHS iSuppli Storage Space market brief from information and analytics provider IHS (NYSE: IHS).

Revenue is set to drop to an estimated $32.7 billion in 2013, down 11.8 percent from $37.1 billion last year. HDD revenue will be flat the following year, amounting to $32.0 billion in 2014, as shown in the figure.

“The HDD industry will face myriad challenges in 2013,” said Fang Zhang, analyst for storage systems at IHS. “Shipments for desktop PCs will slip this year, while notebook sales are under pressure as consumers continue to favor smartphones and tablets. The declining price of SSDs also will allow them to take away some share from conventional HDDs.”

HDD gross and operating margins likewise will decline as a result of continued price erosion. “However, HDDs will continue to be the dominant form of storage this year, especially as demand for Ultrabooks picks up and hard drives remain essential in business computing,” Zhang added.

HDD vs. SSD

HDDs overall will maintain market dominance because of their cost advantage over SSDs, particularly when higher densities are involved and dollars per gigabyte are calculated. HDD costs and pricing are significantly lower than SSDs, with already falling HDD average selling prices expected to decline further this year by 7 percent.

Moreover, HDDs will continue to be part of storage solutions even in Ultrabooks that make use of an SSD component. The solution, which cobbles hard disk drives together with a so-called cache SSD module, boasts of a superior price-value proposition compared to SSD-only counterparts.

A major growth area for HDDs will be the use of hard disk drives in the business sector spanning the enterprise space, cloud storage, big data and big-data analytics. Bearing the lowest cost of any storage medium now on the market, HDDs will remain the final destination for the majority of digital content that need to be filed away. And toward the last quarter of this year, Western Digital is expected to launch a 5-terabyte Helium HDD, catering mostly to data centers for enterprise servers and storage applications, further propelling the HDD space into overdrive.

Western Digital vs. Seagate

Western Digital is expected to continue battling archrival Seagate Technology for market leadership in both revenue and shipments, especially in the enterprise business segment. While Seagate had a 50 percent share of the enterprise market last year, the introduction by Western Digital of its new helium technology could catapult the manufacturer to the top at the end of 2013, dethroning Seagate in the process.

Optical drives vs. extinction

In the parallel market for PC optical disk drives—home to discs like CDs and DVDs—losses in both revenue and shipments are similarly expected. The declines stem from a number of reasons, including smaller chassis sizes for PCs, a shift in preference among consumers toward video streaming instead of using physical discs, and cost cutting from PC manufacturers that have lost interest in using optical drives.

In what appears to be a grim scenario, the optical disk drive industry is expected to encounter continued challenges this year, such as those presented by thinner PC designs. Optical drives could eventually be abandoned by PC makers altogether.

Five University of California, Riverside professors will receive a total of $5 million as part of a $35 million research center aimed at developing materials and structures that could enable more energy efficient computers, mobile phones, and other electronic devices.

The research center, which will be called the Center for Function Accelerated nanoMaterial Engineering (FAME), will be located at UCLA and led by Jane P. Chang, a professor of chemical and biomolecular engineering at UCLA.

Four professors from UC Riverside’s Bourns College of Engineering are part of the center: Alexander A. Balandin, Alexander Khitun, Jianlin Liu and Roger Lake, all of whom are part of the electrical engineering department and materials science and engineering program. Jeanie Lau, a professor of physics and astronomy who is also part of the materials science and engineering program, is the fifth professor. Each professor will receive about $1 million.

FAME is one of six new university microelectronics research centers recently established with $194 million over the next five years from the Semiconductor Research Corporation (SRC) and the Defense Advanced Research Projects Agency (DARPA). The funding supports the continued growth and leadership of the U.S. semiconductor industry.

The other five centers will be located at UC Berkeley, University of Michigan, University of Notre Dame, University of Illinois at Urbana-Champaign and University of Minnesota.

The University of Minnesota center is called the Center for Spintronic Materials, Interfaces and Novel Architectures (C-SPIN). Three UC Riverside researchers – Roland Kawakami, Ludwig Bartels and Cengiz Ozkan – received a total of $3 million as part of that center.

The goal of the FAME center is to create and investigate new nonconventional atomic scale engineered materials and structures of multi-function oxides, metals and semiconductors to accelerate innovations in analog, logic and memory devices for the semiconductor and defense industries.

The center includes 35 faculty researchers from 16 universities: UCLA, Columbia, Cornell, UC Berkeley, MIT, UC Santa Barbara, Stanford, UC Irvine, Purdue, Rice, UC Riverside, North Carolina State, Caltech, Penn, West Virginia and Yale.

Balandin, Lau and Liu will focus on van der Waals materials – a broad range of crystalline solids with layer structures. The van der Waals materials include graphene, topological insulators and charge-density wave materials. It is expected that this class of materials can be used in future information processing.

Design, assembly, inspection and repair personnel have a new tool to help improve reliability of ball grid arrays (BGAs) and fine-pitch ball grid arrays (FBGAs) in high density applications, thanks to the newly released C revision of IPC-7095, Design and Assembly Process Implementation for BGAs.

Published by IPC — Association Connecting Electronics Industries and developed with input from representatives from OEMs, fabricators, EMS companies and others in the electronics manufacturing industry, IPC-7095C addresses design and process considerations of particular importance to portable handheld products in which BGAs are a dominant interconnection technology.

 “Handheld products continue to shrink. At the same time, alloys, ball shape and attachment procedures are evolving,” says Ray Prasad of Prasad Consultancy Group, who helped spearhead development of the document. “That combination presents some unique challenges to product reliability that the new revision of IPC-7095 seeks to solve.”

A notable addition to the revised document is its inclusion of expanded information on mechanical failure issues such as PCB pad cratering or laminate defects that occur after assembly. In addition to providing guidelines for BGA inspection and repair, IPC-7095C addresses reliability issues and the use of lead-free joint criteria associated with BGAs. It also features numerous photographs of X-ray and endoscope illustrations to identify various defect conditions such as head on pillow, an incomplete and unreliable condition that can occur during BGA assembly processes.

Assumed failure mechanism for "head-on-pillow," also known as "head-in-pillow." Source: Renesas

IPC-7095C, Design and Assembly Process Implementation for BGAs, is 165 pages long. IPC members may purchase a hard copy of the document for $55; the industry price is $110. Single-user, site and global licenses are also available. For more information or to purchase a copy of IPC-7095C, visit www.ipc.org/7095.

STATS ChipPAC Ltd. (SGX-ST: STATSChP) and United Microelectronics Corp. (NYSE: UMC; TWSE: 2303) announced the world’s first demonstration of TSV-enabled 3D IC chip stacking technology developed under an open ecosystem collaboration. The 3D chip stack, consisting of a wide I/O memory test chip stacked upon a TSV-embedded 28nm processor test chip, successfully reached a major milestone on package-level reliability assessment.

"The next level of chip integration is rapidly evolving, and 3D IC technology is poised to enable the next frontier of IC capabilities for customers under various deployment models," said Shim Il Kwon, VP of Technology Innovation of STATS ChipPAC.

S.C. Chien, vice president of Advanced Technology Development at UMC, said, "We see no imperative to restrict 3D IC to a captive business model, as UMC’s development work with nearly all the major OSAT partners for 3D IC has been very productive. Our successful collaboration with a leading OSAT partner like STATS ChipPAC has further established the viability of an open ecosystem approach. This model should work especially well for our mutual 3D IC customers, as foundry and OSAT can utilize their respective core strengths during development and delivery, while customers can benefit from keeping supply chain management flexible and realize better transparency over technology access compared to closed, captive 3D IC business models."

Under the 3D IC open development project with STATS ChipPAC, UMC provides the FEOL wafer manufacturing, with a foundry grade fine pitch, high density TSV process that can be seamlessly integrated with UMC’s 28nm poly SiON process flow. The know-how developed will be applied towards implementation on the foundry’s 28nm High-K/metal gate process. For MEOL and BEOL, STATS ChipPAC performs the wafer thinning, wafer backside integration, fine pitch copper pillar bump and precision chip-to-chip 3D stacking.

Renesas Electronics Corp. (TSE: 6723, Renesas) and J-Devices Corp. signed a memorandum of understanding regarding the transfer of the semiconductor back-end production business of three facilities operated by Renesas’ wholly owned manufacturing subsidiaries (the Hakodate Factory of Renesas Northern Japan Semiconductor, Inc. (Renesas Northern Japan), the Fukui Factory of Renesas Kansai Semiconductor Co., Ltd. (SKS), and the Kumamoto Factory of Renesas Kyushu Semiconductor Corp. (Renesas Kyushu)) and Renesas Northern Japan’s wholly owned subsidiary, Hokkai Electronics Co., Ltd. (Hokkai Electronics) to J-Devices.

This proposed transaction “aims at building a long-term, mutually beneficial relationship between the two companies as strategic partners in the semiconductor production business.” According to a press release.  The two companies plan to negotiate a final agreement and to complete the transfer in early June 2013.

The current employees of the transferred facilities will be “on loan” to J-Devices for a set period, under the premise that they will be reassigned to J-Devices on the basis of individual agreements in future. The Renesas products which will be manufactured at the facilities to be transferred will continue to be supplied by Renesas to customers with the quality, delivery schedules, service equal to or better than before even after the transfer.

In addition to the current seven facilities of J-Devices (Usuki, Oita Prefecture (Headquarters); Kitsuki, Oita Prefecture (Headquarters functions); Shibata-gun, Miyagi Prefecture; Aizuwakamatsu, Fukushima Prefecture; Miyawaka, Fukuoka Prefecture; Oita, Oita Prefecture; and Satsumasendai, Kagoshima Prefecture), the present transfer will add an additional three production facilities. This will make J-Devices one of the world’s top five OSAT (Outsourced Semiconductor Assembly and Test) service providers.

At the same time, the advantages gained as a long-term strategic partner of Renesas, including larger business scale, fusion of technical capabilities, and expanded product lineup, will enable J-Devices to improve cost competitiveness, technical capabilities, and product quality, allowing it to contribute to the continued development of the semiconductor industry as a world-top-level OSAT service provider and also providing substantial benefits for customers.

Renesas Electronics Corp. lays claim as world’s number one supplier of microcontrollers, and also offers SoC solutions and a range of analog and power devices. Business operations began as Renesas Electronics in April 2010 through the integration of NEC Electronics Corp. and Renesas Technology Corp., with operations spanning research, development, design and manufacturing for a wide range of applications. Headquartered in Japan, Renesas Electronics has subsidiaries in 20 countries worldwide. More information can be found at .

J-Devices is one of the largest independent semiconductor assembly and test company in Japan with seven factories in Japan. The original company (named Nakaya Microdevices) was established in 1970 and offers a broad lineup of packages including thermally enhanced BGA, CMOS sensor, leadframe and other original packages. J-Devices offers skilled package development as well as the full turnkey "one stop" service such as wafer sort, assembly, and final testing for consumer and automotive product.

China’s rapid transition from a low-cost manufacturing hub to an innovation hotspot with growing foreign ambitions represents both a threat and an opportunity for companies and investors around the globe, according to Lux Research.

Chinese firms in such sectors as energy storage, advanced lighting, emerging electronics and red-biotechnology industries are more likely to pursue both overseas growth and introduction of foreign capabilities into China.

During 2009-2011, Chinese companies’ foreign merger and acquisition (M&A) deals grew 75% to $28.1 billion. Simultaneously, M&A deals by foreign companies in China increased 16 times – from $400 million to $6.9 billion, suggesting new momentum in opportunities inside the world’s fastest growing country. All indications are that this is only the beginning.

“From Chinese companies’ perspectives, acquiring advanced technologies globally and entering foreign markets are major goals as they seek to shed the tag of a low-cost manufacturing hub,” said Zhuo Zhang, Lux Research Associate and the lead author of the report titled, “From the Horse’s Mouth: How Chinese Companies Value Foreign Partners and Opportunities.”

“Entities around the globe need to navigate the new reality of an increasingly crowded market in China where global leaders must learn to operate while developing strategies to face the imminent threat in their own backyard,” he added.

Lux Research analysts studied China’s complex emerging technology ecosystem, surveying and analyzing 380 entities. Among their findings:

  •  Sectors to watch. Energy storage, advanced lighting, emerging electronics and red-biotechnology all sat in the upper-right quadrant of the grid on Lux’s China Innovation Partnership Grid. This indicates that companies in these sectors have both strong foreign growth inclination and strong willingness to introduce appropriate foreign partners into China. In comparison, water treatment and construction material industries are closed to foreign growth and introduction.
  • IP drives openness. Chinese companies with a strong IP portfolio are more open to foreign partnerships. Contrary to conventional wisdom regarding China, it is the companies that value IP, rather than just those looking to infringe upon the IP of others, who are most open. Specifically, 51% of companies with strong IP are open to partnering with foreign entities in China, compared to only 31% of those with weak IP.
  • Government relationships enable growth introverts. Companies with poor government relationships are driven to look overseas, with 54% of these companies having meaningful foreign growth activities compared with only 44% percent of the companies with good government relationships. In many of China’s emerging technology industries, government relationships represent domestic sales channels, reducing the urgency for foreign growth.

The report, titled “From the Horse’s Mouth: How Chinese Companies Value Foreign Partners and Opportunities,” is part of the Lux Research China Innovation Intelligence service.

Zvi Or-Bach, President & CEO of MonolithIC 3D Inc., San Jose, CA, blogs about the evolution of 3D technology seen at the International Electron Devices Meeting. 

From our biased point of view we see the recent IEDM12 as a pivotal point for monolithic 3D. Here’s why:

We start with the EE Times article IEDM goes deep on 3-D circuits, starting with "Continuing on the theme of 3-D circuit technology addressed in an earlier post about this year’s International Electron Device Meeting, Rambus, Stanford University and an interesting company called Monolithic 3D will address issues related to cooling 3-D circuits. .." and follow with a quote from the abstract to IEDMs short course "Emerging Technologies for post 14nm CMOS" organized by Wilfried Haensch, of IBM’s Watson Research Center: "Scaling the dimension was the key for the unprecedented success of the development of IC circuits for the last several decades. It now becomes apparent that scaling will become increasingly difficult due to fundamental physical limits that we are approaching with respect to power and performance trade-offs. This short course will give an overview of several aspects in this “end-of-scaling” scenario. …"

We then continue with statements made by Dr. Howard Ko, a Senior Vice President and General Manager of the Silicon Engineering Group of Synopsys in his 2013: Next-generation 3-D NAND flash technology article: "Yet there are a variety of developments in another type of 3-D scaling that are likely to have a similarly large impact on semiconductors in the near future – 3-D devices for NAND flash…. And as in planar CMOS logic, NAND flash technology has been progressively scaled to smaller feature sizes, becoming the process leader in driving the smallest line-widths in manufacturing as evidenced by the current 1x-nm (~19-nm) process node. Yet, despite plans to scale down to the 1y-nm (~15-nm) and possibly 1z-nm (~13-nm) nodes, the traditional planar floating gate NAND flash architecture is approaching the scaling limit, prompting the search for new device architectures.  Not to be upstaged by the planar to 3-D (FinFET) transition in logic devices, NAND flash has embarked on its own 3-D scaling program, whereby the stacking of bit cells allows continuous cost-per-bit scaling while relaxing the lateral feature size scaling."

In our recent blog 3D NAND Opens the Door for Monolithic 3D we discussed in detail the adoption of monolithic 3D for the next generations of NAND Flash. The trend was very popular subject of this year’s IEDM and is nicely illustrated by this older chart:

And accordingly the updated ITRS 2012 present the change from dimension scaling to monolithic 3D scaling as presented in the following slide.

This year’s IEDM brought up two of the driving forces behind the shift from dimensional scaling to monolithic 3D IC scaling, that we will detail below as #1 and #2.

The current 2D-IC is facing escalating challenges:

On-chip interconnect (#1): Dominates device power consumption, Dominates device performance, Penalizes device size and cost

Lithography (#2): Dominates Fab cost, Dominates device cost and diminishes scaling benefits, Dominates device yield, and Dominates IC development costs.

The problem with on-chip interconnect didn’t start today. This vintage Synopsys slide below clearly indicates that on-chip interconnect started to dominate overall device performance a decade ago:

In response, the industry has spent an enormous amount of money to convert from aluminum to copper and to low-K inter-metal dielectrics. But now, we have very few additional options left (perhaps air-bridge?) as illustrated by the following chart:

It shows that neither Carbon Nano Tube (CNT) nor Optical interconnect are better than copper, and that monolithic 3D still is the best path.

The practiced ‘band-aid’ fix so far has been throwing more transistors (they are getting cheaper, right? No longer. See father below) at the problem in the form of buffer and repeaters. But as we scale down we need exponentially more of these ban-aids as illustrated by the following:

Copper, however, is now reaching its inflection point as was articulated in a special session organized by Applied Materials attached to this IEDM, the 14 nanometer node is expected to be an inflection point. Quoting from the abstract:

"The 14 nanometer node is expected to be an inflection point for the chip industry, beyond which the resistivity of copper interconnects will increase exponentially and may become a limiting factor in chip design. On December 11, 2012, Applied Materials, Inc. will host an important forum in San Francisco to explore the path that interconnect technology must take to keep pace with transistor scaling and the transition to new 3D architectures.” (emphasis added)

This had been illustrated before in the following chart:

And to make it crystal clear, IBM presented the following chart in its short course:

 
Power is now dominating IC design and clearly dimensional scaling does not improve the interconnect’s impact – see the following chart built from the ITRS Roadmap. The only effective path forward that addresses interconnect is monolithic 3D.

As for the second challenge – lithography – we start again with an old chart by Synopsys:

The implication is that any new node of dimensional scaling comes with escalating lithography costs; and sure enough, that’s what is happening. When litho costs are plotted over time, it fits a log-linear scale….this is not a sustainable trend.
The following chart illustrate the lithography escalating cost of equipment which directly reflect the wafer cost.

This resulted in the following slide by IBM at the GSA Silicon Summit 2012:

Quoting from the slide: "Net: neither per wafer nor per gate [are] showing historical cost reduction trends." Another EE Times IEDM12 article covering a keynote given by Luc van den Hove, chief executive of IMEC,  IEDM: Moore’s Law seen hitting big bump at 14 nm, repeats the same conclusion.

In fact, some vendors are already changing course accordingly. GlobalFoundries, in its recent 14nm announcement, disclosed that the back-end will be unchanged from 20nm. This suggests a similar die size and respective increase in per-transistor cost. Further, ST Micro in the Fully Depleted Transistors Technology Symposium (11 December, 2012) during IEDM12 week also acknowledged that their 14nm node will have a 20nm node metal pitch, and, just like GlobalFoundries, a similar die size and increase in per-transistor cost.
So it would seem that also for lithographic reasons, the industry’s next generation path, and the continuation of Moore’s Law, would be achieved by leveraging the third dimension.

Now that monolithic 3D is feasible and practical, the time has come to move in this new direction, as has been nicely illustrated by this concluding chart below:

January 22, 2013 – Reports are circling around Apple’s supply chain of a potential shift in the company’s display strategy for its future iPhones and iPads — moving back to LCDs and away from touch panels — but a drastic realignment of its supply chain is probably not likely, observes DisplaySearch.

Calvin Hsieh, senior analyst at DisplaySearch, cites a report from China that Innolux has delivered "touch on display" samples for the iPhone, another China report that Innolux and AU Optronics have provided "one-glass solution" (OGS) samples for the iPad Mini, and his firm’s own analysis that the iPhone 5 uses in-cell touch technology but the iPad mini uses a glass/film dual ITO (GF2, or DITO) structure. With both those processes struggling to attain good yields, could Apple end up changing its display technology adoption midstream?

TOD is a proprietary on-cell touch technology developed by Innolux in which the sensor is located on the upper glass (the color filter substrate) beneath the top polarizer. On-cell touch combines both LCD and touch so it must meet Apple’s LCD display requirements; Hsieh notes, adding that Innolux accounted for less than 10% of iPhone 4 display shipments (3.5-in, 960×640). "If Apple were to adopt TOD, it would very likely request that Innolux share its technology, structure or even patents with Apple’s other LCD suppliers in order to ensure adequate supply," he writes," and Apple also probably would want to take over the controller IC and algorithm from any Innolux partners (e.g. Synaptics). Apple already owns DITO patents, he adds.

The OGS display technology is an even more complex problem, Hsieh points out. OGS integrates the touch ITO sensor circuits into the cover glass, via two possible methods: a piece type such as "touch on lens" (TOL) or a sheet type, each accomplished with a different process. Either way the X-Y sensor patterns are on the same side of the substrate, so it’s called a "SITO" structure or "G2." Touch panel maker TPK owns patents for the piece-type OGS method, and claim they have key SITO patents as well and are suing Nokia and Chinese panel maker O-film, Hsieh notes; whether the aforementioned Innolux-AUO partnership could produce the technology given the TPK patents is unclear, he says.

There’s more to Apple use of OGS display if it chooses that route. Sheet-type OGS has a compressive cover-glass strength of 500-6600 Mpa; Corning’s IOX-FS and Gorilla glass have 600-700 Mpa for smartphone sizes and cannot be used in sheet type, Hsieh says. Piece type has the higher CS value but are difficult to mask-stamp and align under lithography, and throughput may be low.

Among iPhone 5 panel suppliers only LG Display offers everything from in-cell touch LCD to cover glass lamination (consigned by Apple), Hsieh notes. Other in-cell touch LCD makers Japan Display and Sharp rely on partners for the cover glass. If Innolux and AUO continue with their OGS partnership, they have a choice:

  • An integrated offering of LCD, OGS sheet patterning (cover glass with SITO sensor), and lamination let Apple specify the IOX-FS glass sheet with compressive strength of Gorilla 1; "In this scenario, LG Display will never give up and must be one of the suppliers," he notes.

  • Integrate the LCD, OGS piece-type sensor patterning, and lamination, using consigned cover glass pieces from other finishers (e.g. Lens One). The challenge here is expanding tools, throughput, and yield for piece-type patterning, to be acceptable for the iPhone’s >100M unit base.

All that is somewhat speculation, though, because long-term Apple touch supplier TPK already "has excellent OGS sheet and piece-type technology, and high lamination yield rates," and is unlikely to simply hand over that business to new entrants. "Although AUO and Innolux have advantages as LCD makers and can shorten the supply chain by producing LCD and touch at the same time, TPK has strength in OGS integration from sensor patterning, cover glass finishing (for sheet type), to module lamination," Hsieh writes. "Thus, there is a good chance that TPK will once again be a key touch supplier to Apple if it decides to change touch structures."

January 17, 2013 – Printed, flexible, and organic electronics have garnered more than $7.5 billion in venture funding from 1996-2011, but funding has declined sharply from a peak in 2007, according to a report from Lux Research. Funding topped $990M in 2007, but lost a third of that value within four years to $626M in 2011.

"A number of high-profile failures like Konarka have soured many investors’ impressions of this space — cutting away some unwarranted hype, but potentially raising the hurdles for companies with more promising technologies to secure funds," stated Anthony Vicari, Lux Research associate and lead author of a new report examining investments and opportunities in printed, flexible, and organic electronics. He points to "glaring funding imbalances, with overfunding in areas such as organic photovoltaics, but promising technologies such as electrowetting and electrochromic displays haven’t received investment that matches their potential."

Lux will present a Webinar on Feb. 5 to discuss the report’s findings, but here’s some insights in a nutshell:

– Display technologies have huge potential. Electrowetting, electrochromic, and metal oxide thin-film transistors (MOTFTs) are potential gold mines, offering high technical performance and value relative to competing reflective displays and TFTs.

– Asian startups are underfunded. North America leads overall investment at $5.1B, or 67% of the world total. However, Asian start-ups, like OLED developers in South Korea, account for just $506M of investing. That indicates not a lack of innovation, but the need for an alternate funding model, Lux says.

– Dow, Samsung, and Intel are trendsetters. These three giants lead corporate venture capital (CVC) investors, with high levels of activity in this space. Their best bets have targeted the more promising, higher-potential technologies such as OLEDs and RFID.

January 15, 2013 – The semiconductor industry is undergoing massive transformation as the rise in mobile computing, changes to the fabless-foundry model, uncertainties in technical innovation, and global macroeconomic trends become the dominant forces in 2013 and beyond, according to industry leaders speaking at the SEMI Industry Strategy Symposium (ISS), opening this week in Half Moon Bay, CA.

Ajit Manocha, CEO of GlobalFoundries, during his keynote presentation discussed the dynamic technology and economic needs of mobile computing that is driving new approaches to the chip design-to-production cycle. Calling it "Foundry 2.0," he sees outsourced semiconductor manufacturing moving toward a more IDM-like model, creating new collaboration models and techniques to close the gap between process teams at foundries and design teams at the fabless companies. With daunting technical challenges like 3D stacking, 450mm fabs, new transistor architectures, multi-patterning, and the uncertainties to lithography-based scaling, product development paths with virtual teams will evolve and adapt rapidly in the coming months and years.

With new fabs now costing upwards of $8 billion and leading-edge manufacturing investments expected to exceed $40 billion this year alone, global economic trends and forces — increasingly influenced by uncertain consumer spending in both developed and emerging markets — have never been more important to the semiconductor ecosystem. Dr. John Williams, president and CEO of the Federal Reserve Bank of San Francisco, said "Many businesses are locked into a paralyzing state of anxiety."

Williams used the ISS conference to lessen uncertainty and anxiety in the capital markets, pledging to keep interest rates near zero until the unemployment rate drops to 6.5%, as long as inflation expectations do not climb above 2.5%.

Bruce Kasman, chief economist and managing director of global research at JP Morgan, shared a positive economic outlook, especially in the second half of the year, that is "bumpy, better and less risky." He sees Asia leading the economic rebound, as China demand accelerates with the change in leadership and improved access to credit. University of Texas Austin Churchill scholar, Matthew Gertken, however, discussed the simmering "Asian cold war" developing as territorial disputes with China generate an emerging "containment policy" by many of China’s neighbors.

How these macroeconomic dynamics are impacting the semiconductor industry was discussed by speakers who saw both perils and opportunities. Andy Oberst, senior VP, strategy and corporate development at Qualcomm, looked at what mobile phones would likely look like in 2020, but also pointed out how disruptive changes — not incremental changes — have always driven the mobile phone market.

Satya Kumar, vice president at Credit Suisse, discussed how original equipment makers like phone and computer manufacturers have always benefitted from the declining cost of transistors and pondered, "Could stopping Moore’s Law be a good thing?"

As the world’s largest semiconductor company, Intel’s view is different. Michael Bell, vice president and general manager, mobile and communications group at Intel, brought the audience up to date on the company’s mobile strategy, offering confidence that Intel’s portfolio of RF baseband technologies, leading-edge scaling performance, and supply chain excellence will ultimately deliver significant success.

Conference speakers on Day 2 and Day 3 of ISS will discuss how these and other mega-trends are specifically impact the R&D, product development, manufacturing, investment, and supply-chain challenges impacting various sectors of IC and microelectronics industry.

The SEMI Industry Strategy Symposium (ISS) examines global economic, technology, market, business and geo-political developments influencing the semiconductor processing industry along with their implications for your strategic business decisions. For more than 35 years, ISS has been the bellwether semiconductor conference for senior executives to acquire the latest trend data, technology highlights and industry perspective to support business decisions, customer strategies and the pursuit of greater profitability.