Category Archives: Packaging

Micron Technology, Inc. and Elpida Memory, Inc. trustees announced today the closing of Micron’s acquisition of 100 percent of Elpida’s equity, pursuant to a Sponsor Agreement entered into on July 2, 2012 in connection with Elpida’s corporate reorganization. In a related transaction, Micron also announced today the completion of its acquisition of a 24 percent share of Rexchip Electronics Corporation from Powerchip Technology Corporation and certain of its affiliates. These transactions went into effect today.

Elpida’s assets include a 300mm DRAM fabrication facility located in Hiroshima, Japan; an approximate 65 percent ownership interest in Rexchip, whose assets include a 300mm DRAM fabrication facility located in Taiwan; and a 100 percent ownership interest in Akita Elpida Memory, Inc., whose assets include an assembly and test facility located in Akita, Japan. Together with the Rexchip shares acquired from Powerchip, Micron will control approximately 89 percent of Rexchip’s outstanding shares and 100 percent of Rexchip product supply. The manufacturing assets of Elpida and Rexchip together can produce more than 185,000 300mm wafers per month, which represents an approximate 45 percent increase in Micron’s current manufacturing capacity.

Using its advanced technologies, Elpida has built a strong presence in mobile DRAM, targeting mobile phones and tablets. Micron is a leader in delivering enterprise DRAM solutions for networking and servers as well as offering a wide product portfolio in NAND flash memory and NOR. Combining the two complementary product portfolios will further strengthen Micron’s position in the memory market and enable it to provide customers with an even more complete set of high-quality solutions.

“We are pleased to bring together Elpida with Micron to form the industry’s leading pure-play memory company. This combination will result in enhanced R&D and manufacturing scale, significant cost and production synergies and a stronger memory product portfolio to provide solutions to our customers,” said Micron CEO Mark Durcan.

Yukio Sakamoto, CEO, president and co-trustee of Elpida, said, “This transaction is a strong testament to the value of Elpida’s technologies, products and people, and it will result in a combined organization that can best serve customers with broader memory solutions, strength and scale.”

Effective with the closing, Mr. Sakamoto announced his resignation from Elpida. Micron and Elpida announced that Yoshitaka Kinoshita will replace Mr. Sakamoto as the president, representative director and business trustee of Elpida and become the president of Micron Japan.

“I want to personally thank Sakamoto-san for his strong leadership of Elpida and for his efforts in helping bring Elpida and Micron together. I look forward to working with Kinoshita-san as we seek to strengthen our combined teams,” said Durcan.

 

Zvi Or-Bach, President & CEO of MonolithIC 3D Inc. blogs about the appearance of 3D integration on several roadmaps.

At the recent CEA Leti day, that took place as part of Semicon West2013, Laurent Malier, Leti CEO, presented his “A look at the coming Decade.” Slide 15 of the presentation provides Leti’s vision for CMOS roadmap:

Monolithic 3D is presented on Leti’s roadmap as the technology to follow the 7nm process node.

Early this year we blogged IEDM 2012: The pivotal point for monolithic 3D ICs. It is now quite reassuring to see monolithic 3D now as part of the industry roadmap. We discussed then that memory vendors are already gearing up for volume production of the 3D NAND. And, indeed, just this summer, Toshiba has been reported to leverage the monolithic 3D cost reduction advantage (Toshiba to Build Fab for 3D NAND Flash). It only makes senses for the CMOS market to follow.

Doubters would ask why the industry would introduce a new dimension to the roadmap that has been extremely successful for over 40 years. The answer is very simple – because it is not so successful anymore. We are all aware that the escalating costs of lithography had diminished transistors cost reduction, as is illustrated in the following ASML chart:

Even if we ignore the cost issues we should remember IBM’s Bernie Meyerson caution that “atoms don’t scale.” We are quickly approaching these limit as is visible on the following Intel chart:

Accordingly, Mike Mayberry, director of component research at Intel, said at the recent IMEC Technology Forum that he“has looked down the highway of conventional silicon development and reckons things become foggy beyond about the 7-nm node.” In fact, in his March 2013 presentation “Pushing Past the frontiers of Technology” Mike Mayberry also presents monolithic 3D on his road map:

This transition was well captured in the title of 2011 IEDM keynote address by Mark Bohr, the Senior Fellow of Technology and Manufacturing Group and a Director of Process Architecture and Integration of Intel, “The Evolution of Scaling from the Homogenous Era to the Heterogeneous Era.”

Cascade Microtech, Inc. and imec today announced breakthroughs in probing stacked integrated circuits (3D-SICs), fueling an important growth engine for the semiconductor market. Through a Joint Development Agreement, Cascade Microtech partnered with imec to successfully probe 25µm-diameter micro-bumps on a wide I/O test wafer with its fully-automated CM300 probe solution utilizing an advanced version of Pyramid Probe technology. This achievement comes as part of imec’s 3D integration research program which includes other industry partners from the entire semiconductor value chain.

The 3D semiconductor market (including 3D-SIC, 2.5D interposer, and 3D WLCSP) is expected to represent nine percent of the total semiconductor value by 2017, according to Yole Développement. Logic 3D SoC/SiP (including interposer chips, APE, CPU, FPGA, wide I/O memory, etc.) will be the biggest industry using 3D platforms in the next few years. 3D applications will emerge in high-performance computing, and electronic markets such as nanotechnology and medical applications, which will benefit from the high-density integration that 3D technology offers.

The semiconductor industry is exploring new methods to increase the functionality of ICs at a smaller footprint, extending Moore’s Law. 3D-SICs offer a solution to the speed, power and density requirements demanded by future mobile electronics platforms. Through-silicon vias (TSV) used in 3D-SICs shorten interconnects between logic elements, thus reducing power while increasing performance. Within imec’s 3D integration research program, industry leaders are jointly developing design, manufacturing, and test solutions to bring this new technology to high-volume manufacturing.

Cascade Microtech’s CM300 flexible on-wafer measurement system was designed to deliver superior positioning accuracy and repeatable contact, offering a level of precision that supports both shrinking pad sizes and pitch roadmaps. The CM300 captures the true electrical performance of devices with high-performance capabilities that include low leakage and low noise. As a comprehensive probing solution employing the latest advances in Pyramid Probe technology, the CM300 has proven to meet the fine-pitch (40 µm area array), low-force (< 1gf/tip) advanced probing requirements of 3D-SICs.

“We are excited that our work with Cascade Microtech has resulted in such a breakthrough. I believe together we’ve achieved a first in the industry,” said Erik Jan Marinissen, Principal Scientist at imec in Leuven, Belgium. “We are able to hit 25 µm-diameter micro-bumps with a high level of accuracy due to the probe-to-pad alignment features of Cascade Microtech’s CM300. And advances in their Pyramid Probe technology have enabled us to probe micro-bumped wafers with 40/50 µm pitch according to the JEDEC Wide-I/O Mobile DRAM standard.”

“Cascade Microtech’s CM300 probe solution is designed to provide greater alignment accuracy to probe directly on small, fragile micro-bumps. In conjunction with a fine-pitch, low-force Pyramid Probe card, we have achieved consistent, accurate measurements on a wide I/O test wafer using a single-channel, wide I/O probe core with an array of 6 x 50 tips at 40/50 µm pitch, with the ability to shrink down to 20 µm pitches in the future,” said Steve Harris, Executive Vice President, Engineering, Cascade Microtech. “Together, imec and Cascade Microtech are enabling the ongoing future of CMOS technologies through this ground-breaking work. 3D integration will undoubtedly result in increased performance and yield while reducing overall costs.”

 

Toshiba Corporation and Amkor Technology, Inc. today announced that the companies have completed Amkor’s acquisition of Toshiba Electronics Malaysia Sdn. Bhd., Toshiba’s semiconductor packaging operation in Malaysia. The transaction also includes Toshiba’s license to Amkor of related intellectual property rights and a manufacturing services agreement between Toshiba and Amkor.

Under the manufacturing services agreement, Toshiba has agreed to purchase and TEM has agreed to supply packaging and test services for certain discrete semiconductor products and analog LSI products.

Established in 1973, TEM has steadily expanded the scale of its packaging operations, primarily of discrete and analog semiconductors. In recent years, its main product has been power semiconductors.

Toshiba positions power semiconductors as a driver of growth for its semiconductor business and seeks to maximize cost competitiveness across its front- and back-end operations. Transferring ownership of TEM to the Amkor group will allow TEM to take full advantage of Amkor’s large scale production and materials procurement capabilities and boost the overall efficiency of its power semiconductor operations.

Toshiba will continue to subcontract power semiconductor packaging and test to Amkor as an important source of key products. As it does so, Toshiba will shift its focus and resources to front-end wafer fabrication for power semiconductors by reinforcing production capabilities at Kaga Toshiba Electronics Corporation, Toshiba Group’s discrete semiconductor production facility in Ishikawa Prefecture, Japan.

Amkor expects the transaction to further strengthen its relationship with Toshiba and to grow its semiconductor packaging and testing business. Amkor plans to leverage the technology and scale of this new factory to attract leading power discrete customers to Amkor.

This Blog was prepared by Israel Beinglass, CTO of MonolithIC 3D Inc.

Like every Semicon West show in the past, where many experts are brought together for showing the latest and greatest semiconductor manufacturing equipment and bringing numerous seminar/panel discussions, this Semicon West of 2013 was no different. Two major issues were discussed, which on the face of it look unrelated, that caught my attention:

Progress in 3D –TSV technology, and EUV.

Obviously these two issues are very different, but they are quite similar in respect to the following:

1. As the advanced node progresses to smaller and smaller feature size we are getting closer to the “end of the roadmap” or the “end of Moore’s law”.

Going to EUV does alleviate some of the problems related to the current solution of double patterning (or quadruple in the future assuming, EUV doesn’t come to fruition soon enough).

As well, utilizing 3D devices with TSV has, in the grand scheme, a similar outcome; namely, advancing the integration via 3D structures rather than continued scaling. Though in the future, 3D devices and advanced nodes could go hand in hand.

2. The big miss of the roadmap. When one looks at some old roadmaps from a few years ago, one can ask how did we, the industry, miss by so much?

This actually reminds me of another miss from a few years ago-the low k inter-metal dielectric. Fig. 1 shows the low k dielectric roadmap trend of various ITRS published roadmaps and the prediction in 1999 that by 2004 we would be using k<2 !! Obviously we know what happened and even today 14 years later it is hard to breakthrough a k value of 2.5.

Figure 1: low k Dielectric roadmap

Figures 2 and 3 show the roadmap for EUV and TSV, respectively. Both are of 2009 vintage. In each case the prediction of the roadmap vs. actual is startling.

Figure 2: EUV roadmap

Figure 3: TSV roadmap

It is not the purpose of this blog to go over the reasons why the roadmaps of EUV and TSV missed the time table by miles, nor to blame anybody for it. There are many articles and discussions published on the subjects. Rather, I will touch on some of the highlights as well as try to make some conclusions regarding the pathway of the industry regarding these two important technologies.

EUV The EUV technology has so far gone through monumental achievements vis-à-vis the incredible tasks of developing the next generation stepper technology. The amount of engineering and resources poured into it is unprecedented in the short history of the semiconductor industry and maybe so for other industries.

It looks like as I write this blog that the only barrier for the technology from becoming a HVM tool is EUV source power that can provide a high enough throughput. Many experts doubt that it could ever be achieved; however, there are many other experts saying that it is within a reach.

TSV In this case I could see two totally unrelated issues:1) technology driven obstacles, and 2) logistics and supply chain issues.

In the case of the TSV it is one of the few cases where the “power point” presentation(s) of the TSV idea are so convincing that it is actually hard to oppose it. However, when it comes to the fine details of the technology development, there are many issues that still need to be addressed and resolved. I believe that it is just a matter of time before the technical obstacles will be resolved and a unified standardized solution emerges. However, on the other hand, I see a real problem from the point of view of logistics, cost and supply chain of the technology, and I have some doubts if it can ever be resolved. For further discussion on this issue, please refer to: 3D IC Supply Chain: Still Under Construction, and to a detailed comment in EE Time published blog and comments re. Semicon West 3D –IC TSV, provided here below.

In summary, I believe that the industry will come with a solution for EUV before TSV becomes a production technology.

Yet there is another alternative to TSV and to EUV – it is the Monolithic 3D methods. Moreover, it is very likely that monolithic 3D will reach volume production before EUV and TSV, as we already see the  NAND Flash vendors ramping up for production of 3D NAND.

Semiconductor revenue worldwide will see improved growth this year of 6.9 percent and reaching $320 billion according to the mid-year 2013 update of the Semiconductor Applications Forecaster (SAF) from International Data Corporation (IDC). The SAF also forecasts that semiconductor revenues will grow 2.9 percent year over year in 2014 to $329 billion and log a compound annual growth rate (CAGR) of 4.2 percent from 2012-2017, reaching $366 billion in 2017.

Continued global macroeconomic uncertainty from a slowdown in China, Eurozone debt crisis and recession, Japan recession, and the U.S. sequester’s impact on corporate IT spending are factors that could affect global semiconductor demand this year. Mobile phones and tablets will drive a significant portion of the growth in the semiconductor market this year. The industry continued to see weakness in PC demand, but strong memory growth and higher average selling prices (ASPs) in DRAM and NAND will have a positive impact on the semiconductor market. For the first half of 2013, IDC believes semiconductor inventories decreased and have come into balance with demand, with growth to resume in the second half of the year.

"Semiconductors for smartphones will see healthy revenue growth as demand for increased speeds and additional features continue to drive high-end smartphone demand in developed countries and low-cost smartphones in developing countries. Lower cost smartphones in developing countries will make up an increasing portion of the mix and moderate future mobile wireless communication semiconductor growth. PC semiconductor demand will remain weak for 2013 as the market continues to be affected by the worldwide macroeconomic environment and the encroachment of tablets," said Nina Turner, Research Manager for semiconductors at IDC.

According to Abhi Dugar, research manager for semiconductors, embedded system solutions, and associated software in the cloud, mobile, and security infrastructure markets, "Communications infrastructure across enterprise, data centers, and service provider networks will experience a significant upgrade over the next five years to support the enormous growth in the amount of data and information that must be managed more efficiently, intelligently, and securely. This growth is being driven by continued adoption of rich media capable mobile devices, movement of increasingly virtualized server workloads within and between datacenters, and the emergence of new networking paradigms such as software defined networking (SDN) to support the new requirements."

Regionally, Japan will be the weakest region for 2013, but IDC forecasts an improvement over the contraction in 2012. Growth rates in all regions will improve for 2013 over 2012, as demand for smartphones and tablets remain strong and automotive electronics and semiconductors for the industrial market segment improve in 2013.

CORRECTION: In a previous version of this article stated that Mike Splinter became president/CEO of Applied Materials in 2005. This is incorrect. Mike Splinter became president/CEO of Applied in 2003. The correction has been made to this article. Solid State Technology regrets the error.

Mike Splinter, chairman and chief executive officer of Applied Materials, was awarded the 2013 Robert N. Noyce Award, presented annually by the Semiconductor Industry Association, for outstanding achievement and leadership in support of the U.S. semiconductor industry. Splinter has been on the SEMI International Board of Directors since 2005.

The award is one of the industry’s highest honors and celebrates the memory of Robert Noyce, co-inventor of the integrated circuit and co-founder of Fairchild Semiconductor and Intel Corporation. The award will be presented at the annual SIA Award Dinner to be held on November 7, 2013.

"We applaud the SIA for recognizing Mike Splinter for his enormous contributions to the semiconductor industry,” said Denny McGuirk, president and CEO of SEMI.  “As the first recipient of the Robert N. Noyce Award from the SEMI Board of Directors, his selection underscores the critical contributions of equipment and materials suppliers to the continued health and progress of the semiconductor industry."

With a portfolio of more than 10,000 patents, Applied Materials is a key equipment and technologies supplier that helps build the advanced microchips and displays essential to today’s top-selling electronic devices. Mike Splinter was named president and chief executive officer of Applied Materials in 2003 and chairman of the board of directors in 2009. Splinter is a 40-year veteran of the semiconductor industry and has led Applied Materials to record revenue and profits during his tenure.

Prior to joining Applied Materials, Splinter was an executive at Intel Corporation where he held a number of positions in his 20 years at the company, including executive vice president and director of Sales and Marketing and executive vice president and general manager of the Technology and Manufacturing Group.

Splinter began his career at Rockwell International in the firm’s Electronics Research Center. During his tenure, he became manager of the company’s Semiconductor Fabrication Operations and was awarded two patents. Author of numerous papers and articles, Splinter earned both Bachelor of Science and Master of Science degrees in electrical engineering from the University of Wisconsin, Madison.

Spansion Inc. today announced production of a new family of 16 Mb, 32 Mb and 64 Mb Spansion FL-1K Serial Flash memory devices.

“Serial Flash is one of the fastest growing memory markets,” said Alan Neibel, founder and CEO of WebFeet Research. “Worldwide serial NOR Flash shipments will grow from $1.34 billion in 2012 to greater than $2 billion by 2015. Customer platforms, particularly those with low to mid-density storage needs, benefit from serial Flash solutions for its small form factor and low pin count as a means to simplify board layouts and reduce cost."

"With the introduction of FL-1K family, Spansion continues to expand its serial peripheral interface (SPI) portfolio, delivering high performance, code-efficient small sectors and advanced security for next generation electronics," said Jackson Huang, vice president of product marketing at Spansion. "In particular, the FL-1K’s flexible data protection and one-time-programmable (OTP) features help prevent unintentional programming errors and hacking, allowing for a more secure user experience and high levels of system integrity."

The entire Spansion FL Serial Flash portfolio scales from 4 Mb up to 1 Gb to serve the broad needs of embedded applications with input output (IO) options for single, dual and quad bit read operation as well as a double data rate (DDR) mode that doubles the read throughput of the system.

Samsung announced today that it is mass producing the world’s fastest embedded memory – the industry’s first eMMC 5.0 devices – in 16 gigabyte (GB), 32GB and 64GB densities for next-generation smartphones and tablets.

Featuring an interface speed of 400 megabytes per second (MB/s), the lightning-fast eMMC PRO memory provides exceptionally fast application booting and loading. The chips will enable much faster multi-tasking, web-browsing, application downloading and file transfers, as well as high-definition video capture and playback, and are highly responsive to running large-file gaming and productivity applications.

“With timely mass production of our ultra-fast eMMC PRO line-up offering a more than 10X performance increase over external memory cards, Samsung will accelerate the spread of high-end mobile devices as the market for devices with larger screens and more multimedia functionality expands even further,” said KyongMoo Mang, vice president of memory marketing. “We will continue to provide advanced mobile memory solutions that allow users to enjoy high definition, large-volume content seamlessly, as we also strengthen technological cooperation with mobile devices manufacturers.”

Samsung’s eMMC PRO memory chips, being produced in 16, 32 and 64GB versions, are based on Samsung 64Gb 10nm class NAND flash technology.

The new Samsung chips support the eMMC version 5.0 standard now nearing completion at JEDEC – the largest standards-setting body in the microelectronics industry.

In 32GB and 64GB densities, the new memory solution has a random read speed of 7000 IOPS (inputs/outputs per second), and a random write speed of 7000 IOPS (in cache on mode, without host overhead). In addition, these chips read sequentially at 250MB/s and write sequentially at 90MB/s.

As the fastest eMMC devices at more than 10 times the speed of a class 10 external memory card (which reads at 24MB/s and writes at 12MB/s), the new mobile memory greatly enhances the movement from one application to another in multitasking activities.

Samsung’s 16GB, 32GB and 64GB eMMC 5.0 devices come in 11.5x13mm packages, making them ideal for mobile devices where space on the printed circuit board is extremely limited.

Together with its partners STFC and Fraunhofer IIS, imec announced today that the European Commission has pledged to continue funding the Europractice IC services for another three years under the Seventh Framework Programme (FP7).

"The EU’s continued support of the Europractice IC services speaks to the value of our efforts to help get European ASIC (application specific integrated circuits)-based products to market quickly and cost effectively,” stated Carl Das, director of the Europractice IC service at imec. “This funding will enable us to continue to provide the best and most advanced solutions to European academia and research institutes, start-up companies and companies within small niche markets.”

Europractice IC service is internationally recognized as a leading service to universities and industry for design, development, prototyping and manufacturing of application specific integrated circuits (ASICs) on a cost-sharing basis. Today, about 500 universities, 150 research centers and more than 200 European companies have access to this service.

Europractice IC services offers dedicated training courses on design flows and methods in advanced technologies, and has negotiated low cost opportunities with the most popular industry-standard CAD vendors and foundries.  As such, academics and research centers have access to state-of-the-art CAD tools for training and non-commercial research, and to multi-project wafer (MPW) runs for prototyping and manufacturing.  Europractice IC services also supports companies in the assembly and testing phase. Over the next three years, the service will expand its offering from ASIC services to prototyping possibilities in MEMS and photonics-related technologies.