Category Archives: Semicon West

Imec announced on Monday a cryogenic etching method that protects the surface of porous ultralow-k dielectrics against excessive plasma induced damages.

As semiconductor technology scales below the 20nm node, the capacitance increases between nearby conductive portions of high-density integrated circuits, resulting in loss of speed and cross-talk of the device. To control the increase in capacitance in deeply-scaled devices, insulating layers of porous low-k dielectrics are integrated through plasma etching. However, plasma etching exposes the dielectrics to active plasma radicals that penetrate deeply into the porous substrate, which then react and change the composition of the dielectric.

To bypass such damages, imec developed a new cryogenic etching method. By applying very low (cryogenic) temperatures during etching, a condensation of etch products in the pores of the low-k material, results in a protection of the dielectrics’ surface. Imec demonstrated the method on a porous organosilicate (OSG) film. The results showed that no carbon depletion occurred when the wafer temperature remained below a certain critical level during plasma etching.

“Our cryogenic etch method solves a key issue to further advancing scaling limits. It overcomes the disadvantages of current methods used to reduce plasma induced damage, such as dielectric etch at regular temperatures or low-k repair or high temperature pore stuffing, and it enables sub k=2.0 materials for integration,” stated Zsolt Tokei, program director interconnect at imec. “Our method is a true solution to further drive the development of next-generation, deeply-scaled technologies.”

Imec exhibits at SEMICON West, July 9-11, 2013. To learn more about imec and its new cryogenic etching method, please visit booth 1741, South hall.

 

Graph: Etching at cryogenic temperature results in targeted k-value

EV Group (EVG), a  supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today introduced the latest version of its EVG40NT automated measurement system, which is designed to work in concert with the company’s GEMINI FB fusion wafer bonding system to support the manufacture of next-generation 3D-integrated CMOS image sensors.  The enhanced EVG40NT measures wafer-to-wafer alignment accuracy to within 40nm (3 sigma), while its seamless software integration with the GEMINI FB provides a closed-loop fusion bonding control system that enables the manufacture of ultra-fine-pitch (less than two micron) through-silicon vias (TSVs).  These tighter specifications are necessary for enabling the production of 3D-integrated image sensors, and pave the way for accelerating 3D-integration with other device types, such as stacked memory.

"EV Group’s GEMINI FB fusion wafer bonding platform is the de facto industry standard for CMOS image sensor production, and already leads the industry in wafer-to-wafer alignment accuracy due to our proprietary SmartView alignment technology," stated Dr. Thorsten Matthias, business development director at EV Group.  "The integration of GEMINI FB with the enhanced EVG40NT brings statistical process control and alignment accuracy to a whole new level, and pushes 3D-IC manufacturing to new limits.  High-precision manufacturing requires accurate metrology that is seamlessly integrated into the process to enable real-time monitoring and fast corrective action.  In the case of wafer bonding, measuring and mapping each die gives valuable insight into local stress variations created during upstream processes, which can cause distortions and local misalignments further downstream."

Fusion wafer bonding is ideally suited for 3D-integrated image sensors and other stacked devices because it is a room-temperature bonding process, which eliminates misalignment due to thermal expansion mismatch between the wafers.  Having the ability to inspect the quality of the wafer bond and measure alignment accuracy prior to the final annealing step provides an easy rework path, thereby enabling 100-percent yield for wafer stacking.  The GEMINI FB platform combines EVG’s LowTemp plasma activation technology, wafer cleaning, SmartView wafer-to-wafer alignment and fusion wafer bonding in a single fully automated high-volume-manufacturing system.  The EVG40NT performs highly accurate, non-destructive, top-to-bottom side alignment accuracy measurements on double-sided structured wafers or bond interfaces, as well as critical dimension and box-in-box measurements of single and double-sided structured wafers.

"Next-generation image sensors are the technological frontrunners for 3D-IC manufacturing technology," according to Hermann Waltl, executive sales and customer support director at EV Group.  "High-density TSV arrays, sub-micron-diameter TSVs and ultra-thin wafers have all been successfully transferred into high-volume image sensor manufacturing.  Now that adoption of wafer-to-wafer 3D stacking for image sensors is well underway, we expect to see 3D-integration follow very soon for other devices such as stacked memory."

Media and analysts interested in learning more about EVG’s latest developments in wafer bonding and other processing solutions are invited to visit the company’s booth #819 in the South Hall of the Moscone Convention Center in San Francisco at the SEMICON West show this week, as well as attend the company’s presentations during the show’s technical program.  Markus Wimplinger, corporate technology development and IP director of EV Group, will present "High Resolution In-line Metrology Module for High-Volume Temporary Bonding Applications" at the SEMATECH Workshop on 3D Interconnect Metrology on Wednesday, July 10 from 11:20 – 11:40 a.m. at the San Francisco Marriott Marquis.  In addition, Dr. Thorsten Matthias, business development director at EV Group, will present "From Sensor Fusion to System Fusion" at the TechXPOT session "MEMS and Sensor Packaging for the Internet of Things" on Thursday, July 11 from 12:10 – 12:30 p.m. in the Moscone North Hall.

Following last week’s formal announcement from Governor Cuomo of the formation of the Facility 450 Consortium (F450C), ten leading nanoelectronics facility companies from around the world will collaborate at CNSE to lead the global effort to design and build the next-generation 450mm computer chip fabrication facilities. At the semiconductor industry’s annual SEMICON West tradeshow, taking place at the Moscone Center in San Francisco, CA on July 9-11, the F450C will host its first public panel discussion about facility and infrastructure solutions for the transition to 450mm wafer fabrication.

Who: Members of the Facility 450 Consortium (F450C)

What: Panel entitled: The 450mm Facility; F450C’s Parallel Pathway

When: 4-5 pm on Tuesday, July 9

Where: The Impress Lounge, located at the B Bar above Moscone’s North

Why: Beyond the manufacturing hurdles that 450mm wafer processing brings, next generation fabs present new challenges with respect to the design of the facilities, substrate handling, tool connection, chemical distribution, water and electrical systems and many other areas. Where the G450C provides leadership in the area of 450mm equipment and process technologies, the goal of the F450C is to develop facility and infrastructure solutions essential to the transition to 450mm wafer fabrication.

On the Agenda:

  • Allen Ware, M+W Group & F450C: An Introduction to the F450C
  • William Corbin, G450C: Design to Requirement at the Utility Level
  • Adrienne Pierce, Edwards Vacuum: The ŒGreen Pump Strategy
  • Lothar Till, Ovivo: Water Use at 450mm

To register for the event please RSVP to [email protected]

The Facilities 450mm Consortium (F450C) is a first-of-its-kind partnership at SUNY’s College of Nanoscale Science and Engineering (CNSE) that is leading the global effort to design and build next-generation 450mm computer chip fabrication facilities. The collaboration includes 10 of the world¹s leading nanoelectronics facility companies, including Air Liquide, CH2M HILL, CS Clean Systems, Ceres Technologies, Edwards, Haws Corporation, Mega Fluid Systems, M+W Group, Ovivo, and Swagelok. Members of F450C are working closely with the Global 450mm Consortium (G450C), as announced by New York Governor Andrew M. Cuomo, to identify viable solutions required for 450mm high-volume facility construction, with initial focus areas to include reducing tool installation cost and duration, and improving facility sustainability.

SEMI today announced that Ajit Manocha, CEO of GLOBALFOUNDRIES, has been selected to receive the “SEMI Outstanding EHS Achievement Award — Inspired by Akira Inoue.” The Environment, Health and Safety (EHS) Award is sponsored by SEMI and will be presented on July 9 at 9:00am during the SEMICON West 2013 Opening Keynote and Ceremonies in San Francisco.

“We are pleased to present this award to Ajit Manocha for his outstanding contribution and commitment to EHS issues," said Denny McGuirk, president and CEO of SEMI.  “Ajit joins a distinguished group of semiconductor executives who have been honored by our industry for notable EHS achievement and leadership.”

“Excellence in Environment, Health and Safety is not only a mandate that we set for ourselves, but a fundamental expectation of our customers and the communities where we operate,” Manocha said. “Corporate responsibility is fundamental to our culture and our value proposition to our customers, the communities in which we live and do business, and our full range of global stakeholders.”

Manocha heads GLOBALFOUNDRIES Executive Stewards Council (ESC), the leadership forum for strategic direction and accountability for risk management, corporate responsibility and sustainability.  Manocha’s leadership has resulted in significant EHS achievements at GLOBALFOUNDRIES. Those cited by the Award committee in the selection of Manocha include:

  • Zero-Incident Safety Culture — GLOBALFOUNDRIES safety goal is to continually reduce all injuries and Manocha continually challenged the EHS and project management teams to achieve zero incidents. For example, Manocha ensured that there was a strong focus on safety metrics in the executive project reviews of the new Fab 8 in Malta, New York. GLOBALFOUNDRIES’ Singapore Fabs all received “Silver Awards” for Health and Safety presented by the Workplace Safety and Health Council and supported by the Singapore Ministry of Manpower.
  • Commitment to Eco-Efficiency in Foundry Operations — In 2012, GLOBALFOUNDRIES set corporate environmental goals to reduce GHG emissions 40 percent by 2015, electricity consumption 35 percent by 2015 and water consumption 10 percent by 2015, all normalized to a manufacturing index and compared to 2010.  Fab 8 incorporates multiple energy efficiency measures, waste heat recovery, and “idle mode” for abatement systems and vacuum pumps. Fab 1 in Dresden is powered by two energy-efficient tri-generation power plants that provide electricity, heating and cooling to fab operations, GLOBALFOUNDRIES’ Singapore utilizes reclaimed NEWater for incoming supply and achieved an energy reduction of 50 GWh in 2012, with a 2013 goal of a further 57 GWh reduction.
  • WSC Commitment to Best Practices for Perfluoro-Compound (PFC) Reduction — At the 2012 annual CEO meeting of the World Semiconductor Council (WSC), Manocha led the discussion of EHS topics, urging his fellow CEOs to take action to protect the environment, conserve resources, and achieve the WSC’s PFC reduction goal. GLOBALFOUNDRIES’ newest U.S. fab, Fab 8, meets the WSC Best Practice commitment for PFC emission reduction, and Fab 1 has incorporated best practices for PFC reduction since 1999.
  • WSC Commitment to a “Conflict-Free Supply Chain” — At the 2013 WSC meeting, Manocha  championed a “Conflict-free Supply Chain” policy to address concerns related to sourcing tantalum, tungsten, tin and gold from “conflict regions” of the Democratic Republic of Congo and adjoining countries. The WSC subsequently adopted such a policy. For its part, GLOBALFOUNDRIES has already met customer requests for “Tantalum Conflict-free” products in 2012.

In addition to receiving the EHS Award at SEMICON West, Manocha will deliver the Opening Keynote for the event on July 9 at 9:00am at Moscone Center (Esplanade Hall, Keynote Stage) in San Francisco, Calif.  For more information about SEMICON West — including registration and keynote attendance —   visit http://www.semiconwest.org.

The “Outstanding EHS Achievement Award — Inspired by Akira Inoue” is sponsored by the EHS Division of SEMI. The award is named after the late Akira Inoue, past president of Tokyo Electron Limited and a strong advocate of EHS. Inoue also served on the SEMI Board of Directors. The award recognizes individuals in industry and academia who have made significant contributions by exercising leadership or demonstrating innovation in the development of processes, products or materials that reduce EHS impacts during semiconductor manufacturing.

Past recipients of the SEMI EHS Akira Inoue Award include: Richard Templeton (president and CEO, Texas Instruments), Atsutoshi Nishida (president and CEO, Toshiba), Dr. Jong-Kap Kim (chairman and CEO, Hynix Semiconductor), Dr. Morris Chang (chairman and CEO, TSMC) and other prominent industry leaders.

 

 

Europe’s recently launched industrial strategy to reinforce micro- and nanoelectronics manufacturing is more than just a vision — it’s a major opportunity for equipment and material suppliers to participate to large-scale investment projects, increase their holding in key technologies and reach out to new customers and markets. Implementation is already underway: the first EU funding calls for projects will start at the latest in early 2014 and discussions are already underway on investment priorities.  The recent launch of five EU projects, worth over €700 Million and bringing together over 120 partners, around 30 percent of which are small and medium enterprises, is proof that Europe can put its “money where its mouth is.” So what should you be doing to join the 10/100/20 momentum?

10/100/20 in a nutshell

Dubbed the ‘10/100/20’ strategy, the EU initiative will see €10 billion worth of EU co-funded projects (public/private investment), coupled with €100 Euros investment by the industry with the goal of 20 percent of global chip manufacturing by 2020. The aim is to focus on Europe’s strengths, pool together EU, national and regional resources and invest in specific areas that can give Europe a competitive edge globally. EU investment will cover the entire semiconductor manufacturing supply chain, from research to design and device makers. Maintaining leadership in equipment and material supply is clearly stated as an objective of the EU’s strategy, as is the integration of small and medium enterprises (SMEs) in value chains and providing them access to state-of-the-art technologies and R&D&I facilities.

Why get involved, especially as a SME

A number of companies, and small and medium enterprises in particular, may shy away from EU projects, perceiving them to be too complex to access and placing too much of an administrative burden for little financial gain. But the true value of EU projects lies in the new network you have access to: a variety of companies across the supply chain, many of who will become your new customers, and access to state-of-the-art research facilities and technologies. Take the example of the five pilot lines recently launched with combined funding from the EU, national governments and partner companies under the ENIAC program:

The European 450 Equipment Demo Line (E450EDL) will support the equipment and materials industry in the 450mm wafer size transition. 43 partners from 11 European countries will develop and test lithography, front end equipment, metrology tools and wafer handling and automation equipment. The partners include the large European research centers and equipment and device manufacturers, as well as smaller companies. The demo line will provide a world-class research infrastructure to validate tools that remain at the manufacturers’ sites, thus giving suppliers access to state-of-the-art facilities and an opportunity to share the knowledge and financial burden of testing their products. The Lab4MEMS project will create the first European pilot line for innovative technologies on advanced piezoelectric and magnetic materials, including 3D packaging, offers SMEs and fabless companies a manufacturing route for their future projects that has been difficult to access so far.

Interested? So what’s next?

Now is the time to decide on the technology trends that you want your company to follow and start reaching out to your partners and customers. If you think your technology could give Europe a competitive edge and should be part of Europe’s investment strategy, then start talking about it, show its benefits and convince people that this is the way to go. In the case of EU projects, there is strength in numbers, so start talking to your customers and your suppliers, look at what others are doing, and see how you can fit into the technology and investment trends.

The EU pledge of €10 billion worth of public/private co-financed projects will be spent gradually in the form of regular EU funding calls, the first of which is expected by end 2013. The call will set the overall requirements for project ideas: what technologies the project should focus on, what parts of the value chain should be partners to the project, the estimated overall budget and duration of the project as well as the technical details for applying for EU funding.  By the time the call has been published, you should already have an idea of what it is you want to do, who you want to work with and how you can fit your idea into the investment priorities that will be announced.

How to get connected

If you are visiting SEMICON West in San Francisco, then mark your calendar for Wednesday, July 10. At 16:00/4:00pm there will be a presentation of the new 10/100/20 strategy for Europe at the TechXpot in South Hall. Join us to find out more about the new strategy, why it’s important and how to get involved.

Your next major opportunity to meet with the equipment and materials industry, learn about the latest technologies and discuss the EU strategy is SEMICON Europa 2013 (8-10 October, Dresden, Germany).  Our programs will cover each of the major projects, including 450mm wafer processing, power electronics, MEMS, FDSOI as well as advanced packaging including 3D and TSV technologies.  They will in one way or the other all address Europe’s 10/100/20 strategy. The SEMICON Europa Executive Summit will discuss implementation of the strategy and we are also organizing an EU funding workshop with hands-on advice about how to identify funding opportunities for your company and join EU projects.

For more information on SEMICON Europa, please visit: www.semiconeuropa.org. The event in Dresden will again be co-located with Plastic Electronics Europe. The conference and exhibition is the leading international technology-to-industry and industry-to-industry event focused on organic and large area electronics. It is the premium forum in its kind where professionals in the area and from around the world meet to present and to discuss progress of topics. For more information, please visit: www.plastic-electronics.org.

 

Developers have made major progress in the technology to manufacture printed or flexible circuits, sensors, batteries and displays. But frankly it’s been hard to build applications with much market pull without logic or memory as well, and those have been much harder to make. However, now printed memory and solutions for integrating conventional silicon die into flexible systems are edging into production, to potentially improve performance for a wider range of applications.  On the display side, easily integrated printed or flexible transparent conductive films for touch screens are starting to see some market traction.

Yole Développement projects the market for printed and flexible electronics will remain a modest ~$176 million this year, but will see 27 percent CAGR to ~$950 million by 2020, driven largely by printed layers integrated into large OLED displays.

Thinning patterned die makes flexible silicon on polymer

One interesting solution to add performance to flexible electronics could be an open platform for making flexible silicon die. American Semiconductor proposes drastically thinning conventional fabricated silicon wafers, and coating them with a combination of polymers. The resultant silicon-on-polymer approach protects and eases handling of the ultra-thin die, says CEO Doug Hackler, who will discuss the technology in a program on such hybrid solutions in the emerging market program series at SEMICON West in San Francisco in July. He reports user interest for large area distributed sensing systems that include ICs within structural composites in aircraft bodies to monitor stress, for bio sensors that conform to the body, for RF for wireless data transmission from printed sensors, and for drivers for flexible displays.

The company has qualified TowerJazz’s 130nm process to make SOI CMOS for its initial flexible standard microcontroller, and has worked with the foundry to establish design rules to make an open platform for other designers to create their own flexible chips. American Semiconductor thins these fabricated wafers by standard methods down to about ~40µm. “And then from <40µm it gets trickier and more proprietary,” says Hackler. But once these flexible silicon-on-polymer die are diced and released, they can be handled pretty much like standard chips. “The dicing and release are a little different, but once the die are on tape, then it appears feasible to do traditional pick and place,” he says, noting the company intends to use printed connections instead of bonding wire or solder bumps. After assembly on a flexible substrate, perhaps by a pick-and-place module integrated on a roll-to-roll printing tool, the devices would typically be laminated or overcoated for additional protection. The company plans to follow its flexible microcontroller with a standard analog/digital converter to take in sensor data, and an RF IC to send out the data. 

Innovative solutions for assembling silicon on flexible substrates move towards production

Packaging and assembling tiny thin die on flexible substrates remains a challenge, but multiple suppliers are making progress towards solutions that are starting to edge into commercial production. One approach particularly suitable for attaching sensors to the body is the spring-like stretchy wiring developed by MC10 for attaching thin silicon die to flexible substrates, for everything from wearable heart rate and fitness monitors to sensor membranes that can be implanted directly on organs inside the body. VP of R&D Kevin Dowling reports the company’s first commercial application is in a soft skullcap from Reebok that uses flexibly connected motion sensors to measure impacts to the head.

Tiny die size could also help with both cost and attachment of rigid die to conformable substrates, although handling and assembling them then becomes more of an issue. Terepac Corp. CTO Jayna Sheats notes that plenty of logic for simple controls could be very tiny and low cost — microprocessors with ~8000 transistors like the Z-80 generation currently used for many embedded control applications take up  <70µm2 of silicon with 90nm design rules, for millions on a wafer. But the die are too tiny to make the input/output connections or to handle with traditional pick and place for packaging and assembly. So Terepac proposes a photochemical assembly process instead, picking up an array of thinned and diced chips with a sticky printhead, positioning the chips over the substrate with a tool similar to a proximity aligner, and vaporizing the proprietary polymer/adhesive behind each selected chip with a combination of heat and UV so it falls into the desired position.  Chips can then be attached to the flexible substrate by conductive adhesive, electroplating, or printed connections. The company is working with equipment manufacturing partners including Rockwell International to construct manufacturing facilities for customers with products for the Internet of Things.

Jabil reports progress in low temperature attachment technologies for use with heat-sensitive flexible substrates. And Sandia National Lab reports it’s come up with a solution for the common researchers’ problem in this field of how to build prototypes of flexible systems when the necessary ultra thin chips only come in costly wafer-level volumes. Researchers there have figured out how to thin off-the-shelf single die for developing flexible systems.

Printed memory targets low-cost, high-volume applications          

Thin Film Electronics, meanwhile, is developing systems that use its simple, low cost printed memory. The company’s 20-bit memory can be produced in volume for under ~$0.05, targeted at applications like consumer packaging, with volumes of billions of units a year where roll-to-roll printing makes most sense, says Chandrasekhar Durisety, assistant director, North America, who will give an update on the company’s progress towards commercialization at the session. Thin Film is introducing a next generation of passive array memory, in 4×4 (16 bit), 5×5 (25 bit) or 6×6 (36-bit) options, a more conventional format with fewer pads at higher density for easier addressing than its initial 20-bit in-line architecture. 

The company is working with a global consumer product maker on using low-cost printed memory to make brand authentication cost effective for a wide range of lower-priced products. It’s also working with major flexible packaging supplier Bemis Company Inc. on sensor labels for food, healthcare and consumer products that can collect and wirelessly communicate sensor information at roughly the same low cost as current color-changing chemical indicators. The digital system under development — with Thin Film’s printed memory, an electrochromic display from Acreo, and printed logic technology from PARC — stores data when the temperature exceeds a certain range, to indicate more clearly than a color gradient can whether the product is usable or not. 

Thin Film aims to add electronics to applications that currently don’t use them, to add simple intelligence at prices far below those possible with silicon, such as low-cost brand authentication, temperature sensors on packaging, or simple electronics in toys.  “Silicon die could add significant capability to printed electronics. But with fabrication and assembly it would likely be more expensive than either silicon or printed electronics alone,” suggests Durisety.”  

Market starts to develop for printed/flexible ITO replacements

Another key potential market for printed/flexible electronics is next-generation transparent conductive film to replace brittle and expensive indium tin oxide in touch screens and displays, lighting, and photovoltaics.  Touch Display Research says the market for non-ITO transparent conductors will be about $206 million this year, and grow to some $4 billion by 2020.  “High demand for touchscreens for notebook and PC size displays has created a shortage of ITO touch sensors since the end of last year to drive more interest in these technologies, and the more flexible and potentially cheaper replacement technologies are getting more mature,” notes Jennifer Colegrove, president and analyst, who will speak at the FlexTech workshop on transparent conductors. She notes that Atmel, FUJIFILM, Unipixel and Cambrios are all in some phase of production.

There is, however, a confusing range of contending options for processes and materials for these films.  Applied Materials has interesting progress in its roll-to-roll deposition technology, while FUJIFILM Dimatix targets ink jet printing the materials, and NovaCentrix offers rapid thermal curing that doesn’t heat the substrate. Materials options range from nano metal wires at Cambrios Technology, Carestream and Sinovia, to embossed and metalized patterns from Unipixel, to carbon nanotubes at Brewer Science and graphene at Nanotech Biomachines. 

These and other speakers will talk about the challenges and solutions to move printed/flexible electronics into real markets at SEMICON West’s emerging technology programs, July 9-11 in San Francisco.

· Mon, July 8: Market Symposium, SF Marriott Marquis, Keynote: “New Directions in Flexible and Printed Electronics,” Dr. Ross Bringans, VP at PARC (1:00-5:30pm)

· Tue, July 9: Materials Growth Opportunities at Both Ends of the Spectrum (1:30-3:30pm)

· Wed, July 10: FlexTech Alliance Workshop: Emerging Materials and Processes for Transparent Conductors, SF Marriott Marquis (10:00am-5:00pm)

· Thur, July 11: Integrating Conventional Silicon in Flexible Electronics at the Extreme Electronics TechXPOT, South Hall (10:30am-1:10pm)

For more information, visit www.semiconwest.org/SessionsEvents/PlasticElectronics

Paula Doe is an analyst for advanced technologies for the global trade association SEMI.

Multitest’s James Quinn will present during the 2013 SEMICON West exhibition and conference, scheduled to take place July 9-11, 2013 at the Moscone Center in San Francisco, CA. The presentation, entitled “Quality in 3D Assembly- Is KGD Enough,” will enable the audience to understand the additional risks of 3D assembly and match them with their own situation.

Quinn will provide an overview of the current discussion in the industry and how to manage the risks of 3D assembly. Also, the audience will learn more about the special requirements of the new approaches and understand their pros and cons. The audience will be able to apply the presented concepts to their own 3D business models. The most appropriate equipment will be discussed: What are the limitations of using probing tools or deploying final test equipment? Which strategy will offer the most synergies and reduce cost of test in the end? Finally, an analogy with the MEMS will give an interesting perspective on how to leverage the expertise that has been gained during the last decade.

Quinn is the VP of Sales and Marketing at Multitest. He has a strong semiconductor background and has served as executive VP responsible for sales and marketing at respected companies including Süss Microtec AG, MD of Süss Microtec Inc. in the U.S., and most recently as CEO of a venture capital wafer front-end equipment company in Sweden and France. Quinn studied business administration and marketing at San Francisco State University.

Through a series of lectures and workshops, SEMATECH will address R&D challenges and closing key infrastructure technology gaps from July 8–12 at SEMICON West in San Francisco, CA.

SEMATECH experts will discuss the challenges which are affecting progress in next-generation lithography techniques, new materials and processes for sub-20nm manufacturing as well as present a variety of advances in new materials and device structures and lithography.

“In order to prepare for major industry transitions that will stress the industry’s resources over the next decade, we must evolve our infrastructure collaborations to address rapidly evolving technical and business model challenges,” said Dan Armbrust, president and CEO of SEMATECH.

On July 10, Armbrust will be participating in SEMI’s executive R&D panel, “A Conversation on the Future of Semiconductor Technology.” Collaborative research experts will address the technological and financial challenges in semiconductor design, process technology and manufacturing, and share how technical contributions and synergies from all sectors of the industry are required to achieve industry-wide goals.

SEMATECH experts who are scheduled to speak on the SEMICON West TechXPOT stage, in the North and South Halls of the Moscone Center include:

  • Paul Kirsch, SEMATECH’s director of Front End Processes, “Non-Silicon R&D Challenges and Opportunities,” July 9 at 11:30 a.m., South Hall
  • Stefan Wurm, SEMATECH’s director of Lithography, “EUV Lithography: Status and Outlook,” July 10 at 10:55 a.m., South Hall
  • Abbas Rastegar, SEMATECH Fellow “Challenges of Nanodefectivity,” July 10 at 11:50 a.m., North Hall
  • Mark Neisser, SEMATECH research manager, “ITRS Front End of Line Technologies: Lithography,” July 11 at 1 p.m., South Hall

Additionally, SEMATECH will host several public workshops at the San Francisco Marriott Marquis during SEMICON West:

  • Participants will address the challenges associated with infrastructure gaps, particle metrology and filtration for the reduction and prevention of nanoparticles in solutions at the SEMATECH Workshop on Nanoparticle Defectivity Issues in Solutions on July 9 at 8 a.m.
  • Equipment suppliers, semiconductor researchers and device manufacturers will discuss how they are applying new inspection and metrology technologies as well as modified or enhanced existing techniques to improve 3D interconnect processes at the SEMATECH Workshop on 3D Interconnect metrology on July 10 at 8 a.m.
  • Co-sponsored by SEMI and SEMATECH, the Enabling Supply Chain R&D through Collaboration Workshop will identify the most significant affordability challenges for semiconductor R&D and explore new collaborative opportunities that address these challenges on July 10 at 1:30 p.m.
  • A half-day preview of this year’s International Technology Roadmap for Semiconductors will be offered at the Summer ITRS Public Conference on July 11.

Some of SEMATECH’s most prominent technologists in the nanoelectronics industry will be attending SEMICON West. To arrange for meeting attendance or interviews with executives and technical experts, please contact [email protected].

 

SEMI, the global industry association for companies that supply manufacturing technology and materials to the world’s chip makers, today reported that worldwide semiconductor manufacturing equipment billings reached US$ 7.31 billion in the first quarter of 2013. The billings figure is 8 percent higher than the fourth quarter of 2012 and 32 percent lower than the same quarter a year ago. The data is gathered jointly with the Semiconductor Equipment Association of Japan (SEAJ) from over 100 global equipment companies that provide data on a monthly basis.

Worldwide semiconductor equipment bookings were $7.78 billion in the first quarter of 2013. The figure is 23 percent lower than the same quarter a year ago and 14 percent higher than the bookings figure for the fourth quarter of 2012.

The quarterly billings data by region in billions of U.S. dollars, quarter-over-quarter growth and year-over-year rates by region are as follows:

The Equipment Market Data Subscription (EMDS) from SEMI provides comprehensive market data for the global semiconductor equipment market. A subscription includes three reports: the monthly SEMI Book-to-Bill Report, which offers an early perspective of the trends in the equipment market; the monthly Worldwide Semiconductor Equipment Market Statistics (SEMS), a detailed report of semiconductor equipment bookings and billings for seven regions and over 22 market segments; and the SEMI Semiconductor Equipment Consensus Forecast, which provides an outlook for the semiconductor equipment market.

Advanced packaging technology is undergoing dramatic changes as the smart phones and new sensor technologies demand continued improvements in form and function.  To address these massive changes, SEMICON West will feature a number of programs on new packaging technologies and processes with speakers from leading chip makers, equipment manufacturers, and material suppliers.

According to IDC, forecasts semiconductor revenues will log a compound annual growth rate (CAGR) of 4.1 percent from 2011-2016, but revenues for 4G phones will experience annual growth over 100 percent for the same period. NanoMarkets estimates that the global market for “Internet of Things” sensors will reach $1.6 billion this year and grow to a value of $17.6 billion by the end of the decade as sensors become increasingly connected to the Internet directly or through hubs.  Both trends will significantly impact semiconductor and microelectronics packaging.  Demand for equipment and related tools in the 3D-IC and wafer-level packaging area alone is forecasted to grow from approximately $370 million in 2010 to over $2.5 billion by 2016, according to Yole Developpment.

To address these changes, SEMICON West 2013 (register at www.semiconwest.org/registration), held on July 9-11 in San Francisco, will feature a number of programs on new packaging applications, requirements, technologies, and products, including:

  • Generation Mobile:  Enabled by IC Packaging Technologies — Speakers from ASE, UBM Tech Insights, Amkor Technology, SK Hynix, and Universal Scientific Industrial will present on the latest advances in wafer-level packaging, new materials, and multi-die integration, including new System-in-Package (SiP) and Package-on-Package (PoP) methods. Location: Moscone Center (North Hall), TechXPOT North, Tuesday, July 9, 10:30am-12:30pm.
  • “THIN IS IN": Thin Chip & Packaging Technologies as Enablers for Innovations in the Mobility Era — IEEE/CPMT will hold a technical workshop on the overall trend of maximum functional integration in the smallest and thinnest package with lowest packaging costs with speakers from Intel, Cisco, ASE, Micron, SK Hynix, Nanium, Kyocera and more. Location: San Francisco Marriott Marquis, Tuesday, July 9, 1:30-4:45pm.
  • Advancing 2.5D and 3D Packaging through Value Engineering — Speakers from Altera, Amkor, ASE, ASET, KPMG, UMC, STATS ChipPAC and more will take a critical look at 2.5D implementations and the current outlook for 3D packages, including tools and technologies for heterogeneous stacks. Location: Moscone Center (North Hall), TechXPOT North, Wednesday, July 10, 1:00-3:30pm.
  • MEMS & Sensor Packaging for the Internet of Things— This session will feature speakers from all parts of the ecosystem to address how future visions of a pervasive interconnected world will be realized through the heterogeneous integration of MEMS and ICs.  The program will feature keynote speaker Janusz Bryzek from Fairchild Semiconductor, and speakers from VTT Research, Fraunhofer IZM, Robert Bosche, EV Group, Dai Nippon Printing, and more. Location: Moscone Center (North Hall), TechXPOT North, Thursday, July 11, 10:30am-1:00pm.

In addition to the packaging programs, SEMICON West 2013 will also feature over 560 exhibitors with the latest innovation on microelectronics manufacturing, including over 150 exhibitors with equipment and technology solutions for advanced packaging.  Other programs and exhibitors at West will address lithography, advanced materials and processes, silicon photonics, test, LED and MEMS manufacturing, and other subjects.  For more information on SEMICON West and to register, visit www.semiconwest.org