Category Archives: Semiconductors

SEMI forecasts semiconductor equipment sales will reach $43.98 billion in 2014, a 21 percent increase over estimated 2013 equipment spending, according to the mid-year edition of the SEMI Capital Equipment Forecast, released here today at the annual SEMICON West exposition.

Following two years of conservative capital investments by major chip manufacturers, semiconductor equipment spending is forecast to grow to $43.98 billion in 2014, up from $36.29 billion projected this year.  Key drivers for equipment spending are significant NAND Flash fab investments by Samsung in China and Toshiba/Sandisk in Japan, and investments by Intel, including its fabs in Ireland.  Most major regions of the world will see significant equipment spending increases.  Front-end wafer processing equipment will grow 24 percent in 2014 to $35.59 billion, up from $28.70 billion in 2013.  Test equipment and assembly and packaging equipment will also experience growth next year, rising to $3.18 billion (+6 percent) and $2.9 billion (+14 percent), respectively. The forecast indicates that next year will be the second largest spending year ever, surpassed only by $47.7 billion spent in 2000.

"Continued strong demand by consumers for smart phones and tablet computers is driving chip manufacturers to expand capacity for memory, logic and wireless devices,” said Denny McGuirk, president and CEO of SEMI. “To meet the pent-up demand for capacity, particularly for leading-edge devices, we expect capital spending to increase throughout the remainder of this year and continue through 2014 — to post one of the highest rates of global investment for semiconductor manufacturing ever.”

Growth is forecast in China (82 percent), Europe (79 percent), South Korea (31 percent), Japan (21 percent), North America (9 percent), and Taiwan (2 percent). Taiwan will continue to be the world’s largest spender with $10.62 billion estimated for 2014, followed by North America at $8.75 billion and Korea with $8.74 billion. The following results are given in terms of market size in billions of U.S. dollars and percentage growth over the prior year:

 

 

 

 

 

By Equipment Type

 

 

yr-over-yr

 

yr-over-yr

 

2012

2013F

%Chg

2014F

%Chg

Wafer Processing

28.15

28.70

1.9

35.59

24.0

Test

3.55

3.00

-15.5

3.18

6.0

Assembly & Packaging

3.08

2.55

-17.2

2.90

13.7

Other

2.15

2.04

-5.1

2.32

13.7

Total Equipment

36.93

36.29

-1.7

43.98

21.2

 

 

 

 

 

 

By Region

 

 

yr-over-yr

 

yr-over-yr

 

2012

2013F

%Chg

2014F

%Chg

Korea

8.67

6.69

-22.8

8.74

30.6

Taiwan

9.53

10.43

9.4

10.62

1.8

North America

8.15

8.04

-1.3

8.75

8.8

Japan

3.42

3.80

11.1

4.61

21.3

Europe

2.55

2.35

-7.8

4.21

79.1

China

2.50

2.81

12.4

5.11

81.9

Rest of World

2.10

2.17

3.3

1.94

-10.5

Total Equipment

36.93

36.29

-1.7

43.98

21.2

* Totals may not add due to rounding

 

 

 

 

Source: Equipment Market Data Subscription (EMDS), SEMI

 

CEA-Leti said today that its multi-partner programs, IDEAL and IMAGINE, have demonstrated cost-effective solutions that extend 193nm immersion lithography for 1X nodes for critical levels such as contact and via, and for the cut layer, when multi-patterning is used.

Leti and Arkema launched the IDEAL program in 2011 to develop lithography techniques based on nanostructured polymers, using 300mm directed self-assembly (DSA) process and material solutions for 1X nodes. The partners, which include Sokudo, Tokyo Electron, STMicroelectronics and advanced academic laboratories, such as LTM and LCPO, have demonstrated DSA resolution capability down to sub-10nm half-pitch.

“IDEAL is addressing the limits of conventional optical lithography with a technological solution that offers potential cost-reduction opportunities,” said Serge Tedesco, Leti’s lithography program manager. Self-assembly lithography with block copolymer is a highly promising complementary technology due to its low manufacturing costs and its straightforward integration in existing device-manufacturing processes.”

The collaboration also recently completed DSA process integration in Leti’s 300mm pilot line and new specific modules have been implemented in the 300mm Sokudo DUO Track for coating, baking and PMMA removal, one of the key steps in DSA process implementation.

IMAGINE, a multiple electron-beam-lithography R&D program with a dozen partners, is focused on developing maskless lithography (ML2) based on MAPPER Lithography tools for high throughput.

The IMAGINE program this year will interface a 1,300-electron-beam tool (Matrix platform) with the Sokudo 300mm DUO Track, targeting a throughput of one wafer per hour. That will be followed by a 13,000-beam system producing a throughput of 10 wafers per hour in early 2015. The longer-term goal is a cluster of 10 modules allowing a throughput of 100 wph to support 1Xnm logic-nodes production.

Launched as a three-year project in 2009, IMAGINE was extended for four years in 2012. Besides Leti and MAPPER, the program also includes TSMC, STMicroelectronics, Nissan Chemical, TOK, Dow, JSR Micro, Sokudo, TEL, Mentor Graphics and Aselta Nanographics.

“These concrete results clearly show the industry that DSA and ML2 can extend 193nm immersion lithography by providing cost-effective solutions for critical-layer patterning,” Tedesco said. “They also demonstrate the value of combining the broad and deep technological strengths of Leti, MAPPER, Arkema, and all our partners in programs focused on meeting the demands at 1X nodes.”

 

At SEMICON West 2013, Element Six today announced it has expanded its global manufacturing capabilities of microwave chemical vapor deposition (CVD) synthetic diamond by 60 percent compared to last year. Driven by growth in the company’s semiconductor and optical business segments, Element Six has effectively ramped production capacity to meet emerging demand for thermal management solutions including gallium nitride (GaN)-on-diamond substrates and high-power resistant optical windows for Extreme Ultraviolet (EUV) lithography systems.

“Our bookings have seen a 30 percent increase in compound annual growth over the last two years, and we attribute the majority of our expansion to new applications in the semiconductor market,” said Adrian Wilson, head of the technologies division at Element Six. “We are seeing more interest from packaging designers and manufacturers as the industry comes to recognize the numerous properties and benefits of synthetic diamond, which offer our customers a distinct competitive advantage to further differentiate and strengthen their solutions for a greater return on investment.”

Element Six has expanded its high-volume manufacturing capabilities across its facilities in Silicon Valley, California, and Ascot, United Kingdom—the latter already serving as the world’s largest CVD diamond manufacturing site. The three key areas of production supported at the built-out sites include:

  • CVD diamond thermal material—delivering thermal conductivity between 1000 to 2000 W/mK, synthetic diamond is integrated into semiconductor modules to serve as an effective heat spreader—driving to more than a 20 degree temperature decrease to quadruple a device’s lifetime.
  • Synthetic diamond optical windows—an enabler for Laser Produced Plasma (LPP) EUV lithography system, Element Six’s large CVD synthetic diamond optical windows (71-80mm in diameter) withstand the power levels necessary to produce EUV light—reducing system downtime and improving wafer throughput.
  • GaN-on-diamond wafers—one of the world’s most thermally conductive materials, GaN on free standing polycrystalline CVD diamond is up to five times more conductive than copper at room temperature—enabling rapid, efficient and cost-effective heat extraction that lowers operating temperature and overall system level costs, and increases the power of RF devices. GaN-on-diamond technology earned a Compound Semiconductor Industry Award for its ability to achieve up to a three-fold improvement in heat dissipation, while preserving RF functionality.

To further consolidate and strengthen the company’s innovation capabilities, Element Six also opened its new Global Innovation Centre (GIC), based in Harwell, near Oxford, this month. Building on Element Six’s 50 years of R&D heritage, the GIC will enable the company to rapidly design, manufacture and test market-ready solutions in one location.

For those interested in learning more about synthetic diamond’s diverse properties, semiconductor applications, and the company’s research and development efforts, please visit Element Six’s booth #5750 at SEMICON West.

 

Dow Corning announced Monday that it is among the newest member organizations to join imec, a leading research center for the advancement of nano-electronics. The announcement signals expanded opportunities for both organizations to combine their expertise toward the development and broader adoption of 3D integrated circuit (IC) packaging technologies, wherein IC chips are stacked in vertical 3D architectures.

“This move is a natural and strategic step for Dow Corning and imec, as we both believe collaborative innovation is as critical to industry leadership as native expertise,” said Andrew Ho, global industry director, Advanced Semiconductor Materials at Dow Corning. “Our access to imec’s world-class resources and expertise will not only help us further refine our unique temporary bonding solution, it will allow imec to leverage that solution to advance integration of the 3D IC packaging process that they’ve been developing for years.”

Yet, before 3D IC fabrication can see broader adoption, it will require innovative advances in materials and processing technologies.

One of the key challenges imec is tackling is the bonding of the device wafer to a carrier wafer, prior to wafer thinning, and the safe debonding of the thin wafer after completion of backside processing. This was Dow Corning’s goal when designing its Temporary Bonding Solution, aims at simple processing using a bi-layer concept comprising an adhesive and release layer. The technology also enables room-temperature bonding and debonding processes based on standard manufacturing methods.

Together with imec, Dow Corning will explore its temporary bonding CMOS-compatible solution for 3D Through-Silicon-Via (TSV) semiconductor packaging. The collaboration will aim to further expand the technology’s ability to achieve simple, cost-effective bonding-debonding techniques compatible with standard manufacturing processes.

“Imec’s precompetitive programs are an essential platform for industry leaders to share the risk and cost of advanced research. As one of the semiconductor industry’s most proven pioneers in advanced silicone-based solutions, Dow Corning brings valuable materials and processing expertise to imec’s global network of innovators – as well as a key enabling technology for TSV fabrication,” said Eric Beyne, program director 3D System Integration at imec. “We look forward to collaborating closely with our newest member organization as we drive the next stage of 3D integration, and help ensure compatiblity of the proposed thin wafer carrier solution with advanced, sub-10-nanometer CMOS device technologies.”

Imec exhibits at SEMICON West, July 9-11, 2013 at booth 1741, South hall.

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today announced that it has achieved strong revenue growth and expanded its headcount for the first half of 2013.  The company attributes this success to continuing demand for its flexible process solutions designed to address high-volume manufacturing (HVM) needs across multiple markets–including 3D-ICs, MEMS, power devices and compound semiconductors.  EVG’s latest technology innovations that address these and other markets will be showcased this week at SEMICON West 2013 at the Moscone Convention Center in San Francisco.  In addition to unveiling a series of new solutions, EVG also reports that it continues to expand its wafer processing services and process development consultation capabilities worldwide as part of the company’s long-term growth strategy. 

"2013 has been a strong year for EV Group as we continue to invest in new technologies and capabilities to support our customers’ ability to ramp next-generation devices to volume production quickly and cost-effectively at high yields," said Dave Kirsch, vice president and general manager of EV Group North America.  "This requires not only leading-edge process equipment but also world-class global support and process development services. EVG’s local teams work hand in hand with our corporate headquarters to provide increased flexibility and capability for our customers.  That includes our ability to offer small-scale and pilot-production services at our global applications labs, which is a key differentiator for us and a key value proposition for customers."

Expanding sales growth and global customer support operations

During the first half of 2013, EVG achieved approximately 10 percent growth in sales and more than 10 percent increase in employees. To support its customers’ roadmaps, EVG continues to invest aggressively in research and development–approximately 20 percent of sales–in several key efforts, including 450-mm tool development. Among these efforts, EVG has invested in new state-of-the art cleanrooms and application labs with in-house process demo capability on fully automated systems at its corporate headquarters in Austria, as well as its regional headquarters in Japan and North America. 

VLSIresearch recently recognized EVG’s customer service and support, ranking it at one of the 10 Best Focused Suppliers in Chip Making Equipment. EVG was also ranked in first place in the "Other Silicon Wafer Fab Equipment" category for the company’s wafer bonding solutions. 

Leadership in wafer bonding

Already a leading supplier of HVM wafer bonding solutions, EVG recently unveiled several new platform developments in both fusion bonding and temporary bonding/debonding applications.  Yesterday, EVG unveiled the latest version of its EVG 40NT automated measurement system, which features improved specifications to achieve the highest wafer-to-wafer alignment accuracies needed for the production of next-generation 3-D integrated image sensors and stacked memory devices.  The EVG40NT is seamlessly integrated with EVG’s GEMINI FB automated production fusion bonding system to enable a closed-loop control system that facilitates customers’ ramp to volume production across multiple markets and applications.  Last week, EVG also introduced its LowTemp debonding platform, which features three high-volume-production room-temperature debonding process types and is supported by a supply chain of seven qualified adhesive suppliers to enable greater manufacturing flexibility.

Expertise in lithography and resist processing

Building upon the company’s expertise in lithography, EVG also recently unveiled the EVG120 automated resist processing system, which integrates spin/spray coating and wet processing to provide a highly flexible system that maximizes productivity and cost of ownership.  The EVG120 is ideally suited for a wide variety of markets and applications, including high-topography coating and spray coating for MEMS, thick-film resists and bumping for advanced packaging.  It is also suited for passivation, dielectrics and thick-film processing for compound semiconductor devices.

Rounding out EVG’s latest developments in wafer surface preparation, the company also recently announced the CoatsClean wafer cleaning solution, which combines process, equipment and formulation technology to deliver an innovative, low-cost-of-ownership approach to single-wafer photoresist and residue removal.  Co-developed with Dynaloy, CoatsClean is designed to address thick films and difficult-to-remove material layers for the 3D-IC/through-silicon via (TSV), advanced packaging, MEMS and compound semiconductor markets.

Presentations at SEMICON West 2013

Attendees interested in learning more about the company and its latest developments are invited to visit EVG’s booth #819 in the Moscone South Hall at SEMICON West as well as attend the company’s presentations during the show’s technical program.  Markus Wimplinger, corporate technology development and IP director of EVG, will present "High Resolution In-line Metrology Module for High-Volume Temporary Bonding Applications at the SEMATECH Workshop on 3D Interconnect Metrology on Wednesday, July 10 from 11:20 – 11:40 a.m. at the Marriott Marquis in San Francisco. In addition, Dr. Thorsten Matthias, business development director at EV Group, will present "From Sensor Fusion to System Fusion" at the TechXPOT session "MEMS and Sensor Packaging for the Internet of Things" on Thursday, July 11 from 12:10 – 12:30 p.m. in the Moscone North Hall.

Imec announced on Monday a cryogenic etching method that protects the surface of porous ultralow-k dielectrics against excessive plasma induced damages.

As semiconductor technology scales below the 20nm node, the capacitance increases between nearby conductive portions of high-density integrated circuits, resulting in loss of speed and cross-talk of the device. To control the increase in capacitance in deeply-scaled devices, insulating layers of porous low-k dielectrics are integrated through plasma etching. However, plasma etching exposes the dielectrics to active plasma radicals that penetrate deeply into the porous substrate, which then react and change the composition of the dielectric.

To bypass such damages, imec developed a new cryogenic etching method. By applying very low (cryogenic) temperatures during etching, a condensation of etch products in the pores of the low-k material, results in a protection of the dielectrics’ surface. Imec demonstrated the method on a porous organosilicate (OSG) film. The results showed that no carbon depletion occurred when the wafer temperature remained below a certain critical level during plasma etching.

“Our cryogenic etch method solves a key issue to further advancing scaling limits. It overcomes the disadvantages of current methods used to reduce plasma induced damage, such as dielectric etch at regular temperatures or low-k repair or high temperature pore stuffing, and it enables sub k=2.0 materials for integration,” stated Zsolt Tokei, program director interconnect at imec. “Our method is a true solution to further drive the development of next-generation, deeply-scaled technologies.”

Imec exhibits at SEMICON West, July 9-11, 2013. To learn more about imec and its new cryogenic etching method, please visit booth 1741, South hall.

 

Graph: Etching at cryogenic temperature results in targeted k-value

EV Group (EVG), a  supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today introduced the latest version of its EVG40NT automated measurement system, which is designed to work in concert with the company’s GEMINI FB fusion wafer bonding system to support the manufacture of next-generation 3D-integrated CMOS image sensors.  The enhanced EVG40NT measures wafer-to-wafer alignment accuracy to within 40nm (3 sigma), while its seamless software integration with the GEMINI FB provides a closed-loop fusion bonding control system that enables the manufacture of ultra-fine-pitch (less than two micron) through-silicon vias (TSVs).  These tighter specifications are necessary for enabling the production of 3D-integrated image sensors, and pave the way for accelerating 3D-integration with other device types, such as stacked memory.

"EV Group’s GEMINI FB fusion wafer bonding platform is the de facto industry standard for CMOS image sensor production, and already leads the industry in wafer-to-wafer alignment accuracy due to our proprietary SmartView alignment technology," stated Dr. Thorsten Matthias, business development director at EV Group.  "The integration of GEMINI FB with the enhanced EVG40NT brings statistical process control and alignment accuracy to a whole new level, and pushes 3D-IC manufacturing to new limits.  High-precision manufacturing requires accurate metrology that is seamlessly integrated into the process to enable real-time monitoring and fast corrective action.  In the case of wafer bonding, measuring and mapping each die gives valuable insight into local stress variations created during upstream processes, which can cause distortions and local misalignments further downstream."

Fusion wafer bonding is ideally suited for 3D-integrated image sensors and other stacked devices because it is a room-temperature bonding process, which eliminates misalignment due to thermal expansion mismatch between the wafers.  Having the ability to inspect the quality of the wafer bond and measure alignment accuracy prior to the final annealing step provides an easy rework path, thereby enabling 100-percent yield for wafer stacking.  The GEMINI FB platform combines EVG’s LowTemp plasma activation technology, wafer cleaning, SmartView wafer-to-wafer alignment and fusion wafer bonding in a single fully automated high-volume-manufacturing system.  The EVG40NT performs highly accurate, non-destructive, top-to-bottom side alignment accuracy measurements on double-sided structured wafers or bond interfaces, as well as critical dimension and box-in-box measurements of single and double-sided structured wafers.

"Next-generation image sensors are the technological frontrunners for 3D-IC manufacturing technology," according to Hermann Waltl, executive sales and customer support director at EV Group.  "High-density TSV arrays, sub-micron-diameter TSVs and ultra-thin wafers have all been successfully transferred into high-volume image sensor manufacturing.  Now that adoption of wafer-to-wafer 3D stacking for image sensors is well underway, we expect to see 3D-integration follow very soon for other devices such as stacked memory."

Media and analysts interested in learning more about EVG’s latest developments in wafer bonding and other processing solutions are invited to visit the company’s booth #819 in the South Hall of the Moscone Convention Center in San Francisco at the SEMICON West show this week, as well as attend the company’s presentations during the show’s technical program.  Markus Wimplinger, corporate technology development and IP director of EV Group, will present "High Resolution In-line Metrology Module for High-Volume Temporary Bonding Applications" at the SEMATECH Workshop on 3D Interconnect Metrology on Wednesday, July 10 from 11:20 – 11:40 a.m. at the San Francisco Marriott Marquis.  In addition, Dr. Thorsten Matthias, business development director at EV Group, will present "From Sensor Fusion to System Fusion" at the TechXPOT session "MEMS and Sensor Packaging for the Internet of Things" on Thursday, July 11 from 12:10 – 12:30 p.m. in the Moscone North Hall.

Boston University filed a lawsuit against Apple Inc. and several other big tech companies over an alleged patent infringement, a thin film semiconductor technology that they claim was developed by one of their professors.

The suit, which was filed on Tuesday in a federal district court in Boston, the school claims that Apple violated its patent on “highly insulating monocrystalline gallium nitride thin films.” BU says this technology is being used in products such as the iPhone, iPad and MacBook Air.

Boston University names Theodore Moustakas, a professor of electrical and computer engineering, as the inventor of the technology, and claims that the patent for the semiconductor film was issued in 1997.

The school is seeking financial compensation that will be determined by a jury, if the case goes to trial. However, the patent on Moustakas’ technology expires in 2015, leaving experts to speculate on what little impact a Boston University victory could have on Apple’s future.

Neither party has commented on the case.

Toshiba Corporation today announced that it will expand its No. 5 semiconductor fabrication facility (Fab 5) at Yokkaichi Operations in Mie, Japan, to secure manufacturing space for NAND flash memories fabricated with next generation process technology and for future 3D memories. Fab 5 second phase construction will start at the end of August this year and be completed in summer next year. Decisions on equipment investment and production will reflect market trends.

Yokkaichi Operations currently has three Fabs mass producing NAND flash memory, including Fab 5 phase 1. Fab 5’s construction was planned around two phases, the first of which went into operation in July 2011. After giving careful consideration to the balance of product supply and demand, and noting a recovery driven by growing demand for smartphones, tablets, SSD for enterprise servers and other new applications, Toshiba now anticipates further medium- to long-term market expansion and recognizes that the time is right to expand Fab 5.

In addition to securing capacity for future generations of NAND Flash memory fabricated with the company’s latest process technology, Toshiba will also use Fab 5 phase 2 for production of 3D memories that are expected to find growing application in coming years. The extension will allow the company to boost competitiveness and enhance its responsiveness to technology advances and market demands.

Fab 5 phase 2 will have an automated product transportation system and quake-absorbing structure and will be designed to minimize environmental loads. Deployment of LED lighting and up-to-date energy-saving production facilities, along with full and effective use of waste heat, are expected to cut CO2 emissions by 13 percent compared with Fab 4.

Going forward, Toshiba will expand its memory business and boost competitiveness by timely investments, leadership in advanced process technology and the development of new generation memories that answer market needs.

Following last week’s formal announcement from Governor Cuomo of the formation of the Facility 450 Consortium (F450C), ten leading nanoelectronics facility companies from around the world will collaborate at CNSE to lead the global effort to design and build the next-generation 450mm computer chip fabrication facilities. At the semiconductor industry’s annual SEMICON West tradeshow, taking place at the Moscone Center in San Francisco, CA on July 9-11, the F450C will host its first public panel discussion about facility and infrastructure solutions for the transition to 450mm wafer fabrication.

Who: Members of the Facility 450 Consortium (F450C)

What: Panel entitled: The 450mm Facility; F450C’s Parallel Pathway

When: 4-5 pm on Tuesday, July 9

Where: The Impress Lounge, located at the B Bar above Moscone’s North

Why: Beyond the manufacturing hurdles that 450mm wafer processing brings, next generation fabs present new challenges with respect to the design of the facilities, substrate handling, tool connection, chemical distribution, water and electrical systems and many other areas. Where the G450C provides leadership in the area of 450mm equipment and process technologies, the goal of the F450C is to develop facility and infrastructure solutions essential to the transition to 450mm wafer fabrication.

On the Agenda:

  • Allen Ware, M+W Group & F450C: An Introduction to the F450C
  • William Corbin, G450C: Design to Requirement at the Utility Level
  • Adrienne Pierce, Edwards Vacuum: The ŒGreen Pump Strategy
  • Lothar Till, Ovivo: Water Use at 450mm

To register for the event please RSVP to [email protected]

The Facilities 450mm Consortium (F450C) is a first-of-its-kind partnership at SUNY’s College of Nanoscale Science and Engineering (CNSE) that is leading the global effort to design and build next-generation 450mm computer chip fabrication facilities. The collaboration includes 10 of the world¹s leading nanoelectronics facility companies, including Air Liquide, CH2M HILL, CS Clean Systems, Ceres Technologies, Edwards, Haws Corporation, Mega Fluid Systems, M+W Group, Ovivo, and Swagelok. Members of F450C are working closely with the Global 450mm Consortium (G450C), as announced by New York Governor Andrew M. Cuomo, to identify viable solutions required for 450mm high-volume facility construction, with initial focus areas to include reducing tool installation cost and duration, and improving facility sustainability.