Category Archives: Semiconductors

SEMATECH, the global consortium of semiconductor manufacturers, today announced that William R. Rozich has assumed the role of chairman of the board of directors. Rozich, who previously was a member of the company’s board, succeeds Michael R. Polcari, who served as chairman since November 2009.

“The strength and commitment of our board is a great advantage for SEMATECH and we welcome Bill to his role as chairman. His extensive industry experience, familiarity with the progressive developments of our industry in Albany, NY and his leadership and insights are valuable to SEMATECH and our members,” said Dan Armbrust, SEMATECH’s president and CEO.

“I am honored to serve as chairman of SEMATECH’s board,” said Rozich. “SEMATECH has been setting global direction through the facilitation of precompetitive collaboration among its members for over 25 years, and I look forward to building on that history and collaborating with our board to address the complex, ever-changing technology landscape and the unique needs of our members.”

Rozich, who begins his new role July 1, most recently served as the director of semiconductor operations of IBM Corporation at the College of Nanoscale Science and Engineering in Albany, New York. He has more than 30 years of semiconductor fabrication operations experience and extensive interactions with equipment and materials suppliers, as well as leading complex alliances.

Rozich began his career at IBM in 1974 and progressed through a variety of assignments in equipment engineering, manufacturing technology and alliance management. He previously served on SEMATECH’s Executive Technical Advisory Board from 1994 through July 2006, the I300I Executive Steering Committee from 1995 until December 2000, and as a SEMATECH board member from 2006 to 2010.

Rozich received his bachelor’s degree in biology and chemistry from Fordham University and Marist College, as well as a Master of Arts degree in chemistry from State University of New York at New Paltz.

Samsung announced today that it has begun mass producing the industry’s first PCI-Express (PCIe) solid state drive (SSD) for next-generation ultra-slim notebook PCs.

“With the Samsung XP941, we have become the first to provide the highest performance PCIe SSD to global PC makers so that they can launch leading-edge ultra-slim notebook PCs this year,” said Young-Hyun Jun, executive vice president, memory sales and marketing, Samsung Electronics. “Samsung plans to continue timely delivery of the most advanced PCIe SSD solutions with higher density and performance, and support global IT companies providing an extremely robust computing environment to consumers.”

Samsung started providing the new SSD to major notebook PC makers earlier this quarter. The XP941 lineup consists of 512, 256 and 128GB SSDs.

The new Samsung XP941 delivers a level of performance that easily surpasses the speed limit of a SATA 6Gb/s interface. Samsung XP941 enables a sequential read performance of 1,400MB/s (megabytes per second), which is the highest performance available with a PCIe 2.0 interface. This allows the drive to read 500GB of data or 100 HD movies as large as 5GB in only six minutes, or ten HD movies at 5GB in 36 seconds. That is approximately seven times faster than a hard disk drive (which would need over 40 minutes for the same task), and more than 2.5 times faster than the fastest SATA SSD.

By mass producing the new PCIe SSD, Samsung has established the groundwork for a significant transition into the new paradigm in the global SSD market which enables increasing the performance and the memory storage capacity of SSDs at the same time.

The XP941 comes in the new M.2 form factor (80mm x 22mm), weighing approximately six grams – about a ninth of the 54 grams of a SATA-based 2.5 inch SSD. Also, the XP941’s volume is about a seventh of that of a 2.5 inch SSD, freeing up more space for the notebook’s battery and therein providing the opportunity for increased mobility that will enhance user convenience.

Samsung intends to continuously expand its production volumes of high-performance 10nm class NAND flash memory, in helping the company to maintain its lead in PCIe SSDs for ultra-slim PCs and notebook PCs. Furthermore, Samsung plans to introduce next-generation enterprise NVMe SSDs in a timely manner to also take the lead in that high-density SSD market, adding to its competitive edge.

Through a series of lectures and workshops, SEMATECH will address R&D challenges and closing key infrastructure technology gaps from July 8–12 at SEMICON West in San Francisco, CA.

SEMATECH experts will discuss the challenges which are affecting progress in next-generation lithography techniques, new materials and processes for sub-20nm manufacturing as well as present a variety of advances in new materials and device structures and lithography.

“In order to prepare for major industry transitions that will stress the industry’s resources over the next decade, we must evolve our infrastructure collaborations to address rapidly evolving technical and business model challenges,” said Dan Armbrust, president and CEO of SEMATECH.

On July 10, Armbrust will be participating in SEMI’s executive R&D panel, “A Conversation on the Future of Semiconductor Technology.” Collaborative research experts will address the technological and financial challenges in semiconductor design, process technology and manufacturing, and share how technical contributions and synergies from all sectors of the industry are required to achieve industry-wide goals.

SEMATECH experts who are scheduled to speak on the SEMICON West TechXPOT stage, in the North and South Halls of the Moscone Center include:

  • Paul Kirsch, SEMATECH’s director of Front End Processes, “Non-Silicon R&D Challenges and Opportunities,” July 9 at 11:30 a.m., South Hall
  • Stefan Wurm, SEMATECH’s director of Lithography, “EUV Lithography: Status and Outlook,” July 10 at 10:55 a.m., South Hall
  • Abbas Rastegar, SEMATECH Fellow “Challenges of Nanodefectivity,” July 10 at 11:50 a.m., North Hall
  • Mark Neisser, SEMATECH research manager, “ITRS Front End of Line Technologies: Lithography,” July 11 at 1 p.m., South Hall

Additionally, SEMATECH will host several public workshops at the San Francisco Marriott Marquis during SEMICON West:

  • Participants will address the challenges associated with infrastructure gaps, particle metrology and filtration for the reduction and prevention of nanoparticles in solutions at the SEMATECH Workshop on Nanoparticle Defectivity Issues in Solutions on July 9 at 8 a.m.
  • Equipment suppliers, semiconductor researchers and device manufacturers will discuss how they are applying new inspection and metrology technologies as well as modified or enhanced existing techniques to improve 3D interconnect processes at the SEMATECH Workshop on 3D Interconnect metrology on July 10 at 8 a.m.
  • Co-sponsored by SEMI and SEMATECH, the Enabling Supply Chain R&D through Collaboration Workshop will identify the most significant affordability challenges for semiconductor R&D and explore new collaborative opportunities that address these challenges on July 10 at 1:30 p.m.
  • A half-day preview of this year’s International Technology Roadmap for Semiconductors will be offered at the Summer ITRS Public Conference on July 11.

Some of SEMATECH’s most prominent technologists in the nanoelectronics industry will be attending SEMICON West. To arrange for meeting attendance or interviews with executives and technical experts, please contact [email protected].

 

EV Group and Dynaloy, LLC today introduced CoatsClean—an single-wafer photoresist and residue removal technology designed to address thick films and difficult-to-remove material layers for the 3D-ICs/through-silicon vias (TSVs), advanced packaging, MEMS and compound semiconductor markets.  In its official press release, EVG said CoatsClean provides a complete wafer cleaning solution that offers significant efficiency, performance and cost-of-ownership (CoO) advantages compared to traditional resist stripping and post-etch residue removal methods.

"Increasing wafer processing challenges associated with the adoption of new materials, device architectures and packaging schemes requires a new, holistic view of wafer cleaning, where the chemistry, process and equipment are all critically important and must be addressed in combination," stated Steven Dwyer, business director at Dynaloy.  "We’re pleased to be working with EV Group on developing and commercializing CoatsClean technology to meet the needs of our customers for a more cost-effective, flexible approach to thick-film resist removal."

The CoatsClean process and chemical formulation are engineered to perform at higher temperatures, resulting in faster stripping rates and cycle times.  This enables CoatsClean to operate as a single-wafer process for thick resist films and difficult-to-remove resists—resulting in improved performance, consistency, reproducibility and repeatability.  The engineered formulation also enables selective stripping of the resist.

CoatsClean is also unique in its ability to dispense a small amount of material on the top of the wafer, and then activate the material with direct heat.  This direct utilization of the material and heat dramatically reduces the strip material used.  CoatsClean uses fresh solution for each processed wafer compared to competing techniques that use an immersion bath—resulting in greater process efficiency and eliminating cross contamination.  The highly selective application of resist strip material eliminates damage to the wafer backside.  The entire CoatsClean process is performed in a single bowl, which reduces tool footprint.

"CoatsClean applies the right chemistry at the right process conditions to provide optimal cleaning results," stated Paul Lindner, EV Group’s executive technology director.  

EV Group will be responsible for selling the CoatsClean systems and providing customer support, while Dynaloy will be responsible for selling the CoatsClean resist stripping materials.  CoatsClean systems have already been installed for customer demonstrations, and EVG and Dynaloy are now accepting orders for the systems and resist stripping materials.

Imec and Renesas Electronics Corporation, a supplier of advanced semiconductor solutions, unveiled the world’s first multi-standard radio frequency (RF) receiver in 28nm CMOS technology, and a 28nm analog-to-digital converter (ADC) targeting wide-bandwidth standards such as LTE-advanced and next-generation WiFi. The companies released this new development at this week’s VLSI circuits Symposium in Kyoto, Japan.

Imec specializes in developing reconfigurable RF solutions, high-speed/low-power ADCs and new approaches to digitize future RF architectures and minimize antenna interface requirements. The company combines innovative design with advanced chip technology (28nm and beyond) to develop small, low-cost, energy-efficient RF solutions with competitive performance. Imec aims at developing solutions that cover all key broadband communication standards including emerging cellular and connectivity standards such as LTE advanced and next-generation WiFi.

The 28nm receiver is a linear software-defined radio (SDR) operating from 400MHz up to 6GHz and supporting reconfigurable RF channel bandwidths up to 100MHz. Through novel design and architecture techniques, the receiver operates at a low standard supply of 0.9V, while maintaining +5dBm of out-of-band IIP3 and tolerating 0dBm blockers.  It achieves noise figures down to 1.8dB, occupies an active area of 0.6mm2, and consumes less than 40mW.

The ADC is a 410MS/s dynamic 11bit pipelined SAR ADC in 28nm CMOS. It achieves a peak Signal-to-Noise Distortion Ratio (SNDR) of 59.8dB at 410MS/s with a power consumption of 2 mW. By combining novel digital calibration techniques with a new ADC architecture, an excellent energy efficiency was achieved. The ADC, including an on-chip calibration engine, occupies an active area of 0.11mm2.

“High-volume consumer devices require advanced chip technology that is cost-effective,” stated Joris Van Driessche, program manager of reconfigurable radios at imec. “Along with our partner, Renesas, we are thrilled to continue to offer innovative solutions to the market. Our 28nm wireless receiver brings the electronics industry closer to the development and adoption of next-generation wireless devices.”

“High level integration and low power are strongly required for recent wireless transceivers. There is every possibility of creating epoch-making architecture for RF and analog cores by using fine CMOS technology,” said Hisayasu Sato, senior manager of 2nd Analog Core Development Department, Core Technology Business Division, 1st Solution Business Unit, Renesas Electronics Corporation. “Through the collaboration with imec, we have been developing cutting-edge technologies. We continue to supply competitive IP cores and solutions to our customers.”

28nm CMOS technology

At this week’s VLSI 2013 Symposium in Kyoto, Japan, imec highlighted new insights into 3D fin shaped field effect transistors (finFETs) and high mobility channels scaling for the 7nm and 5nm technology node.         

At the VLSI 2013 symposium, imec presented the first strained Germanium devices based on a Si-replacement process, where a Ge/SiGe quantum-well heterostructure is grown by epitaxially replacing a conventional Si-based shallow trench isolation (STI). The technique allows for highly-versatile means of heterogeneous material integration with Si, ultimately leading the way to future heterogeneous finFET/nanowire devices.  The device shows dramatically superior gate reliability (NBTI) over Si channel devices due to a unique energy band structure of the compressively-strained Ge channel.

 “We are facing significant challenges  to scale the MOSFET architecture towards 7nm and 5nm. Besides dimension scaling, enhancing the device performance, in the face of rising parasitics and power, is a major focus of the logic device research at imec,” said Aaron Thean, logic devices program director at imec. “Among the key activities are R&D efforts investigating both high-mobility channel material and new methods of enhancing Si-based finFET.” 

With options to introduce heterostructure into next-generation finFET, quantum-well channels based on a combination of materials that enhance both mobility and electrostatics, can be engineered. At VLSI 2013, imec also presented comprehensive simulation work that investigated material combinations of Si, SiGe, Ge and III-V channels to enhance device electrostatics, providing important process guidance to extend finFET scalability.

Moreover, imec presented novel highly scalable engineering approaches to tune gate workfunction and improve mobility, noise and reliability in Si nMOS finFETs. The impact on the performance of layout-induced stress effects in scaled finFETs and the impact of random telegraph noise (RTN) fluctuation in lowly doped devices was shown.

Imec’s research into next-generation finFETs is performed in cooperation with imec’s key partners in its core CMOS programs including GLOBALFOUNDRIES, INTEL, Micron, Panasonic, Samsung, TSMC, Elpida, SK hynix, Fujitsu and Sony.

Multitest, a designer and manufacturer of final test handlers, contactors and load boards used by integrated device manufacturers (IDMs) and final test subcontractors worldwide, today announced that it will hold its annual Open House Week July 9-11, 2013. Daily tours of the Multitest Santa Clara, CA facility, located at 3021 Kenneth Street, will be held at 10 a.m. and 2 p.m.

The tours will include live demos of fully installed handling equipment, a factory tour of Multitest’s board fabrication, as well as expert discussions about the company’s innovative test solutions to fully support the opportunities of mobility. Mobile devices such as smartphones, tablets and notebooks allow connecting anywhere at any time. Semiconductors for mobile applications need to meet dedicated requirements. Semiconductor design and production implement new approaches. Advanced packaging technologies need to be supported by cost-efficient test solutions.

Multitest’s handling equipment, contactors and load boards fully support the special electrical and mechanical requirements of mobility. Mobility drives new package types, advanced IC functionalities and integration. Multitest offers the ideal test setup to leverage the optimum features from each test cell element, harmonize the elements, and offer a cost-efficient, high-performance solution. For more information or to register for the event, visit http://multitest.com/openhouse

SiOnyx Inc. announced independent validation of its image sensor technology.  The U.S. Army’s premier agency for night vision technology tested the SiOnyx XQE-1310 sensor in its labs and confirmed imaging at 1 mLux (1×10-4 Ft-candles).

"We are very excited about these independent validation test results," said Dr. Martin Pralle, VP of Government Programs for SiOnyx. "1 mLux is a critical threshold in the development of digital night vision."

For the past 60 years, night vision technology was based upon the analog image intensifier tube, a fully integrated system including both sensor and display in a single assembly.  Digital night vision offers the warfighter the ability to separate these two critical components.  This enables a highly flexible system architecture where the imager can be a clip-on module that can move from helmet to weapon sight to rail camera, while the independent heads-up display provides the imagery to the warfighter.

SiOnyx’s XQE sensors enable this capability by digitally capturing nighttime imagery using starlight and the natural ambient night sky illumination known as night glow.  Once in the digital domain, streaming and sharing the video at the unit level or with central command is readily achievable.

All sensors in the XQE family share the benefits of ultra-low read noise for extended low-light imaging and 72dB of native dynamic range.  Additionally, all XQE sensors have on-chip high dynamic range (HDR) features that allow up to 120dB dynamic range.  XQE sensors are fabricated with a standard CMOS process that offers low power, low dark current, and no sensor cooling requirements.

SiOnyx XQE image sensors are being provided on a sample basis in Q2 2013 to customers interested in evaluating the use of XQE image sensors in the next generation of imaging platforms. 

IBM and United Microelectronics Corporation, a global semiconductor foundry, today announced that UMC will join the IBM Technology Development Alliances as a participant in the group’s development of 10nm CMOS process technology.

"Established over a decade ago, the IBM alliance allows the partners to leverage our combined expertise and collaborative research and innovative technology development to address the demanding needs for advanced semiconductor applications," said Gary Patton, VP, IBM Semiconductor Research & Development. "UMC is a strong addition to the alliance."

Po Wen Yen, CEO at UMC, added, "IBM is a recognized leader in fundamental semiconductor technology. We are extremely pleased to work jointly with IBM on advanced fundamentals, and to contribute our many years of experience in developing highly competitive manufacturing technology. Our role as one of the world’s top foundries requires us to introduce leading-edge processes in a timely manner to enable next generation customer chip designs. We look forward to collaborating closely with IBM, leveraging their deep technology expertise to shorten our 10nm and FinFET R&D cycles and create a win-win situation for UMC and our customers."

The agreements between UMC and IBM expand upon their 2012 agreements concerning prior nodes, including 14nm FinFET. With IBM’s support from this collaboration, UMC will continue to improve its internally developed 14nm FinFET to offer industry competitive low-power technology enhancements for mobile computing and communication products. The parties plan to develop baseline 10nm process technology to meet the needs of UMC customers. UMC will send an engineering team to join the 10nm development work that will take place in Albany, New York, while UMC’s 14nm FinFET and 10nm implementation will take place at UMC’s Tainan, Taiwan R&D site.

At this week’s International Image Sensor Workshop (IISW 2013, Snowbird, Utah, June 12-16 2013), imec and Holst Centre presented a large-area fully-organic photodetector array fabricated on a flexible substrate. The imager is sensitive in the wavelength range suitable for x-ray imaging applications.

Because of their very high absorption coefficient, organic semiconductors allow extremely thin active layers (10 to 50 nm). Also, given their low processing temperature, they can be processed on foils. As a result, organic imagers can be more robust and light-weight compared to their traditional counterparts and may be used for conformal coating of randomly shaped substrates. Moreover, the wide variety of organic molecules available ensures that the properties of the active layer can be tuned to applications requiring specific wavelength ranges.

The presented imager is sensitive in the wavelength range between 500 and 600nm, making it compatible with typical scintillators and therefore suitable for x-ray imaging applications. It was fabricated by thermally evaporating an ultrathin (submicron) photosensitive layer of small, organic molecules (SubPc/C60) on top of an organic readout circuit. A semi-transparent top contact enables front-side illumination. The readout backplane was manufactured on six-inch foil-laminated wafers. It consists of pentacene-based thin-film transistors (TFTs) in arrays of 32×32 pixels with varying pitch (1 mm and 200 µm). To prevent degradation of the organic semiconductors in the air, the photodetector array is encapsulated. The imager was characterized under illumination with a calibrated green light-emitting diode (LED), yielding a linearly increasing photocurrent from the incident power of 3 µW/cm2. Dark current density is below 10-6 A/cm2 at a bias voltage of -2V.

organic, flexible imager
Fully-organic, flexible imager developed by imec, Holst Centre and Philips Research

“This latest achievement is a significant step forward in not only finding the optimal materials, but pinpointing the best ways to process materials into reliable organic circuits and systems with state-of-the-art performance,” said Paul Heremans, technology director at the imec/Holst Centre. “Once again, we’re proud to demonstrate how imec’s top-notch research leads to relevant industrial solutions, and subsequently brings added value to our partners’ businesses.”

This research results are presented in collaboration with Philips Research, at the (2013 International Image Sensor Workshop (IISW), sponsored by the International Image Sensor Society (IISS), June 12-16, 2013.