Category Archives: Semiconductors

senior vp and general manager of spansionSpansion Inc., a provider of flash memory solutions for embedded markets, today announced the appointment of Robin J. Jigour as senior vice president and general manager of the company’s Flash Memory Business Group.

"Robin brings deep memory product expertise to Spansion and will play an instrumental role in continuing to drive new product innovation with our NOR and NAND Flash memory solutions," said John Kispert, president and CEO of Spansion. "He has a track record of new product development that translates into new market opportunities and revenue growth."

Jigour has over 35 years of experience in the semiconductor industry with companies such as Intel, ICT, Nexcom, ISSI and NexFlash. In the mid-1990s, Jigour pioneered the industry’s first Serial Flash memories, a market segment with annual sales of over $1.3 billion and growing. In the mid-2000s, he defined and introduced the market’s first Multi-I/O (Dual and Quad) Serial Flash memories, setting the standard that is widely used in the industry today. Most recently, Jigour was vice president of Flash Memory marketing at Winbond, where he played a key role in starting the company’s Serial Flash memory business in 2005 and growing it to approximately $370 million in 2012.

"Building upon Spansion’s industry-leading technology brings forth an exciting opportunity to accelerate the use of Flash memory and continue to deliver the solutions our customers need for next-generation, high-performance memory intensive systems," said Robin Jigour. "I am thrilled to join an organization such as Spansion with unparalleled focus and execution in the embedded market."

The global semiconductor foundry United Microelectronics Corporation announced the opening of its UMC Korea office. UMC intends for this office to help expand regional business and provide local support to customers. In its official release, UMC said the proximity of its new office to its Korean customers will create working synergies that will help expedite engagement and support, thus shortening time-to-market for Korea-based customers designing and manufacturing on UMC process technologies.

Steve Wang, vice president in charge of Asia sales division at UMC said, "Korean companies have been deeply involved in the global IC supply chain as high-tech applications become increasingly mobile with more demands on power saving, portability, and performance. We see this as a great opportunity to partner with Korea based IC companies as they can take advantage of UMC’s expertise in power management, display driver, touch panel IC, and leading-edge process technologies as well as our flexible, collaborative foundry working model. We look forward to creating new opportunities with Korea-based customers with the opening of UMC’s new Korea office."

In addition to opening its Korea office, UMC was the first independent foundry to introduce a Korean language website.

A team of researchers from the Nanoengineering Research Centre (CRNE) and the Department of Electronic Engineering at the Universitat Politècnica de Catalunya · BarcelonaTech (UPC) has found a way to make the manufacture of crystalline silicon materials faster and more affordable. The results of their research have recently been published in the online version of the landmark journal Applied Physics Letters ("’Silicon millefeuille’: From a silicon wafer to multiple thin crystalline films in a single step").

Thin crystalline silicon wafers measuring around 10 µm (micres) are costly but also very sought after in the field of microelectronics, especially in view of the growing demand for 3D circuit integration with microchips. Silicon wafers also have potential photovoltaic applications in the medium term in the conversion of sunlight to electricity and the production of more affordable, more flexible and lighter solar cells.

In recent years, techniques have been developed to obtain increasingly thinner crystalline silicon wafers from monocrystalline cylindrical ingots. Layers cut from the ingots using a multithreaded saw infused with abrasive material have a minimum thickness of around 150 µm. Obtaining wafers that are any thinner is more complicated, as existing methods only allow such wafers to be obtained one at a time. Furthermore, 50 percent of the silicon is lost in the process.

The technology developed by the research team – David Hernández, Trifon Trifonov and Moisés Garín, led by Professor Ramon Alcubilla – enables a large number of crystalline layers, controlled for thickness, to be produced from a single crystalline silicon wafer in just a single step. The outcome is a kind of crystalline silicon “millefeuille” produced more efficiently, more rapidly and more affordably than by existing methods.

The methodology developed by the scientists is based on making small pores in the material and applying a high temperature during the manufacturing process. Multiple separate crystalline silicon wafers are obtained by carefully controlling the pore profiles. Precise control over diameter controls both the number of layers and their thickness. The millefeuille silicon layers are then separated by exfoliation. The resulting number of silicon layers is determined by the thickness of the layers themselves and the initial thickness of the wafer. The CRnE researchers have succeeded in creating up to 10 thin wafers (5-7mm thick) from a single 300 mm thick wafer.

Reduced costs for industry

The demand for thin and ultra-thin crystalline silicon wafers responds to the application possibilities offered by 3D circuit integration of micro-electromechanical systems (MEMS) with conventional microchips and also to the latest generation of photovoltaic technology. Wafer cutting for solar cell production, for example, has been steadily improving. Thickness has been reduced (350mm in the 1990s to 180mm currently) while efficiency has been enhanced, resulting in reduced manufacturing costs; nonetheless, greater reductions are likely to be difficult to achieve. It has been shown that, despite lesser thickness, the wafers retain a high capacity to absorb solar energy and convert it into electricity.

SEMI, the global industry association for companies that supply manufacturing technology and materials to the world’s chip makers, today reported that worldwide semiconductor manufacturing equipment billings reached US$ 7.31 billion in the first quarter of 2013. The billings figure is 8 percent higher than the fourth quarter of 2012 and 32 percent lower than the same quarter a year ago. The data is gathered jointly with the Semiconductor Equipment Association of Japan (SEAJ) from over 100 global equipment companies that provide data on a monthly basis.

Worldwide semiconductor equipment bookings were $7.78 billion in the first quarter of 2013. The figure is 23 percent lower than the same quarter a year ago and 14 percent higher than the bookings figure for the fourth quarter of 2012.

The quarterly billings data by region in billions of U.S. dollars, quarter-over-quarter growth and year-over-year rates by region are as follows:

The Equipment Market Data Subscription (EMDS) from SEMI provides comprehensive market data for the global semiconductor equipment market. A subscription includes three reports: the monthly SEMI Book-to-Bill Report, which offers an early perspective of the trends in the equipment market; the monthly Worldwide Semiconductor Equipment Market Statistics (SEMS), a detailed report of semiconductor equipment bookings and billings for seven regions and over 22 market segments; and the SEMI Semiconductor Equipment Consensus Forecast, which provides an outlook for the semiconductor equipment market.

SEMATECH announced today that Applied Seals North America (ASNA) has joined SEMATECH’s Manufacturing Technology Center, which is designed to improve semiconductor equipment manufacturing productivity, yield and cost. 

The Manufacturing Technology Center is working on particle management solutions to reduce the number of particle excursions that are found in vacuum process tools. As a part of this project, fab participants identified chemical vapor deposition (CVD) systems as the largest contributor to the failure rate and shallow trench isolation (STI) gap fill as the most problematic process application within the CVD tool group.

As a member of SEMATECH’s Manufacturing Technology Center, ASNA will collaborate with SEMATECH engineers to reduce the number of particle excursions by identifying seal designs and materials for STI gap fill process tools that are used in both 200 mm and 300 mm semiconductor manufacturing facilities. Additionally, ASNA and SEMATECH will work together to develop and introduce new material solutions that will help to significantly extend the life of the seals and reduce the number of particles that are shed from them.

“We are excited to collaborate with SEMATECH on innovative technology development to help address current and future technology challenges for sealing of vacuum systems,” said Dalia Vernikovsky, CEO of ASNA. “This project will help spearhead initiatives and collaborative efforts to drastically improve sealing performance while significantly decreasing defects that are attributed to seals. As the complexity of the technology increases, innovations in materials, seal design and particle control is essential for successful manufacturing.” 

“Particle excursions are a major cost-of-ownership issue for vacuum tools and there is a technology gap that ASNA can help address to enable fabs to squeeze additional productivity from their very expensive vacuum tools,” said Julian Richards, Manufacturing Technology project manager. “We look forward to working closely with ASNA in a collaborative effort to engineer sealing solutions that reduce the number of down events caused by particle excursions.”

The 10th International Conference on Group IV Photonics (GFP 2013) will feature presentations spanning a broad range of topics focused on silicon photonics and other Group IV element-based photonic materials and devices. Professionals from industry, academia, and government around the world will gather from August 28-30, 2013 for the GFP 2013 conference, held for the first time in Seoul, Korea at the Grand Hilton Seoul. 

Planned as a single-track conference, GFP 2013 will feature both oral and poster sessions of contributed and invited papers focused on silicon photonics and other Group IV element-based photonic materials, applications, and manufacturing technology. In addition, a post-deadline session will feature the most up-to-date results involving Group IV element photonic materials and devices, including integration and fabrication technologies.

Some of the major topic areas will include:

  • Electro-Photonic Convergence on Silicon: mainstreaming industrial Si photonics; optical interconnect technology, including light sources, modulators, and detectors; technology platforms, design tools/rules, and industrial fabrication concerns.
  • Novel Materials and Structure: novel materials and material combinations, and/or structures generating scientific interest; graphene, complex oxides, photonic crystals, gratings, as well as plasmonics and its hybrids.
  • Photonic Devices and Nanophotonics: devices and systems that are at the stage of focusing on real applications but do not necessarily need/require integration with electronics; couplers, (bio) sensors, Si photonics for telecom applications.

A supplier exhibition and a range of sponsorship opportunities are available for participating companies to promote awareness, discuss the latest new products, interact with customers and develop new sales contacts.  Individualized sponsorship opportunities are available. Contact conference planner Megan Figueroa at +1 732 562 3895 or via e-mail at [email protected] for more information.

In an industry where finer features are driving market needs, current deposition processes are no longer sufficient to address challenges like interconnect dimensions below 16/14nm or high aspect ratio TSVs (>8) without experiencing defects, voids, or low reliability. Beyond process performance, cost remains a critical consideration for manufacturing next-generation devices. Today, Alchimer is announcing a new collaboration with imec to validate its wet deposition technology.

Alchimer is a provider of wet deposition technologies for dual damascene, TSVs, MEMS and solar. The new joint development project with imec will evaluate and implement copper filling solutions for advanced nano-interconnect technologies. The focus of the project will be on Alchimer’s Electrografting products, which have demonstrated void-free filling on 7nm node devices and allow direct Cu fill on barrier with no seed layer required for damascene processes.

As CMOS scaling creates finer features, market requirements for copper damascene include smaller dimensions (≤16/14 nm) with a thin barrier layer, and thin or no Cu seed layer. Filling processes must be defect/void free to meet reliability specifications, and achieve high yields. Conventional physical vapor deposition (PVD) and chemical vapor deposition (CVD) processes are not meeting these requirements. Alchimer’s wet deposition technologies are based on a molecular build-up process that breaks through the limitations of dry deposition processes.

"We believe that as the industry moves to smaller technology nodes, performance and cost will drive technology adoption," said Bruno Morel, CEO of Alchimer. "The performance of eG in advanced damascene applications, including single and dual damascene below 20nm, hasbeen very promising both in terms of performance and cost of ownership. Collaborating with imec gives us access to tremendous resources to validate our technology’s suitability at 300mm and understand what it would take to get ready for 450mm."

The goal of the JDP is to obtain reliability data and electrical performance for eG wet deposition processes in a 300mm manufacturing environment for sub-22nm technologies. As part of the JDP, the companies will assess the plating chemistry and work to identify the optimal process conditions for 300mm wafer-level advanced damascene plating applications.

 

 

Researchers from Ulsan National Institute of Science and Technology (UNIST), South Korea, and University of Illinois, U.S.A, developed the large-scale heteroepitaxial growth III-V nanowires on a Si wafer.

The research team demonstrated a novel method to epitaxially synthesize structurally and compositionally homogeneous and spatially uniform ternary InAsyP1-y nanowire on Si at wafer-scale using metal-organic chemical vapor deposition (MOCVD). The high quality of the nanowires is reflected in the remarkably narrow PL and X-ray peak width and extremely low ideality factor in the InAsyP1-y nanowire/Si diode.

semiconductor nanowires
These are optical and SEM images of the InAsyP1-y nanowire array.

A nanowire is a nanostructure with a diameter of the order of a nanometer (10-9 meters). Alternatively, nanowires can be defined as structures that have a thickness or diameter constrained to tens of nanometers or less and an unconstrained length. Technology related to nanowires has been selected as one of the 10 Breakthrough Technologies of 2004 by MIT Technology Review.

High-aspect-ratio semiconductors have led to significant breakthroughs in conventional electrical, optical, and energy harvesting devices. Among such structures, III-V semiconductor nanowires offer unique properties arising from their high electron mobility and absorption coefficients, as well as their direct bandgaps.                                   

A common technique for creating a nanowire is Vapor-Liquid-Solid (VLS) synthesis. This process can produce crystalline nanowires of some semiconductor materials. However, metal catalysts, usually expensive noble metals, should be used for initiating the VLS mechanism. In addition, these metal catalysts are known to significantly degrade the quality of semiconductor nanowires by creating deep levels, thus limiting practical applications of nanowires into opto-electronic devices.

In this work, however, Prof. Choi’s group developed a novel technique of growing III-V semiconductor nanowires without metal catalysts or nano-patterning. Metal-organic chemical vapor deposition (MOCVD, AIXTRON A200) was used for the growth of the InAsyP1-y. 2 inch Si (111) wafer was cleaned with buffer oxide etch for 1 minute and deionized (DI) water for 2 seconds. Then, the wafer was immediately dipped in poly-L-lysine solution (Sigma-Aldrich inc.) for 3 minutes then rinsed in DI water for 10 seconds. The Si substrate was then loaded into the MOCVD reactor without any delay. The reactor pressure was lowered to 50 mbar with 15liter/min of hydrogen gas flow. Then the reactor was heated to growth temperatures (570 – 630 ℃), and stabilized for 10 minutes.

Kyoung Jin Choi, associate professor at Ulsan National Institute of Science and Technology (UNIST), Korea, and Xiuling Li, Professor at University of Illinois, U.S.A. led the research and this description of the new research was published on the web on May 7 in ACS Nano. (Title: Wafer-Scale Production of Uniform InAsyP1-y Nanowire Array on Silicon for Heterogeneous Integration).

"If we develop new technology which manages the density of nanowire and bandgap energy with further study, it is also possible to produce high-efficiency and low-cost large scale solar cells," said Prof. Choi. "This technology will give us a chance to lead the research on the new renewable energy."

Altera Corporation today introduced its Generation 10 FPGAs and SoCs, offering system developers breakthrough levels of performance and power efficiencies. Generation 10 devices are optimized based on process technology and architecture to deliver the industry’s highest performance and highest levels of system integration at the lowest power. Initial Generation 10 families include Arria 10 and Stratix 10 FPGAs and SoCs with embedded processors. Generation 10 devices leverage the most advanced process technologies in the industry, including Intel’s 14-nm Tri-Gate process and TSMC’s 20 nm process. Early access customers are currently using the Quartus II software for Generation 10 product development.

Altera said its Stratix 10 FPGAs and SoCs are designed to enable the most advanced, highest performance applications in the communications, military, broadcast and compute and storage markets, while slashing system power. Leveraging Intel’s 14nm Tri-Gate process and an enhanced high-performance architecture, Stratix 10 FPGAs and SoCs have an operating frequency over one gigahertz, 2X the core performance of current high-end 28nm FPGAs. For high-performance systems that have the most strict power budgets, Stratix 10 devices allow customers to achieve up to a 70 percent reduction in power consumption at performance levels equivalent to the previous generation.

Altera is announcing the technology details of Stratix 10 FPGAs and SoCs today as part of the Generation 10 portfolio introduction, and will disclose more details on the product at a later date. Stratix 10 FPGAs and SoCs provide the industry’s highest performance and highest levels of system integration, including:

  • More than four million logic elements (LEs) on a single die
  • 56-Gbps transceivers
  • More than 10-TeraFLOPs single-precision digital signal processing
  • A third-generation ultra-high-performance processor system
  • Multi-die 3D solutions capable of integrating SRAM, DRAM and ASICs

Arria 10 FPGAs and SoCs are the first device families to roll out as part of the Generation 10 portfolio. Leveraging an enhanced architecture that is optimized for TSMC’s 20nm process, Arria 10 FPGAs and SoCs deliver higher performance at up to 40 percent lower power compared to the previous device family.

Early access customers are currently using the Quartus II software for development of Arria 10 FPGA and SoCs. Initial samples of Arria 10 devices will be available in early 2014. Altera will have 14 nm Stratix 10 FPGA test chips in 2013 and Quartus II software support for Stratix 10 FPGAs and SoCs in 2014.

Sapphire is currently used in some exotic, luxury phones. However, the sapphire price reduction combined with the massive adoption of touch screens in smartphones have stimulated the interest of cell phone OEMS for this material. Crystal growth equipment manufacturer GTAT is leading the charge and recently created a lot of buzz around this application and on the OEM front. Apple is rumored to have conducted an extended due diligence.

Adoption of sapphire in mobile display covers represents the single largest opportunity. It remains, however, uncertain. Yole Développement sees four major challenges: technology, supply chain, cost and market acceptance. Crystal growth and finishing technologies still need to be optimized in order to guarantee stable performance and reduce the price gap with chemically strengthened glass like Corning’s Gorilla. Yole Développement’s analyst estimates that the current cost of manufacturing a sapphire display cover is around $22 but could drop to $12 and ultimately below $10. It remains to be seen if the bill of material increase vs. the $3 glass display cover will be absorbed by the OEM in exchange for increased market share or if the consumer will value the increased durability brought in by the sapphire cover and accept paying a premium.

sapphire substrate use

It is difficult to predict the success of sapphire in this application. However, Yole Développement expects that some OEMs will probe the market and introduce some models featuring sapphire by late 2013 – early 2014. Initial customer reaction will have a strong influence on the future of the technology. If successful, strong market traction could ease the funding for the more than $1.5 billion in capex needed to serve this industry and set up the supply chain to serve this application.

Glass cover lens manufacturers might seize the opportunity. Because of their vast existing glass finishing capacity that could be converted to process sapphire and their privileged access to leading smartphone OEMs, those companies could beat established sapphire finishing companies into this market. However, another scenario would see collaborations between some leading sapphire and cover lens makers in order to pool technical knowledge, capacity and customer access under the push of some smartphone OEMs.

In any case, if this opportunity materializes, it will transform the sapphire industry with new players emerging, and overall production capacity increasing by a factor of more than 7x.

Defense semiconductor and other applications represent 25% of the sapphire industry revenue

“These applications will bring in revenue of $240 million in 2013 and, excluding the display cover opportunity, will increase at a nine percent CAGR to US$366 million in 2018. Watch windows are currently the single largest application with revenue of US$120 million in 2012. Most applications are fairly mature with relatively low growth opportunity with the exception of the emerging mobile device camera lens cover and the aerospace market, driven by the F-35 jet fighter program and the emergence of sapphire-based transparent armors,” explains Eric Virey, senior analyst, Compound Semiconductors, at Yole Développement.

Most applications have their own “eco-systems” with preferred material vendors, finishing companies, growth technologies and barrier of entrance. The defense market, for example, is characterized by strong technical barriers in both growth and finishing, combined with export restrictions and national preferences. The semiconductor market is also fairly concentrated with two companies, Saint-Gobain Crystals and Gavish which both hold the bulk of the market due to their technology for growing the large sapphire tubes used in many plasma tools. However, competition is increasing on simpler parts like viewports and lift pins.

Industry transformation could open the door for new applications

Driven by the promise of large volumes for the LED industry, sapphire crystal growth and manufacturing capacity has increased by more than 8x in the last five years. In just the last two years, more than 80 companies have announced their intention to enter the industry, bringing the potential number of players to 130+ with more than 50 of these potential new entrants located in China.

The entrance of aggressive new players with large idle capacity is likely to challenge established players in many applications. Yole Développement expects those players to initially enter domestic and international markets with low barrier of entrance and later expand their reach as their technology matures.

Excess capacity and increased competition have created a challenging environment for sapphire makers. However, they also drove prices down dramatically and stimulated technology improvements to further reduce cost and improve capability (crystal sizes, shapes …). Yole Développement expects that ultimately, this will be favorable for the industry: lower price and improved crystal growth and finishing capabilities will open the door to a large gamut of new applications where sapphire has been considered for its performance but never adopted because of its cost.