Category Archives: Semiconductors

AIXTRON SE today announced that the University of Cambridge has successfully commissioned another multi-wafer Close Coupled Showerhead (CCS) MOCVD reactor at its new facility at the Department of Material Science and Metallurgy. The CCS 6×2-inch system will be configured to handle single 6-inch (150mm) wafers (1×6-inch). 

“We will be using the systems to expand our research efforts for LED and electronic devices based on gallium nitride (GaN) epitaxy on 6-inch silicon wafers,” said Professor Sir Colin Humphreys, director of research in the Department of Materials Science and Metallurgy. “We already use one CCS 6×2-inch system in our work, but the gathering pace of GaN-on-Si development means that we need an extra system with large diameter wafer handling.”

The Centre for Gallium Nitride in Cambridge,UK, not only grows nitride semiconductors, but is one of the few places in the world to have on the same site extensive advanced characterization facilities such as electron microscopy, X-ray diffraction, atomic force microscopy, photoluminescence (PL), and Hall effect equipment. The team also includes specialists in basic theory for understanding in detail the physical properties of nitride semiconductor materials.

 “AIXTRON is proud to continue its long-standing collaboration with the University of Cambridge and to supply another state-of-the-art CCS research system to complement the university’s existing reactor,” said Tony Pearce, managing director at AIXTRON. “Under Prof. Humphreys’ lead, the Cambridge group has developed world leading GaN-on-Si processes and we look forward to further supporting this work with this new system.”

MOCVD reactor

Cree, Inc. and Delta Energy Systems announce a breakthrough in the photovoltaic (PV) inverter industry with the release of Delta’s new generation of solar inverters, which utilize SiC power MOSFETs from Cree. The use of SiC MOSFETs in the next-generation PV inverters can enable significant new milestones in power density, efficiency and weight.

 “The next-generation PV inverters from Delta are designed to set a new milestone of power density by utilizing SiC MOSFETs,” said Mr. Klaus Gremmelspacher, head of research and development for PV inverters at Delta Energy Systems. “The SiC MOSFETs from Cree were essential for us to realize our goals for new, high-power inverters that are lightweight and have industry-leading efficiency.”

Cree released the first silicon carbide MOSFETs, used for their ability to cut losses and allow PV inverters to run at higher efficiencies and higher power densities, in 2011 and a dramatically improved, second-generation SiC MOSFET in 2013. Now, as a milestone product announcement, Delta Energy Systems, a subsidiary of Delta Electronics Group, one of the world’s largest providers of power management solutions, has incorporated Cree SiC MOSFETs into its next-generation solar power inverter. Utilizing 1200V SiC MOSFET’s from Cree in an 11kW PV inverter, Delta has already been able to extend the DC input voltage range while maintaining and even increasing the maximum efficiency of its previous products. The Delta 11kW booster, which employs Cree’s SiC MOSFET and now has 1kV DC input instead of 900V, is targeted for release in Q2 2013.

“We are pleased and honored to have Delta Energy Systems as a customer for our SiC MOSFET,” Dr. Scott Allen, senior director of marketing, Cree Power, remarked. “They are utilizing the 1200V, 160m-Ohm MOSFET, which has matured rapidly since its release in 2011 and offers industry-leading performance and cost. Advanced technology customers like Delta are now moving aggressively forward with our SiC MOSFET technology, which enables reduced size, weight and cost for PV inverters, from 20 to 50% when compared with silicon, while at the same time maintaining or increasing efficiency.”

Intermolecular, Inc. today announced that it has entered into a multi-year technology development and IP licensing agreement with Micron Technology, Inc., focused on technology development and related IP for advanced memory technologies.

In their official press release, Intermolecular said the collaboration will involve development activities at Intermolecular’s R&D center in San Jose and will leverage Intermolecular’s High Productivity Combinatorial (HPC) innovation platform. The collaboration is also anticipated to provide time-to-market improvements for Micron through acceleration of advanced materials development.

"New materials and device architectures are increasingly needed to meet future embedded and mobile technology requirements, and partnering with Micron in this exciting area is a significant milestone for Intermolecular," said Dave Lazovsky, president and CEO of Intermolecular.

"Micron’s global R&D efforts are focused on creating advanced memory solutions, and we believe development of new materials technology is a key enabler to many of our future challenges," said Scott DeBoer, Micron’s vice president of research and development. "We look forward to working with Intermolecular to enhance our novel materials development efforts."

Intermolecular’s mission is to improve R&D efficiency in the semiconductor and clean energy industries through collaborations that use its HPC platform, which allows R&D experimentation to be performed at speeds up to 100 times faster than traditional methods.

Founded in 2004, Intermolecular is based in San Jose, California. Intermolecular’s focus in on a proprietary approach to accelerate research and development, innovation, and time-to-market for the semiconductor and clean-energy industries. The approach consists of its proprietary High Productivity Combinatorial (HPC) platform, coupled with its multi-disciplinary team.

Read more on advanced memory trends.

Researchers at the Georgia Institute of Technology are developing a novel technology that would facilitate close monitoring of structures for strain, stress and early formation of cracks. Their approach uses wireless sensors that are low cost, require no power, can be implemented on tough yet flexible polymer substrates, and can identify structural problems at a very early stage. The only electronic component in the sensor is an inexpensive radio-frequency identification (RFID) chip.

Georgia Tech researcher smart skin sensors
Credit: Gary Meek

Moreover, these sensor designs can be inkjet-printed on various substrates, using methods that optimize them for operation at radio frequency. The result would be low-cost, weather-resistant devices that could be affixed by the thousands to various kinds of structures.

“For many engineering structures, one of the most dangerous problems is the initiation of stress concentration and cracking, which is caused by overloading or inadequate design and can lead to collapse – as in the case of the I-35W bridge failure in Minneapolis in 2007,” said Yang Wang, an assistant professor in the Georgia Tech School of Civil and Environmental Engineering. “Placing a ‘smart skin’ of sensors on structural members, especially on certain high-stress hot spots that have been pinpointed by structural analysis, could provide early notification of potential trouble.”

Wang is collaborating with a team that includes professor Manos M. Tentzeris of the School of Electrical and Computer Engineering, and Roberto Leon, a former Georgia Tech professor who recently moved to Virginia Tech. The work is supported by the Federal Highway Administration.

crack testing smart skin sensors
Credit: Gary Meek

This research was recently reported in IEEE Antennas and Wireless Propagation Letters, Volume 11, 2012, and International Journal of Smart and Nano Materials, Volume 2, 2011. Parts of this research were also presented at ASME 2012 Conference on Smart Materials, Adaptive Structures and Intelligent Systems (SMASIS) and several other conferences.

Antennas as Sensors

The Georgia Tech research team is focusing on wireless sensor designs that are passive, which means they need no power source. Instead, these devices respond to radio-frequency signals sent from a central reader or hub. One such reader can interrogate multiple sensors, querying them on their status at frequent intervals.

As long as the structural member to which the antenna/sensor is affixed remains entirely stable, its frequency stays the same. But even a slight deformation in the structure also deforms the antenna and alters its frequency response. The reader can detect that change at once, initiating a warning months or years before an actual collapse.

“A key benefit of this technology is that it’s completely wireless,” Wang said. “It doesn’t require a battery, and you don’t have to climb around on bridges running long connecting cables.”

The research team has developed a prototype strain/crack sensor that has been successfully tested in the laboratory, Wang said. The simple device consists of a small piece of copper mounted on a polymer substrate, plus a 10-cent 1mm by 1mm RFID chip. The chip is used to distinguish each individual sensing unit from others. The simple sensor architecture allows it to be made at very low cost and to potentially be deployed in large quantities on any bridge.

Inkjet-Printed Circuits

More sophisticated designs are in the works. Tentzeris’ team is tackling an approach that produces strain sensors using different applications of inkjet printing technology.

One such design uses a silver-nanoparticle-based ink that is applied to a flexible or semi-flexible substrate, said Rushi Vyas, a Ph.D. student working with Tentzeris. The ink lays down a structure that can change properties in response to strain.

smart skin sensors for aging infrastructure
Credit: Gary Meek

A second approach involves the use of inkjet-printed carbon-nanotube-based structures, Vyas said. In this case, the nanotubes themselves produce an altered response when subjected to deformation.

In laboratory testing, the team’s prototype sensors have demonstrated high sensitivity in response to even slight changes in metal structures, Wang said. The sensors have been able to reliably detect a degree of deformation change as low as tens of microstrains (one microstrain equals 0.0001 percent, or 1 part per million), and they can continuously monitor stress accumulation until the metal develops a severe crack.

One issue still being addressed is the capacity of the passive sensor to respond to a reader. A reader transmits a radio-frequency beam to a sensor, which utilizes that received energy to reflect a signal back to the reader.

But this technique can be rather inefficient, Vyas said. A signal from a reader might travel 50 feet, yet the sensor’s response might only travel back 10 feet. One issue is that readers are limited by FCC regulations, which govern how much power can be transmitted to the sensor.

Increasing the Power

What’s needed are ways to supply a sensor with a power source that would increase the range of the response signal. Batteries are not preferred because they can be undependable and require periodic replacement.

One candidate solution – in addition to solar-energy and vibration-energy harvesting – is scavenged energy, Tentzeris said. A Georgia Tech team that includes Tentzeris and Vyas is researching ways to gather power from ambient or electromagnetic energy in the air, such as television, radio, radar or other manmade signals found in Earth’s lower atmosphere.

Scavenging experiments utilizing TV bands have already yielded power amounting to hundreds of microwatts. Multi-band systems are expected to generate one milliwatt or more – enough to operate some small electronic devices such as low-power wireless sensors.

Tentzeris noted that smart-skin technology may soon help to enable a broad range of applications. These could include not only real-time stress monitoring in bridges, factories and buildings, but also new and extremely lightweight aircraft with self-sensing/self-diagnostic capabilities, and battery-free methods for monitoring structures after major disasters such as earthquakes or hurricanes.

“The wireless strain sensor could prove to be an effective, low-cost and easy-to-scale solution to a very important need,” Tentzeris said. “A simple device – consisting of an antenna, an inexpensive RFID chip and some power-boosting technology – could quietly monitor at-risk structures for many years, and then send back a real-time warning if there’s suddenly a problem.”

BeSpoon, a fabless semiconductor company, and CEA-Leti have demonstrated an IR-UWB integrated circuit able to measure distances within a few centimeters’ accuracy, and have established a world-record operating range at 880m (standard regulation) and 3,641m (emergency situations).

IC world-record distance measurement

Impulse radio ultra-wideband (IR-UWB) is recognized as an ideal technology for indoor applications, both in terms of accuracy and robustness. It measures distances within a few centimeters’ precision and is not affected by walls or people passing by.

The BeSpoon and Leti collaboration overcame two challenges sometimes associated with this technology: the difficulty integrating it on a single chip and its perceived limited operating range.

The chip jointly designed by BeSpoon and Leti features a full-blown IR-UWB CMOS-integrated transceiver that is able to perform accurate distance measurements. The standalone chip (RF front-end and digital base band) is designed for a straightforward integration within smartphones or set-top boxes.

Furthermore, BeSpoon has demonstrated the capability to comply with the strict regulation of IR-UWB, and yet operate up to 880m in line of sight. A world record distance measurement has been established at 3,641 meters, in compliance with the regulation for emergency situations.

“Indoor location is only beginning and, very soon, robustness and precision will be key to offering great new services,” said Jean-Marie André, BeSpoon CEO. “Mobile geofencing is another exciting development of our technology.”

“This achievement capitalizes on the UWB expertise Leti has developed over the past 12 years,” said Laurent Malier, CEO of Leti. “The world record distance measurement is a major milestone in our partnership with BeSpoon, and a source of great satisfaction for the people involved in this collaboration.”

Leti is an institute of CEA, a French research-and-technology organization with activities in energy, IT, healthcare, defence and security. NEMS and MEMS are at the core of its activities. CEA-Leti operates 8,000-m² of state-of-the-art clean room space on 200mm and 300mm wafer platforms. It employs 1,700 scientists and engineers including 320 Ph.D. students and 200 assignees from partner companies. CEA-Leti owns more than 2,200 patent families.

 BeSpoon is a fabless semiconductor company, responsible for cracking the individual positioning problem. BeSpoon chips can track items or individuals within a few centimeters.

E.ON Elnät Sverige AB announced a step to enhance their ability to glean real intelligence from smart grid data. E.ON, part of one of the largest private energy companies in the world, announced that they will be using Ericsson’s hosted solution including consulting and systems integration services, harnessing big data and smart grid solutions for its customers.

The solution is an important step towards real-time big data measurements, supplying E.ON’s customers with accurate and up-to-date information on energy consumption. The evolution of smart grids is a priority in a number of countries, including EU and the US, and will eventually create a smart energy network that manages a huge amount of data in 24-hour intervals.

Ericsson’s solution will gather data from energy meters and provide collected data to E.ON’s internal IT environment. Data will be exported daily rather than monthly, increasing data delivery by 3000 percent. Ericsson will also provide E.ON with related field services. The agreement stretches over the next five years, and includes more than 600,000 metering points in northern Stockholm, Malmö, Örebro, as well as Norrköping and Skåne.

The Ericsson Smart Metering solution, provided as a service, helps providers like E.ON become more efficient. The solution combines managed services, consulting and systems integration services and includes meter reading and control, meter management, meter monitoring, Service Layer Agreement (SLA) management, work force management, asset management, business process management, as well as field services and an operations center.

This will open new opportunities for efficient grid and consumption management as well as a seamless integration of locally produced renewable energy into the infrastructure.

Currently regulations within the European Union require utilities, or Distribution System Operators, to deploy smart metering in order to ensure the first steps towards Smart Grids and more efficient energy usage.

Error correction code and redundant addresses are both techniques well-known in memories as a way of optimizing yield. But new data from the University of Ferrara shows that these common techniques may be overused. By classifying erratic bits more carefully, it’s possible to use less ECC and up to 35 percent less redundancy.

At the International Reliability Physics Symposium (IRPS), being held April 14-18, 2013 at the Hyatt Regency Monterey Resort & Spa in Monterey, CA, researchers will present a paper titled “Erratic Bits Classification for Efficient Repair Strategies in Automotive Embedded Flash Memories.”

The figure shows three different types of erratic bits and their behavior over time. In the first case (top), the read current of one type of erratic bit is shown, where it will periodically spike to a higher read current. The second type of erratic bit (middle) is in a low read current state half the time, and a high read current state the other half. A third class of erratic bits (bottom) is going back and forth constantly between the high read state and the low read state.

erratic bits
Examples of different erratic bit signatures (left). Normal and erratic states are highlighted for clarity. Erratic bits percentage per signature classification in delay time cycling experiments are shown on the right.

“Typically, what would be done when you have these bad bits after you’ve created them after so many read-write cycles, is you would just use a redundant address repair on these, “ said Charlie Slayman, IRPS Vice Technical Program Chair. “But what the authors are saying is that that redundant address space costs you more money. You’ve got to build in more memory. For a certain class of bad bits, the erratic bits [top] that are most of the time good and only infrequently bad, don’t bother using redundant address, just use your error correction code and that’s sufficient. Save your redundant addresses for the really bad erratic bits.” 

The ability of a resistive RAM device to maintain its resistance state, otherwise known as retention time, can be impacted by the electrode materials used.  At the International Reliability Physics Symposium (IRPS), being held April 14-18, 2013 at the Hyatt Regency Monterey Resort & Spa in Monterey, CA, a paper on memory, authors from Minatec and various research centers  presented a paper titled “Investigation of the role of electrodes on the retention performance of HfOx based RRAM cells by experiments, atomistic simulations and device physical modeling.”

The RRAM consists of two metal electrodes and a hafnium oxide between those, where the hafnium oxide acts as a variable resistor (see figure). The authors of this paper considered the use of different metal materials. In one case, they used platinum for the electrode, and in a second example they used TiN/Ti to sandwich the hafnium oxide. They showed that the Pt/Pt electrode device loses its on-state resistance sooner than the TiN/Ti device.

"They attribute the phenomenon to oxygen interstitials in the HfO2, and TiN-Ti’s ability to basically getter those interstitials (Oi) and pin them at the surface," according to Charlie Slayman, IRPS Vice Technical Program Chair.

Atomistic structure of HfO2 with an Oi intersitials leading the the recombination of Oi+Vo in Pt/Pt during reset (left). Atomistic structure of Ti with an Oi interstitial creating more Vo in HfO2 (right).

New flash memory chips are replacing the floating gate with thin layers of material that "trap the charge." The charge trap is a sandwich of materials such as silicon-oxide-nitride-oxide-silicon (SONOS), metal-oxide-nitride-oxide-silicon (MONOS) and tantalum-aluminum oxide-nitride-oxide-silicon (TANOS), all of which are substantially smaller than the floating gate.

At the International Reliability Physics Symposium (IRPS), being held April 14-18, 2013 at the Hyatt Regency Monterey Resort & Spa in Monterey, CA, researchers from Mila Polytechnic, Micron and Intel will present a paper titled "Resolving Discrete Emission Events: a New Perspective for Detrapping Investigation in NAND Flash Memories." The authors say their results provide important insights into the fundamental scaling challenges of aggressively-scaled NAND flash technologies, where the impact of single electrons and defects becomes increasingly important.

Charlie Slayman, IRPS Vice Technical Program Chair, said that researchers looked at the effects of individual discrete traps in the tunnel oxide for 30nm NAND flash (see figure).

flash memory
Example of ΔVT, i and dti extraction from a detrapping VT transient.

"Looking at the threshold voltage over time, you can actually see the threshold voltage change in discrete quantized steps. They’ve analyzed this and determined these are individual traps in the device that are trapping and detrapping. This will have an impact on future flash technologies where single electron and defects become increasingly important," Slayman said.

Researchers are developing a new type of semiconductor technology for future computers and electronics based on "two-dimensional nanocrystals" layered in sheets less than a nanometer thick that could replace today’s transistors.

The layered structure is made of a material called molybdenum disulfide, which belongs to a new class of semiconductors – metal di-chalogenides – emerging as potential candidates to replace today’s technology, CMOS.

New technologies will be needed to allow the semiconductor industry to continue advances in computer performance driven by the ability to create ever-smaller transistors. It is becoming increasingly difficult, however, to continue shrinking electronic devices made of conventional silicon-based semiconductors.

"We are going to reach the fundamental limits of silicon-based CMOS technology very soon, and that means novel materials must be found in order to continue scaling," said Saptarshi Das, who has completed a doctoral degree, working with Joerg Appenzeller, a professor of electrical and computer engineering and scientific director of nanoelectronics at Purdue’s Birck Nanotechnology Center. "I don’t think silicon can be replaced by a single material, but probably different materials will co-exist in a hybrid technology."

The nanocrystals are called two-dimensional because the materials can exist in the form of extremely thin sheets with a thickness of 0.7 nanometers, or roughly the width of three or four atoms. Findings show that the material performs best when formed into sheets of about 15 layers with a total thickness of 8-12 nanometers. The researchers also have developed a model to explain these experimental observations.

Findings are appearing this month as a cover story in the journal Rapid Research Letters. The paper was co-authored by Das and Appenzeller, who also have co-authored a paper to be presented during the annual Device Research Conference at the University of Notre Dame from June 23-26.

"Our model is generic and, therefore, is believed to be applicable to any two-dimensional layered system," Das said.

Molybdenum disulfide is promising in part because it possesses a bandgap, a trait that is needed to switch on and off, which is critical for digital transistors to store information in binary code.

Analyzing the material or integrating it into a circuit requires a metal contact. However, one factor limiting the ability to measure the electrical properties of a semiconductor is the electrical resistance in the contact. The researchers eliminated this contact resistance using a metal called scandium, allowing them to determine the true electronic properties of the layered device. Their results have been published in the January issue of the journal Nano Letters with doctoral students Hong-Yan Chen and Ashish Verma Penumatcha as the other co-authors.

Transistors contain critical components called gates, which enable the devices to switch on and off and to direct the flow of electrical current. In today’s chips, the length of these gates is about 14 nanometers, or billionths of a meter.

The semiconductor industry plans to reduce the gate length to 6 nanometers by 2020. However, further size reductions and boosts in speed are likely not possible using silicon, meaning new designs and materials will be needed to continue progress. The research was funded by the National Science Foundation.