Category Archives: Semiconductors

At ISSCC 2013, Holst Centre and imec have presented an innovative method for the power-management of piezoelectric energy harvesters. The proposed interface IC provides energy-aware supply voltage regulation from cold start with a power consumption of less than 140nW. A power efficiency of 90 to 94% is achieved in a wide power range of 1µW to 1mW. Key building block of the IC is a new active diode bridge rectifier with zero bias property.

Holst Centre and imec have developed an integrated piezoelectric energy interface IC with zero bias rectifier circuit and energy-aware supply regulator. The IC is suitable for regulating the voltage in battery-less smart sensors that are typically composed of a piezoelectric energy harvester, sensors, an energy storage system and wireless transceivers.  With a power consumption of less than 140nW and a power efficiency as high as 90 to 94% in a wide 1µW-to-1mW power range, the circuit outperforms existing implementations that typically suffer from high energy losses.

The IC regulates the AC power from the piezoelectric energy harvester and supplies an energy-aware DC voltage to the user. The rectified output voltage is connected to a capacitor which accumulates the harvested energy. When this output voltage reaches a target startup voltage, a power-OK signal is set and a timer oscillator with 8-bit counter is enabled. When the output voltage reaches the threshold voltage set by a shunt regulator, a USE signal is generated and the counter is stopped. The USE signal triggers the users to draw current from the capacitor until the USE signal is reset. The harvested power will charge the capacitor again and the cycle is repeated.

The proposed circuit has been fabricated in a commercial TSMC 0.25µm CMOS process with 0.25mm2 active area. The harvested power was generated by an aluminum nitride vacuum packaged MEMS piezoelectric harvester. Tests have demonstrated that the IC itself consumes only 40nA of quiescent current and that this new method of power management delivers optimal power matching for input AC-peak voltages up to 5V.

A comparison with state-of-the-art interfaces shows that this solution consumes less power than previous solutions (only 140nW) while at the same time providing full cold-start, high efficiency AC-DC conversion, output regulation and energy awareness.

Solid State Technology is pleased to announce Subu Iyer, IBM Fellow, will be giving the keynote address at The ConFab 2013 in Las Vegas on Tuesday, June 25, 2013. Iyer will speak on orthogonal scaling to fill today’s fabs in the future.

“Semiconductor technology development is at an inflection point where the historical expectations for node-to-node productivity are difficult to maintain,” Iyer writes in his abstract. “This slowing down of classical scaling is an opportunity to explore alternatives ways of leveraging both our technology and existing fab infrastructure. This talk will ask some tough questions on what we can really expect from recent technological innovations such as Hi K gate dielectrics and FINFETs in the future and what some other constraints are. We will explore the addition of orthogonal features to existing technologies that will enhance them significantly. Fabs of the future will be more diverse, offer a variety of novel capabilities, be more intimately tied to their clients whether they are captive or not, and will have to be a bigger part of the overall systems’ supply chain.”

Subramanian S. Iyer is an IBM Fellow at the Systems and Technology Group, and is responsible for technology strategy and competitiveness, embedded memory and three-dimensional Integration. He obtained his B.Tech at IIT-Bombay, and Ph.D. at UCLA. His key technical contributions have been the development of the world’s first SiGe base HBT, electrical Fuses, eDRAM and 45nm technology used at IBM and IBM’s development partners. His current technical interests and work lie in the area of 3-dimensional integration for memory sub-systems and the semiconductor roadmap. He is a Distinguished Alumnus of IIT Bombay and received the IEEE Daniel Noble Medal for emerging technologies in 2012.

For more information on The ConFab 2013 or to register, visit The ConFab section of our website.

A new undergraduate program approved this week at the University of Central Florida (UCF) will help the U.S. stay competitive in global technology as well as broaden the path for students seeking rewarding careers in the important field of optics and photonics, say leaders of SPIE, the international society for optics and photonics.

UFC photonics undergrad program
Photo: UCF

The UCF Board of Trustees yesterday announced a new Bachelor of Science degree program in photonics science and engineering, in partnership between the College of Optics and Photonics (CREOL) and the College of Engineering and Computer Science, said CREOL Director Bahaa Saleh. Students will receive their degrees from both colleges. The first classes of the new program will be offered this fall.

The curriculum is designed to prepare students for a wide variety of jobs in optics and photonics and to satisfy the requirements of ABET accreditation based on the criterion established by SPIE and IEEE for degrees in the field recently, Saleh said. ABET is a nonprofit, non-governmental organization that accredits college and university programs in the disciplines of applied science, computing, engineering, and engineering technology.

“I am personally excited to see this announcement because it serves as another indicator that optical and photonics engineering is finally coming of age as a discipline, providing a distinct program choice and career path for students to follow,” said Barry Shoop, professor and head of the Department of Electrical Engineering and Computer Science at the U.S. Military Academy in West Point, New York. Shoop leads the SPIE/IEEE team to develop ABET program criteria for optical and photonics engineering.

Shoop said that establishment of the new program also is “further evidence of the growth, influence, and importance of optical and photonics engineering as a discipline. This program joins a growing number of optical engineering programs across the country that are attracting some of the best and brightest students to serve the growing needs of industry, government and academia.”

“The program will help ensure that the U.S. has a chance to participate at all levels in the coming growth in photonics,” said SPIE CEO Eugene Arthurs. “As ABET moves to accredit programs in optics and photonics, UCF, long a leader in technology transfer programs and photonics education, is again showing its innovative drive. This timely new undergraduate program reflects the growing awareness of a vital field that has already changed the world in multiple ways – the Internet, laser surgery, and 3D imaging, to name a few — and that will continue to change the world many times over.”

Students in the new UCF program will study geometrical optics, physical optics, optical materials, and photonics devices and systems, striking a balance between general engineering breadth and basic knowledge and practical skills for solving problems and designing and building working optical systems, Saleh said. Along with core courses, the program will provide hands-on training in laboratories and a capstone senior design project, and participation in a summer internship program with local industry will be encouraged.

As UCF faculty were instrumental in the development of the new ABET program criteria for optical, photonics and similarly named engineering programs, this new program is anticipated to become ABET accredited, which will directly serve the growing need for photonic engineers and further increase the visibility and recognition of optical and photonics engineering as a discipline.

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Solid State Technology is pleased to announce that Dr. An Steegen, Senior Vice President of Process Technology at imec, will be presenting on CMOS scaling by 10nm at The ConFab 2013. In her presentation, Steegen will explain the paradigm shift underway in the semiconductor industry, where chip scaling is possible with the right materials and new design architectures to enable tomorrow’s smart systems.

“To answer the industry’s need for extreme computation and storage capabilities, bound by (ultra) low-power or heat dissipation constraints, we have to push the limits of transistor scaling,” Steegen writes in her abstract. “To reach ultra-small dimensions beyond 10nm, advanced patterning processes, new materials with high electron mobility – such as germanium, IIIV materials or graphene – and new device architectures – such as FinFETs and TunnelFETs – with heterojunctions will be required, as well as a reduction in process complexity and variability control New memory concepts are also on the rise, including resistance based memories, such as resistive RAM, phase-change RAM or spin-torque transfer magneto resistive RAM and vertical Flash memory. These advanced memory technologies further reduce cost and maximize density. Introduction of the third dimension will allow for even more functionality, compute power and memory on a chip.”

Steegen holds a Ph.D. in Material Science and Electrical Engineering from the Catholic University of Leuven, KU Leuven, in collaboration with the Interuniversity Microelectronics Center, imec, in Belgium. Throughout the years, Steegen has published more than 30 technical papers and she holds many patents in the field of semiconductor development. She joined IBM Semiconductor R&D in Fishkill, NY, in 2001, where she was the director of the bulk CMOS technology development division until 2010. In that position, she served as the host executive in charge of IBM’s logic International Semiconductor Development Alliance and was responsible for establishing strong collaborative partnerships in innovation and manufacturing as measured by power/performance, defect density and cost/complexity.

For more information on speakers or to register, visit The ConFab section of our website.

Volunteers sponsored by SPIE, the international society for optics and photonics, were in Washington, D.C., last week to thank Congressional representatives for recent support for photonics R&D and to urge future support for in several key areas vital to economic growth and scientific progress. They were among more than 250 scientists, engineers, and business leaders visiting Capitol Hill March 12-13 for a Congressional Visits Day (CVD) sponsored by the Science-Engineering-Technology (SET) Work Group.

  • SPIE volunteers focused primarily on three messages identified by the SPIE Engineering, Science, and Technology Policy (ESTeP):
  • Support for a National Photonics Initiative (NPI) being forwarded by a coalition of professional societies including SPIE, LIA (Laser Institute of America), IEEE Photonics Society, OSA (The Optical Society), and the American Physical Society.
  • Overhaul of export controls.
  • Eliminating restrictions on government-employee travel to scientific conferences.

Members and staff were generally in agreement that now is a critical time for the U.S. to be prioritizing investments in science and innovation and that while control of spending is important, funding for R&D and for STEM education are important ways to grow the economy.

"I appreciate the preparations by SPIE to support those of us working in photonics to succinctly bring our message to our representatives in Congress,” said Jim McNally, director of operations at Applied Technology Associates. “The background materials and coaching tips provided really help us to clearly and concisely articulate the critical priorities to support our nation’s competiveness and innovation edge. We were able to have very productive discussions emphasizing the urgency for a National Photonics Initiative."

Ben Franta, a student at Harvard University, called the event “an eye-opening experience.”

“In the same way that being a scientist or engineer is very different from what most other people imagine it to be, our government operates in a way that’s different from what we might expect by watching or reading the news,” he said.

Franta said the CVD program was “a valuable opportunity to engage with our lawmakers in a way that can lead to real results. To me, the fact that SPIE makes such great use of this opportunity — both to communicate with Congress and to educate students like me — shows a forward-looking approach to promoting technologies in optics and photonics in this country and throughout the world."

An evening reception provided an informal opportunity for CVD participants to talk with Congressional members and staff, and included an exhibition in which company representatives demonstrated products based on discoveries and innovations resulting from federal R&D funding. SPIE co-sponsored a booth highlighting the recent National Academies report, “Optics and Photonics: Essential Technologies for our Nation,” and raising awareness of efforts to create the NPI.

At the reception, the SET George E. Brown Award was presented to Representatives Mike Honda (D-California) and Richard Hanna (R-New York), to recognize their outstanding efforts to advance and promote science, engineering, and technology on Capitol Hill.

More than 50 percent of all industrial innovation and growth in the United States since World War II can be attributed to advances pioneered through scientific research, with publicly funded R&D the vital foundation for today’s scientific and technological progress.

Technology transfer from academic research adds billions of dollars to the economy each year and supports hundreds of thousands of jobs.

SPIE is the international society for optics and photonics, a not-for-profit organization founded in 1955 to advance light-based technologies. The Society serves nearly 225,000 constituents from approximately 150 countries, offering conferences, continuing education, books, journals, and a digital library in support of interdisciplinary information exchange, professional networking, and patent precedent. SPIE provided over $3.2 million in support of education and outreach programs in 2012.

MagnaChip Semiconductor Corporation, a Korea-based designer and manufacturer of analog and mixed-signal semiconductor products, and Sidense Corp., a developer of logic non-volatile memory one-time programmable (OTP) memory IP cores today announced that Sidense’s SLP 1T-OTP macros have been fully qualified for MagnaChip’s 180nm 1.8/3.3/18V high-voltage CMOS and mixed-signal process. Semiconductor devices fabricated in these processes are used in applications such as LED lighting controllers, display controllers and power-management ICs (PMICs) for mobile and other high-volume applications.

"Leading semiconductor device manufacturers are already using Sidense 1T-OTP macros for LED energy management solutions fabricated using MagnaChip’s leading process technology," said Tom Schild, Sidense’s Vice President of Worldwide Sales and Marketing. "By offering our very dense and low-power SLP memory macros in MagnaChip’s HV process, customers have a proven platform in which they can take full advantage of the benefits of 1T-OTP memory and its cost-effectiveness, reliability and security advantages over eFuse, mask ROM and other NVM technologies."

SLP macros are available in a comprehensive range of off-the-shelf configurations ranging from 128 bits for trim and configuration applications up to 256 Kbits per macro for code storage and multiple NVM uses. Benefits of Sidense’s SLP OTP include small footprints to minimize cost, low power consumption, field-programmability, available configurations with word widths up to 128 bits and fast read access to allow executing code from OTP for many applications.

Headquartered in South Korea, MagnaChip Semiconductor is a Korea-based designer and manufacturer of analog and mixed-signal semiconductor products for high volume consumer applications.

Sidense Corp. provides secure, very dense and reliable non-volatile, one-time programmable (OTP) memory IP for use in standard-logic CMOS processes with no additional masks or process steps required. Sidense SiPROM, SLP and ULP memory products, embedded in more than 250 customer designs, are available from 180nm down to 28nm and are scalable to 20nm and below.

The Institute of Microelectronics (IME), a research institute of the Agency for Science, Technology and Research (A*STAR) in Singapore, has launched the Copper (Cu) Wire Bonding Consortium II. The consortium which rides on the successes of Phase I launched in 2010 aims to improve the reliability of semiconductor devices by tackling copper wire bonding issues related to corrosion and stress. Members of this consortium span across the semiconductor supply chain including Atotech S.E.A., GLOBALFOUNDRIES, Heraeus Materials and Infineon Technologies.

Copper, which offers favorable cost, performance, quality and reliability benefits over gold, has become one of the preferred materials for wire bonding interconnects in microelectronics. Today, however, the industry still faces many technical challenges in developing copper as the best choice for chip-to-package interconnection. One of the key technical issues is related to copper’s hardness relative to gold, which requires bonding parameters to be very well controlled in order to eliminate the risk of damaging bond pads and underlying structures. Another daunting challenge of using copper is its reactivity with oxygen in the surrounding air which causes corrosion-related problems. These two issues can affect the reliability and quality of semiconductor devices.

Against this background, the IME Cu Wire Bonding Consortium II will conduct a study on corrosion and the mechanisms on the effect of various packaging materials. To understand the effects of copper wire hardness when bonding on different materials, the consortium will carry out modeling and characterization of copper wire bonding stress using stress sensors developed under the scope of Phase I of the Cu Wire Consortium to provide an improved technique of measuring wire bonding stress. The outcome of this work will enable semiconductor manufacturers as well as test and packaging houses to develop solutions to improve product reliability, especially those targeted at high reliability applications.

"IME has been dominant in the R&D of advanced packaging technologies and remains focused on developing solutions to help the industry reduce manufacturing costs,” said Prof. Dim-Lee Kwong, Executive Director of IME. “We are excited to begin a new phase of the Cu Wire Bonding Consortium to enable the development of robust, high reliability and low cost interconnection solutions."

“GLOBALFOUNDRIES is pleased to be in this consortium as the first phase of our partnership has successfully resulted in optimizing 0.7 mil in copper wire bonding on our 40nm product and passed the JEDEC reliability test,” said Mr. K. C. Ang, Senior Vice President and General Manager for GLOBALFOUNDRIES Singapore. “The success has brought us to the next phase of collaboration where the process will be tested on our advanced 28nm product. We see this industry collaboration truly augmenting the value proposition we have on offering quality and cost effective wafer manufacturing to our customers.”

“Infineon has been part of the Copper Wire Bonding Consortium since it first launched in 2010,” said Mr. Guenter Mayer, Senior Director, Package Technology and Innovation, Infineon Technologies Asia Pacific. “Today, our interest lies in copper wire bond interconnect performance and reliability in semiconductors that can meet the stringent quality requirements of Automotive and Industrial applications.”

“Being a member of the consortium enables Heraeus to work with strong industry partners and research institutes in order to have more in-depth understanding of wire bond reliability. The consortium members are of various backgrounds, such as wafer manufacturers, mold compound manufacturers and end users. The wafer manufacturers design pad structures that cater for the harder copper wire which created challenges on 1st bond mechanical stress during bonding and package reliability due to corrosion. Other partners are mold compound manufacturers and end users who can equally contribute to materials and assessment on best combination of package design, materials and application solution,” said Mr. Bernd Stenger, Executive Vice President, Contact Materials Division, Heraeus Materials Technology.

Advances in petawatt photonics, laser systems, optical sensing, holography, metamaterials, nonlinear and quantum optics, and related topics will be presented by leading experts at SPIE Optics + Optoelectronics in Prague next month. The weeklong conference will also feature sessions for industry and presentation of three prestigious awards from the International Commission for Optics (ICO).

More than 600 technical papers on the latest developments in optics and optoelectronic devices, technologies, and their integration will be presented at SPIE Optics + Optoelectronics 2013 next month. The international symposium will be held at the Clarion Congress Hotel in the historic city of Prague, Czech Republic, April 15-18, 2013.

Conferences will cover recent advances in petawatt photonics, high-power and high-repetition rate systems, diode-pumped laser systems, and FELs, along with the latest research in optical sensing, holography, x-ray optics, metamaterials, nonlinear and quantum optics.

Attendees will be able to learn first-hand about new developments in ground-breaking intense laser-matter interaction research, inspired by what will be the future site of one of the world’s most advanced laser facilities, ELI Beamlines. The facility, expected to be open to users by January 2016, will serve researchers in laser science as well as other fields including material sciences, engineering, medicine, biology, chemistry, and others with its multifunctional and user-friendly design.

A two-day exhibition running April 16-17 will connect researchers with more than twenty suppliers and project partners from around the world who provide optical instruments and systems to address an ever-increasing number of industrial and research applications, in areas such as imaging and vision, defence, telecommunications, space, transportation, industrial process control, and laser fusion.

A special technical session on the prospects for inertial fusion energy (IFE) will feature invited speakers from the HiPER and LIFE laser energy projects.

ICO, the International Commission for Optics, will present three of its annual awards during the event, with talks by award winners:

Industry-focused sessions include:

  • A one-day Laser Energy Workshop emphasising engagement with industry as an important element of the Laser Energy roadmap, both in a facility delivery context and also as assurance that arising technological advances are exploited for shorter-term economic impact, along with discussion of the key enabling technologies and the underlying physics of laser-driven fusion and progress to “first ignition” at NIF.
  • A one-day National Science Foundation (NSF) Workshop on “US-Czech frontiers in photonics,” covering non-linear optics, EUV-soft x-rays, microstructured and specialty fibers, optical sensors, optical manipulators, metamaterials, and THz and Mid IR photonics.
  • An afternoon workshop for ELI prospective users, bringing together researchers who are developing and building the ELI Beamlines facility with members of the community of prospective users of proposed beamlines and end-stations. Several roundtable discussions will be held to identify and specify the most promising user experiments.
  • Symposium General Chairs are Jiří Homola of the Institute of Photonics and Electronics of the Academy of Sciences of the Czech Republic (IPE/ASCR), Chris Edwards of the UK Central Laser Facility, Science and Technology Facilities Council, Mike Dunne of Lawrence Livermore National Lab, and Ivo Rendina of the Instituto per la Microelettronica e Microsistemi. Miroslav Miler (IPE/ASCR) is Honorary Chair.

Accepted conference proceedings papers will be published in the SPIE Digital Library as soon as approved after the meeting, and in print volumes and digital collections.

SPIE is an international society for optics and photonics, a not-for-profit organization founded in 1955 to advance light-based technologies.

The Semiconductor Machinery Manufacturing industry has been highly volatile during the past five years.

“Demand from the industry is determined by conditions in the downstream semiconductor manufacturing, which is characterized by rapid technological change,” said IBISWorld industry analyst Andrew Krabeepetcharat.

Industry performance also derives from downstream demand for electronic products that use semiconductors. Revenue is expected to decline at an average annual rate of 0.5% to $1.7 billion during the five years to 2013, largely due to a decline in demand from downstream manufacturing.

Revenue declined quickly in 2009 as semiconductor manufacturers postponed machinery purchases in the midst of the recession.

“Downstream demand for products that use semiconductors also experienced weaker demand during the period,” said Krabeepetcharat.

Industry revenue fell 33.3% in 2009 but bounced back 32.7% in 2010. Despite a quick recovery, growth quickly slowed and came to a small decline through 2013, with revenue falling 0.9% from the previous year. Over the five years to 2018, industry revenue is projected to grow slowly.

The Semiconductor Machinery Manufacturing industry has a moderate level of concentration. IBISWorld estimates that the four largest industry operators will account for less than 15.0% of industry revenue in 2013, down from about up from about 44.0% in 2008. Several firms left the industry in 2009 with the number of firms falling 10.7% during the year, contributing to the increase in market share concentration. During the five years to 2013, the number of industry firms is projected to decline at an average annual rate of 3.0% to 24 companies. Over the next five years, the number of industry firms is expected to decline at an average annual rate of 2.6% to 21 firms as major companies acquire smaller competitors and other firms move operations overseas.

Exports account for a large share of revenue, accounting for about 54.1% in 2013. International trade of industry products fell heavily during the economic downturn as global demand fell and semiconductor manufacturers delayed capital investments. During the past five years, the value of exports is expected to increase at an average annual rate of 2.1% to $923.5 million. Imports also declined during the economic downturn, increasing at an average annual rate of 1.0% to $243.0 million in 2013.

ChipStart LLC, a provider of semiconductor intellectual property (SIP), and DELTA Microelectronics, a provider of ASIC services for the semiconductor industry, announced a new joint venture this week. The relationship will involve the sale, marketing and global representation of DELTA’s design services, including its production and test capabilities through ChipStart’s extensive sales channel.

“We are extremely pleased to be in a position to take advantage of DELTA’s intimate knowledge of the mobile payment, RFID and sensor markets and to be able to offer their extensive portfolio of solutions,” said Howard Pakosh, President and Chief Executive Officer of ChipStart. “By officially recognizing this partnership, we are continuing to grow our capabilities and services giving our customers the tools necessary to develop next generation technologies.”

“DELTA Microelectronics is happy to team with ChipStart. Their portfolio is complementary to DELTA’s, so we expect that our customers can gain significant synergies from this cooperation,” said DELTA’s Vice-President of Sales and Marketing, Gert Jørgensen.

ChipStart will promote DELTA Microelectronics’ ASIC Design Services to system houses and semiconductor communities throughout North America, with the specific focus on chips used in the areas of mobile payment systems, RFID, optical systems and sensor systems.

ChipStart is a semiconductor intellectual property solution company based in Palo Alto, California. ChipStart provides sales, marketing, and support engagement solutions for companies that commerce third party semiconductor intellectual property, high quality pre-verified subsystem solutions, and support design services for ASIC and fabless semiconductor companies. ChipStart products are used as critical components of communications, consumer and computing products including switches, routers, modems, cellular phones, set-top boxes, HDTVs, DVD players and PCs.