Category Archives: Semiconductors

North America-based manufacturers of semiconductor equipment posted $1.07 billion in orders worldwide in February 2013 (three-month average basis) and a book-to-bill ratio of 1.10, according to the February Book-to-Bill Report published today by SEMI.  A book-to-bill of 1.10 means that $110 worth of orders were received for every $100 of product billed for the month.

The three-month average of worldwide billings in February 2013 was $975.3 million. The billings figure is 0.8 percent higher than the final January 2013 level of $968.0 million, and is 26.3 percent lower than the February 2012 billings level of $1.32 billion.

book-to-bill ratio semiconductor industry Feb 2013

“Three-month average bookings and billings posted by North American semiconductor equipment providers remain above parity and consistent with prior month levels," said Denny McGuirk, president and CEO of SEMI. "We expect modest investment by semiconductor makers in the first half of the year with foundry and advanced packaging technology among the near-term spending drivers.”

The SEMI book-to-bill is a ratio of three-month moving averages of worldwide bookings and billings for North American-based semiconductor equipment manufacturers. Billings and bookings figures are in millions of U.S. dollars.

The data was compiled by David Powell, Inc., an independent financial services firm, without audit, from data submitted directly by the participants. SEMI and David Powell, Inc. assume no responsibility for the accuracy of the underlying data.

The data is contained in a monthly Book-to-Bill Report published by SEMI. The report tracks billings and bookings worldwide of North American-headquartered manufacturers of equipment used to manufacture semiconductor devices, not billings and bookings of the chips themselves. The Book-to-Bill report is one of three reports included with the Equipment Market Data Subscription (EMDS).

SEMI is the global industry association serving the nano- and micro-electronic manufacturing supply chains. SEMI maintains offices in Bangalore, Beijing, Berlin, Brussels, Grenoble, Hsinchu, Moscow, San Jose, Seoul, Shanghai, Singapore, Tokyo, and Washington, D.C.

 

Next generation memories are the emerging non-volatile memory technologies, which are expected to replace existing memories. Not all existing memories will be replaced, however. Next generation memories majorly targets the non-volatile memories such as NAND and NOR. High write and read latency, scalability, high endurance etc. makes emerging memories the best replacement for traditional non-volatile memories. Out of these memories, only MRAM and FeRAM have reasonable market share, and they are quite commercialized in the market. PCRAM has very marginal market and memristor is set to enter the market by the end of 2013   

The major drivers for the next generation memory market are faster switching time, high endurance and power efficient. In addition, the huge application base of traditional memories will also become the driver for this market. Since these memories are not completely established, there are still flaws in processes which causes drawbacks like instability and low write endurance rate in some of the memories. As mentioned, these memories are the replacement for flash memories in near future. The flash market has already tapped the huge market and hence it makes the way for next generation memories.   

The major issue for next generation memories is its design cost. Not all the processes are intact yet, hence it increases the cost of the process and design. However, early adoption of these memories will be the game changing strategy for memory market. Most of the next generation memories are also called as “Universal memory,” which performs both the function volatile and non-volatile. So the early adoption of such memories will be the crucial for the companies.   

The companies currently involved in next generation memory market are Samsung (South Korea), SK Hynix (South Korea), Micron (U.S.), Elpida (Japan), Toshiba (Japan), Powerchip (Taiwan), Winbond (Taiwan), Fujitsu (Japan), Nanya (Taiwan), Rambus (U.S.), Everspin Technology (U.S.), IDT Incorporated (U.S.), HP (U.S.).  

Researchers sponsored by Semiconductor Research Corporation (SRC), a university-research consortium for semiconductors and related technologies, today announced development of a modeling process designed to simulate atomic-level etching with chemicals that are effective alternatives to widely used perfluorocarbon (PFC) gases. The novel approach under way at the University of California, Los Angeles (UCLA) will identify and evaluate green plasma chemistries for processing emerging memory/logic devices and through-silicon-via (TSV)-enabled technologies for the semiconductor industry.

In order to continue the advancement of transistor and memory cell performance, the research will focus on several promising new materials that have been introduced for future generations of integrated circuits (ICs). To exploit this opportunity, the industry requires new and effective etch processes with which to pattern the next-generation fabrics.

The aim of the UCLA research effort within the SRC-funded Engineering Research Center for Environmentally Benign Semiconductor Manufacturing (ERC) is to identify environmentally friendly chemistry for patterning materials in IC fabrication and verify their performance to be equal to, or greater than, current state-of-art plasma chemistries.

The unique performance characteristics required for advanced devices and technologies dictates the use of certain materials and corresponding aggressive etch chemistries. Next-generation processes will benefit from chemicals that are more benign, less hazardous and more efficiently utilized.

The advanced modeling approach developed by UCLA will predict emissions from plasma processes and assess the effectiveness of non-PFC etch chemistries compared to those using PFC gases. While historically PFC gases have been an enabling component of semiconductor manufacturing, the industry continues to aggressively pursue and implement PFC replacement and abatement strategies. The UCLA research will greatly assist and accelerate this industry effort.

“The industry can’t afford to conduct thousands of hands-on experiments to measure, one at a time, the chemical reactions that etch at a molecular scale,” said Dr. Jane Chang, lead researcher for the SRC-funded activity at UCLA. “With modeling, we can conduct those evaluations in a relatively short time. In terms of months rather than years, we expect to identify the conditions for a benign etch chemistry that will help to facilitate the industry’s technology roadmaps.”

Peeling Layers at the Atomic Level

Chemical vapor deposition and plasma etch have been extensively used as part of an integrated process flow to realize chip manufacturing over the last several decades. 

In this era of nanotechnology, atomic layer deposition has become a viable approach to synthesize functional materials for chip manufacturing. However, its counterpart, atomic layer etch, has not been fully developed.

The UCLA program is designed to reverse engineer the atomic layer deposition process, providing guidance for simulation of the atomic-layer etch. Such capability is projected by industry scientists to become increasingly important in order to achieve the patterning of complex and multi-layer thin-film structures.

For example, new composite or hybrid materials required for emerging memory and logic devices pose significant etch challenges that must be addressed by aggressive, yet highly selective, etch chemistries. Conversely, PFC replacement etches for TSVs, which enable 3D device integration, face a different set of challenges such as high aspect ratio and multiple interfaces. Both types of etching present difficult challenges, but also significant opportunities to enable higher density, performance and functional diversification in future ICs.

By screening potential surface reactions and applying thermodynamic and kinetics assessment to measure reaction, researchers are taking a unique approach to remove specific surface elements and design chemistries that will work better than PFCs. As a result, the model prediction provides a design of experiments that can be much more efficient and shorten the timeframe for discovery and confirmation of alternative chemicals.

“Atom by atom, this is the fastest and most affordable way to discover the best approaches for etching down to silicon and metal layers with a variety of chemicals for chipmaking,” said Farhang Shadman, Director of the SRC-funded ERC based at the University of Arizona.

Next Steps

According to the World Semiconductor Council, semiconductor manufacturers in the European Union, Japan, Korea, Taiwan and the United States voluntarily lowered PFC emissions by more than 30% between 1995 and 2010, surpassing the WSC goal to reduce emissions by 10%. UCLA predicts that its modeling approach will lead to further reductions in PFC emissions from semiconductor manufacturing, supporting the industry’s ongoing commitment to environmental protection.

An additional potential benefit of the UCLA atomic scale etch model is an improvement in throughput for chip production by identifying and confirming higher etch-rate processes.

“Needless to say, accelerating the pace of PFC replacement is an important priority for the semiconductor industry, and SRC member companies are working closely with Dr. Chang’s UCLA research team to provide both guidance and support in developing and verifying these new models,” said Bob Havemann, director of Nanomanufacturing Sciences at SRC. “This project provides an outstanding example of the vital ongoing research at the ERC, which is focused on developing ESH-preferable processes for current and future semiconductor manufacturing.”

Zvi Or-Bach, President & CEO of MonolithIC 3D Inc. and Benjamin S. Louie of Zeno Semiconductor blog about dimensional scaling as it relates to EUV and future per transistor device cost.

At the IEEE International Solid-State Circuit Conference, the issue of dimensional scaling as it relates to EUV and future per transistor device cost was an important topic in the plenary session. One important, and perhaps overlooked, aspect of the industry’s scaling issue relates to the future of the SRAM bit-cell within this framework of dimensional scaling. We would like to shine some light on this impending issue.

As widely reported in the industry and articulated by ASML’s Executive VP & CTO Martin van den Brink at ISSCC 2013, there is substantial evidence that without EUV the cost of logic transistors is most likely going up with scaling. One slide he used to illustrate this is below:

Source: ASML

The above slide arrived after Martin had presented another non-encouraging slide, showing the same view from three companies: a Broadcom chart of increasing cost per gate correlated with dimensional scaling, together with the now famous Nvidia chart of no more crossover of transistor cost below 28nm, and third a GlobalFoundries chart showing some limited value for EUV.

 

 

 

We may attribute Martin statements to ASML interest in promoting EUV, but since ASML has already received significant EUV participation from INTEL, Samsung and TSMC, it might indicate further bumps are on the road to bringing EUV to market. We don’t know if EUV will ever become real, but we do know very well that it is been delayed, and delayed again, and delayed again. It was made public recently that EUV has probably already missed the 10nm process node -“10nm will be optical,” said Ajit Manocha, chief executive of GlobalFoundries.

An even more interesting slide was presented by van den Brink:

This chart brings up an important aspect of dimensional scaling that has not been discussed much before – the scaling of the SRAM bit-cell.  According to this chart, the SRAM bit-cell size might not be reduced from the 20nm to 10 nm node, and might even get larger at 7nm as it may need more than 8 transistors. (Sound familiar? Fabs are doing the same with BEOL metallization scaling…little or none).

Modern logic devices demand a significant amount of embedded SRAM. In fact, more than 50% of the typical logic device area is allocated for these SRAM as illustrated by the following chart of Semico (June, 2010).

The dominant embedded SRAM bit-cell architecture has been the 6 transistor cell (6T). And for many years this very cell has been hand-crafted using special design rules independently developed by foundries for every new technology node. It makes sense: the SRAM cell is a unique structure that does not obey normal logic design rules as it drives output against output anytime a write cycle is being performed. In many cases it is the SRAM cell that is the most sensitive portion of the logic device to process parameter variations and this sensitivity greatly impacts end device yield.

It well known that scaling the SRAM bit-cell has become harder and harder. Some vendors have already moved away from the 6T bit-cell in preference to the 8T (eight transistors) bit-cell.  ISSCC 2013 had a significant number of papers that were presented using 8T SRAM.  The few papers who kept the 6T SRAM embedded in their logic devices were forced to add read/write support circuits and additional overhead to enable the 6T bit-cell to function reliably.

Since SRAM bit scaling is now not able to keep up with logic scaling, the overall end device cost scaling could be even more disappointing than the transistor or gate cost illustrations above. 

Of course, well aware of this trend, IBM has been promoting their embedded DRAM solution for years. In the recent Common Platform Forum Dr. Gary Patton, VP, IBM Semiconductor R& D Center, was very pleased to share that in their 32nm product line the use of the embedded DRAM has given IBM the equivalent of a process node scaling benefit. Yet, as of now, most other vendors have not adopted eDRAM due to the process complexity and cost it adds to the logic process. It fair to assume that the appetite for eDRAM will not grow with dimensional scaling as the DRAM capacitor will be very hard to scale, the extra power for supporting DRAM will not be available and the cost of advance process development to add in extra complexity will be too high.

Accordingly we can learn from the recent ISSCC that dimensional scaling is facing the cost challenges we were aware of before in addition to new challenges that we might not have been aware of: the cost and the active/passive power handicaps due to the incompatibility of the 6T SRAM  bit-cell with scaling.

As we have suggested before, now that monolithic 3D is practical, we could advance and maintain Moore’s Law by augmenting dimensional scaling with 3D IC scaling. We could enjoy depreciated equipment charges for more years and much lower R&D engineering outlays that would bring down production and development costs, and also enjoy improvements to power and performance.

Another exciting option is to replace the 6T SRAM bit-cell with the 1T bi-stable floating body memory cell invented by Zeno Semiconductor.  The Zeno bit-cell provides two stable states, analogous to an SRAM while only consuming ~20% area of a traditional 6T SRAM and requires considerably less power.  The area and power savings over a traditional 6T SRAM improve further with scaling.  Most excitingly the Zeno bit-cell is compatible with existing logic processes. 

About the authors

Zvi Or-Bach is a well-known serial entrepreneur. He founded eASIC in 1999 and served as the company’s CEO for six years. eASIC was funded by leading investors Vinod Khosla and KPCB in three successive rounds. Or-Bach also founded Chip Express in 1989 (recently acquired by Gigoptix) and served as the company’s President and CEO for almost 10 years. In 2009 he founded and incorporated MonolithIC 3D Inc., a company that developed and patented a technology breakthrough for practical monolithic 3D-ICs.

Benjamin S. Louie has more than 16 years of experience in memory design including NOR Flash, NAND Flash and MRAM.  Most recently he led design efforts at Magsil, an MRAM IP company.  Prior to Magsil, Ben worked as a Design Manger at Micron Technology where he led the design development of Micron’s NAND program. 

Most electronic systems that power our digital life are inflexible and flat. Rigid electronic designs work for our computers and phones but not for our bodies. Humans are soft and curved. Electronic systems capable of bending, twisting, and stretching have great potential for applications in which conventional, stiff semiconductor microelectronics would not suffice. One promising area for conformable electronics is in biomedical applications such as wearable and implantable electronic systems. Design for Reliability of Multi-Layer Thin Film Stretchable Interconnects, to be presented at the Electronic Components and Technology Conference on May 28 – 31, 2013, discusses the use of stretchable interconnects (Figure 1) and the future shape of conformable electronics.

multiple layers of stretchable interconnects
Figure 1. Multiple layers of stretchable interconnects crossing at the strain relief structure described below.

Previous stretchable interconnect designs are composed of only a single metal layer. Due to the nature of this single metal layer design, these stretchable electronic systems have large, sparse layouts. However, as the system gets more complex, single metal layer interconnects become impractical. Multi-layered stretchable interconnects allow for smaller, more intricate, and more practical systems and can be produced through conventional bottom-up micro-fabrication processes. When multiple meandering interconnects intersect, however, the junctions of the interconnects are subject to the specific orientation of each structure, complicating the design, risking the integrity of the small junction areas, and resulting in complex mechanics during stretching.

A circular structure to relieve strain at the junctions between multiple metal interconnect layers is proposed in the paper. In the proposed strain relief structure design (Figure 2), meandering horseshoe patterned metal interconnects contain circular rings that are stacked to allow the interconnects to overlap one another.  While the proposed strain relief structure is a universal design that can be applied to any number of systems with multiple interconnecting layers, structures composed of two metal layers are examined in this study.

strain relief structure design
Figure 2. Strain relief structure design with two layered intersecting interconnects.

A comprehensive investigation into the deformation behavior and failure mechanisms of the structures was carried out through both numerical and experimental analysis. Numerical analysis indicates that elongations of up to 20% cause no plastic strain in the structure, allowing it to operate indefinitely. Simulations show that the crests of the horseshoe interconnects are the regions with the greatest strain and that the structure will ultimately fail at one of these crests (Figure 3).

simulated strain distribution
Figure 3. Right: Structure imaged during testing. Left: Simulated strain distribution.

Results of electromechanical testing show that the strain relief structure can stretch up to 285% of its initial length prior to failure. Initial results from fatigue life testing of the structures has demonstrated that they are able to withstand more than one million cycles of 100% elongation at a 200% per second strain rate. Fatigue life testing also verified the numerical simulations, indicating that the strain relief structure effectively dissipates strain from the interconnect junctions to the crests of the horseshoes. Both the simulation and experimental results show that this multi-layer strain relief structure for stretchable electronic systems is a durable and highly promising design with significant implications for the future of conformable electronics.

Jim Feldhan

The semiconductor industry has broken the $300 billion mark. One of the major driving forces in the foundry and overall semiconductor market is the end applications. Solid State Technology is excited to have Jim Feldhan, President of Semico Research, present data and analysis from Semico’s MAP model, which provides insight into semiconductor revenues, units and wafer demand by computing, communications and consumer end markets. The data indicates that all the growth is not necessarily occurring in the advanced technology high performance processor or memory arenas.

“Innovation has created specialized applications leading to growth in product segments such as power management, MEMs sensors and RF markets,” Feldhan writes in his abstract.

Jim will address the changes that are occurring and what is needed to support future growth on June 24, 2013 at The ConFab in Las Vegas.

Jim Feldhan founded Semico Research in 1994. A 20-year veteran of the semiconductor industry, he brings his management, forecasting and modeling expertise to Semico, along with a reputation of quality research. Feldhan designed and developed the research methodologies and report structures, which are the basis for Semico’s Custom Research and Portfolio Services. Feldhan also develops Semico’s overall economic outlook as well as performing various semiconductor consulting and forecasting. With a focus on quality, Semico Research has grown to the largest semiconductor-focused consulting and research firm.

For learn more or to register for The ConFab, visit The ConFab section of our website.

Brion Technologies, a division of ASML, announced a major milestone today in its partnership with GLOBALFOUNDRIES. The companies are collaborating to deliver high-volume computational lithography capabilities for 28 nm and 20 nm tapeouts, while also accelerating the development of future nodes, including extreme ultraviolet (EUV) lithography.

In integrated circuits design, tape-out or tapeout is the final part of the design cycle before a photomask is manufactured. In its current practice (also known as ‘mask data preparation’ or MDP) chip makers perform checks and make modifications to the mask design specific to the manufacturing process. Optical proximity correction (OPC) is the most common example, which corrects for the diffraction and interference behavior of light when printing the sub-micron scale features of modern integrated circuit designs.

The process window is very challenging for leading edge technologies and substantially impacts yield, time to market and ultimately profitability. ASML’s holistic lithography approach enables both process window enhancement and process window control from design to mask tapeout to chip manufacturing by leveraging the computational model accuracy that comes from tight integration with the ASML scanners including FlexRayTM and FlexWaveTM.

GLOBALFOUNDRIES is working with Brion to ensure that their foundry customers have the best possible and most cost effective semiconductor manufacturing capability available. Critical to achieving this is the use of Tachyon FlexTM, which is the platform architecture that allows the Tachyon applications to run on a customer’s existing compute cluster, distributed across many thousands of CPU cores. Tachyon Flex has been demonstrated to have efficiency (or scalability) significantly better than other industry competitors, resulting in substantial time and cost savings for large tapeouts.

"At 28nm and below it is necessary to explore and realize every possible process window improvement to achieve a manufacturable patterning solution," said Chris Spence, Senior Fellow of GLOBALFOUNDRIES. "We have found that Brion’s OPC and Computational Lithography solutions enable us to achieve this goal and ensure the best possible yield for GLOBALFOUNDRIES’ customers."

Jim Koonmen, general manager of Brion Technologies said, "We look forward to this important expansion of our long-standing relationship with GLOBALFOUNDRIES, and to the successful use by GLOBALFOUNDRIES of these leading edge technologies at the N28, N20, N14 and future nodes."

surface metrology

PI miCos announced the release of a new 2-axis precision linear translation stage. The new MCS XY precision linear stage was designed for industrial precision motion control and surface metrology applications and combines robustness and high accuracy.

This precision motorized XY positioner handles loads of up to 20 kg and offers resolution down to 0.005 µm over a travel range of four inches, based on an interferometric linear encoder. An option with 0.001 µm resolution is also available. A precision machined base and high accuracy bearings provide straightness/flatness of two microns. Despite the high accuracy, the translation stage was designed for industrial robustness. Transmitted light applications benefit from the large clear aperture of 150x150mm.

Very Wide Velocity Range

The stage can achieve velocities from as low as one µm/second all the up to 200 mm/second (eight inches/second). Several PI miCos motion controllers are available.

Motor and Sensor Options

Several motor and sensor options are offered. For applications where closed-loop operation is not required, lower-cost open-loop stepper motors are recommended. Several closed-loop versions are available for higher performance demands: stepper motors, DC servo motors and direct-drive electromagnetic noncontact linear motors.

For high speed operation the direct-drive linear motors are recommended. Extremely smooth motion, with constant velocity at the low end down to single digit microns/second is achieved with PI miCos stepper motors SMC Hydra motion controllers.

Multi-Axis Options

The MCS XY precision linear translation stage can be combined with linear vertical positioners, rotary positioners and goniometers from PI miCos.

Vacuum Positioners

PI miCos specializes in vacuum compatible positioning systems from 10-3 to 10-10 Torr. Basically all of our linear and rotary stages can also be ordered for vacuum use.

The 24th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2013) will be held May 13-16 in Saratoga Springs, New York. The conference will feature more than 85 presentations including peer-reviewed manuscripts covering critical process technologies and fab productivity, workshops, and tutorials. This year’s event features a panel discussion on the process and economic challenges of the move to 450mm and 15 technical sessions on advanced semiconductor manufacturing, as well as tutorials on computational lithography by Intel Corporation and 3D-ICs by GLOBALFOUNDRIES.

ASMC has been held annually for over two decades, where industry professionals come together to learn and share knowledge on new and “best practice” semiconductor manufacturing issues and concepts. The conference seeks to provide a valuable source of cost-effective, hands-on solutions to address real-world manufacturing challenges.

ASMC will also hold an interactive poster session and reception, to provide opportunities for networking between authors and conference attendees. During this session, participants can engage authors in in-depth discussion of a wide range of issues.   New this year is a co-located workshop on May 13 on manufacturing below the 10nm node.

 ASMC 2013 is presented by SEMI with technical sponsors: Institute of Electrical & Electronics Engineers (IEEE), IEEE Electron Devices Society (EDS), and IEEE Components, Packaging and Manufacturing Technology Society (CPMT).  Corporate sponsors include: Applied Materials, ASML, ATMI, ChemTrace, CNW Courier Network, DAS, Edwards, KLA-Tencor, GLOBALFOUNDRIES, Marcy NanoCenter at SUNYIT, MSP, NY Loves Nanotech, and Valqua.

SEMI is the global industry association serving the nano- and microelectronics manufacturing supply chains. SEMI maintains offices in Bangalore, Beijing, Berlin, Brussels, Grenoble, Hsinchu, Moscow, San Jose, Seoul, Shanghai, Singapore, Tokyo, and Washington, D.C.

Wafers with a diameter of 450mm enable the micro-chip industry an increase in yield of up to 80%. This leads to an enormous increase in productivity. In order to control the product quality, these wafers receive a specific marking from the manufacturer.

Promptly at the start of the year, InnoLas Semiconductor GmbH has successfully installed a second 450mm system. As an optional bridge-tool variant the system can mark 450mm and 300mm wafers on either side. The system checks the result automatically and thus reduces the process operations significantly. According to requirements the customer can choose between vacuum handling and edge-grip handling. The latter transports the wafers especially carefully and cleanly.

The company places particular emphasis on in-house developments and products in the application of high-precision components. Together with the robust further development of proven engineering this takes care of the constant high quality standard in marking and handling processes, also for the new wafer sizes.

 “The marking and handling quality will be maintained at our high level for the new wafer sizes. To achieve this we use components developed in-house whenever the requirements are of high precision. These are otherwise not available in suitable quality as required by us and our customers,” Andreas Behr, general manager of the InnoLas Semiconductor GmbH, explains the consistently high standard achieved by his wafer marking systems.

450mm wafer laser marking system