Category Archives: Semiconductors

brooks instruments mass flow controllerBrooks Instrument, a provider of flow measurement and control instrumentation to the microelectronics industry, will launch the GF135 pressure transient insensitive (PTI) mass flow controller at SEMICON China, March 19-21 at Shanghai New International Expo Center. In its first year at SEMICON China, Brooks will showcase the GF135 and its high-performance digital solutions for flow, vacuum and pressure measurement with partner SCH Electronics at booth 5505.

The GF135 improves yield and uptime with real-time integral rate-of-decay flow measurement and advanced diagnostic capabilities to verify accuracy, check valve leak-by and monitor sensor drift without stopping production. It provides market-leading actual process gas accuracy and ultra-fast flow settling time for reduced process cycle time. Onboard diagnostic data logging, zero stability trending and correction, and early detection of valve corrosion or clogging allow semiconductor manufacturers to achieve tighter tolerances and maintain uniformity in etch profiles and critical dimensions. The combination of these features allows the GF135 to deliver accuracy and cost savings to the semiconductor industry.

Additionally, Brooks will demo its GF81 mass flow controller, the new high-flow version of the GF80. The GF81 is the mass flow controller of choice for process engineers in solar, coatings and industrial thin-film applications. The GF81 offers flow rates up to 300 slpm, as well as a high-purity flow path. Unlike other high-flow mass flow controllers, it has a smaller footprint and offers the broadest range of communication protocols.

Based in Pennsylvania, Brooks Instrument is a multi-technology instrumentation company serving a range of markets. Brooks also owns Key Instruments, which offers precision machined acrylic flow meters, molded plastic flow meters, glass tube flow meters, and flow control valves. The company has manufacturing locations, sales, and service offices in the Americas, Europe, and Asia.

A researcher from North Carolina State University has developed a technique for creating high-density ceramic materials that requires far lower temperatures than current techniques – and takes less than a second, as opposed to hours. Ceramics are used in a wide variety of technologies, including body armor, fuel cells, spark plugs, nuclear rods and superconductors.

At issue is a process known as “sintering,” which is when ceramic powders, such as zirconia, are compressed into a desired shape and exposed to high heat until the powder particles are bound together into a solid, but slightly porous, material. But new research from Dr. Jay Narayan, John C. Fan Distinguished Chair Professor of Materials Science and Engineering at NC State, may revolutionize the sintering process.

Narayan’s new technique, selective-melt sintering, allows sintering of yttria-stabilized zirconia at 800 degrees Celsius (C) – instead of the conventional 1450 C. In addition, using the selective-melt sintering technique, it is possible to sinter zirconia at 800 C in less than a second, and create a material with no porosity at all. In contrast, traditional sintering techniques take four to five hours at 1450 C.

“This technique allows you to achieve ‘theoretical density,’ meaning it eliminates all of the porosity in the material,” Narayan says. “This increases the strength of the ceramic, as well as improving its optical, magnetic and other properties.”

The key to Narayan’s approach is the application of an electric field, at approximately 100 volts per centimeter, to the material. When this field is applied, it creates subtle changes in the material’s grain boundaries – where atoms from different crystals meet in the material. Namely, the field draws defects to the grain boundary. These defects consist of vacancies (missing atoms) which can carry charges. The defects are negatively charged and draw current from the electric field to the area – which raises the temperature along the grain boundary.

Raising the temperature along the grain boundary means that the material can be sintered at a much lower temperature, because sintering is done by selectively melting the grain boundaries to fuse the crystals together.

Normally you would have to apply enough heat to raise the mass of all the material to the melting point, even though you only need to melt the grain boundary. Pre-heating the grain boundary with an electric field is what allowed Narayan to lower the sintering temperature from 1450 C to 800 C and sinter the material much more quickly.

The work is described in two papers published online this month in Scripta Materialia. The papers are Grain growth model for electric field-assisted processing and flash sintering of materials, and an invited viewpoint paper, New mechanism for field-assisted processing and flash sintering of materials. Narayan is the sole author.

 

Mentor Graphics Corp. (NASDAQ: MENT) today announced availability of the Kronos Cell Characterization and Analysis platform. The Kronos platform quickly produces accurate performance models for standard cells, I/Os, and complex cells within an advanced, integrated environment. Without correctly characterized libraries, an entire design project may be at risk, and designing at the wrong environmental corner or not taking advantage of a special operating voltage may lead to slower, larger designs that waste power or take longer to close on timing.

Accurate Models

At 45nm and below, speed and power consumption are much more sensitive to environmental conditions including voltage and noise. Therefore, producing accurate models at the appropriate conditions is critical to achieving design success. The Kronos platform quickly generates accurate and complete timing/power models and incorporates unique methods for noise immunity and signal integrity to avoid design problems that otherwise might not be detected until failure analysis.

High Throughput

The Kronos Platform’s advanced algorithms and efficient job distribution reduces characterization time from weeks to days. During characterization, SPICE simulations are continuously monitored, and numerous data checks and recovery mechanisms significantly improve turn-around time by pinpointing specific model results and simulations if a problem is detected.

Kronos Characterizer

Kronos Characterizer is a high-throughput, general purpose cell library characterization tool for standard cells, complex cells, IO pad, and custom macros. The Kronos platform features high-performance integration with the best-in-class Eldo Classic SPICE simulator. Eldo Classic has been extensively optimized for cell characterization, offering quick simulation turnarounds and the industry’s most accurate results. The tight integration of Kronos Characterizer with Eldo Classic delivers improved performance for shorter total characterization time through dedicated features in the Eldo simulator that support library characterization.

Kronos Analyzer

Kronos Analyzer is a library analysis and verification tool for ensuring high quality libraries whether qualifying libraries from an external supplier or developing library models internally. The tool enables design engineers and library qualification teams to compare and validate complex ASIC cell libraries for design-critical characteristics such as performance, area, and power. Kronos Analyzer can be used with any cell characterization solution for library validation and optimization.

“Our customers know that sophisticated and robust Standard Cell Library analysis and characterization are of critical importance,” said Robert Hum, vice president and general manager, Deep Submicron Division (DSM), Mentor Graphics. “Our SPICE simulator, Eldo, has been optimized for cell characterization and used to drive this type of solution for many years. Now we have the opportunity to deeply integrate Eldo into a best-in-class characterization technology for optimal accuracy and performance.”

 

Intel announced Monday a major move to expand its foundry business. Altera Corporation and Intel Corporation have entered into an agreement for the future manufacture of Altera FPGAs on Intel’s 14nm tri-gate transistor technology. These next-generation products, which target ultra high-performance systems for military, wireline communications, cloud networking, and compute and storage applications, will enable breakthrough levels of performance and power efficiencies not otherwise possible.

"Altera’s FPGAs using Intel 14nm technology will enable customers to design with the most advanced, highest-performing FPGAs in the industry," said John Daane, president, CEO and chairman of Altera. "In addition, Altera gains a tremendous competitive advantage at the high end in that we are the only major FPGA company with access to this technology."

Intel promised Altera access to the 14nm process for 12 years to satisfy long-term availability requirements of defense and other customers, Daane said. The agreement will allow Altera the use of other nodes, but Altea will focus on high-end parts at 14nm initially. Intel has yet to disclose the details about its 14nm tri-gate technology.

Daane told Reuters he believes Intel’s manufacturing technology will give Altera’s chips a several-year advantage against Xilinx, Altera’s main competitor.

While Intel has built manufactured chips in collaboration with other companies in the past, this particular announcement with Altera is a significant step in the unfolding timeline of its 14nm technology.

"They’ve crossed over the line from it just being a questionable experiment to – we’re going to do this for tier-1 customers," said RBC analyst Doug Freedman to Reuters.

Daane said he believes Intel is two to four years ahead of other foundries with its 14nm FinFET process, which Altera plans to use to on its highest-end FPGAs, giving them advantages in power, performance and density.

"We are essentially getting access like an extra division of Intel. As soon as they’re making the technology available to their various groups to do design work, we’re getting the same," Daane said.

Altera’s next-generation products will now include 14nm, in addition to previously announced 20nm technologies, extending the company’s tailored product portfolio that meets myriad customer needs for performance, bandwidth and power efficiency across diverse end applications.

"It’s a step in terms of building into a business level we wish to achieve," Sunit Rikhi, Vice President and General Manager of Intel custom foundry, told Reuters on Monday. "There’s no doubt in my mind the foundry will be a significant player in the future."

Altera still plans to use TSMC as its primary foundry, which will continue to supply its current processes and fulfill Altera’s product portfolio.

The global market in Key Enabling Technologies (KET) is forecast to grow from about 650 billion euro in 2008 to over one trillion euro in 2015. In response to this growth, top professionals in fields utilizing KETs have formed an expert group to assist the European Commission in the implementation of the strategy to boost the industrial production of KETs-based products in Europe. Today marks the inaugural meeting of the European Commission Key Enabling Technologies (KET) High Level Commission expert group, including professionals in automotive, communication, aeronautics, defence, medical and energy fields.

Representing the European photonics industry, EPIC President Drew Nelson, CEO and President of epitaxial wafer supplier IQE, has been appointed as a member of the new High Level Group as technology representative for the Photonics KET. EPIC is the European Photonics Industry Consortium, a membership-led not-for-profit industry association that promotes the sustainable development of organisations working in the field of photonics.

“I will be a vigorous supporter and promoter of KETs at regional, national, and European level and take every opportunity to help design and implement policies to help the competitiveness of Europe through the rapid deployment of KETs” Drew Nelson stated, “I expect from the KET high level group that it is able to persuade the European Commission through evidence based examples and debate to adapt EU policies throughout each directorate general that fully support KETs implementation throughout Europe.”

The expert group advises the European Commission on KETs related policy issues, follows up the implementation of the European strategy for KETs adopted by the European Commission on June 26, 2012, and promotes the development of KETs policies by the Member States.

“KETs offer a fantastic opportunity for all of Europe; we must explore and embrace its potential. Especially in Photonics, there are many opportunities ahead of us,” said Carlos Lee, director general of EPIC. Lee is a member of the working group on “Promotion and Implementation of KETs Policies at National and Regional Level.”

The group aims to foster the industrial deployment of European KETs in order to keep pace with main international competitors, restore growth, create jobs and help address today’s major societal challenges.

The group was inaugurated by European Commissioners Antonio Tajani from DG Enterprise, Máire Geoghegan-Quinn from DG Research, and Johannes Hahn from DG Regio. Drew Nelson, President of EPIC, represents the photonics industry.

 

New automotive technologies that go beyond touchscreens, satellite radio, and voice-activated GPS commands are being tested and improved, and will soon begin to appear in many more new car models, resulting in solid growth for the automotive IC market through 2016, according to the 2013 edition of IC Insights’ IC Market Drivers—A Study of Emerging and Major End-Use Applications Fueling Demand for Integrated Circuits.

Military-like night-vision systems that quickly identify pedestrians, animals or road hazards in low-light conditions; airbags stowed in shoulder harnesses of seatbelts; and the ability for drivers to customize the look of their dashboard instrument panels are examples of systems that are available in a select number of cars now, but will soon become available in many more vehicles. Along with backup cameras, electronic stability control, active-cruise control, and several other systems covered in the IC Market Drivers report, emerging electronic systems are forecast to help the automotive IC market grow 52% from $18.2 billion in 2012 to $27.7 billion in 2016. This growth translates to an average annual increase of 11% for the automotive IC market.

Analog ICs and MCUs are forecast to benefit most from the increasing electronic content within automobiles.  According to the IC Market Drivers report, analog ICs accounted for 41% of the 2012 automotive IC market (Figure 2).  Analog ICs are used in “traditional” applications such as to gauge input functions like speed measurement and for output functions like opening and closing power windows and adjusting power seats.  One of the newer applications for analog ICs in cars is LED lighting.  Depending on the application, LED drivers and various converters are used to supply constant current despite variations in battery voltage.

Microcontrollers accounted for 36% of the automotive IC market in 2012.  16-bit applications in chassis and safety applications (lane-detection warning, hands-free telematics, etc.) are increasing, but enhanced 8-bit and low-end 32-bit MCUs are competing for many of the same sockets as 16-bit controllers.  Applications like anti-skid braking and airbag systems are solidly 16-bit now, but are transitioning to larger bit widths.  Electronic parking assist could be a new sweet spot for 16-bit MCUs. These systems typically use two to four (but as many as eight) ultrasonic sensors to detect objects near the vehicle.  Processing the additional information drives the requirements into the domain of 16-bit devices.

The 32-bit chips are incorporated into powertrains to handle functions such as electronic throttle control, cylinder deactivation, variable valve timing, and fuel injection, and in next-generation chassis and safety systems including active high-end electronic stability control, complex smart airbag systems, and more.  In addition, 32-bit MCUs are used to process sophisticated, real-time sensor functions within safety and crash-avoidance systems.

Gesture recognition is a growing trend that is being incorporated both inside and outside the car. 32-bit MCUs are at the core of many emerging gesture-recognition systems and in many ways, they are an extension of gesture-recognition technology found onboard in game controllers.

Though the automotive market represents only about 7% of total IC sales, increasing electronic system content in motor vehicles is forecast to result in this segment being one of the fasting-growing end-use categories through 2016.

 

 

Transphorm Inc. today announced at the 2013 ARPA-E Energy Innovation Summit that its novel 600V Gallium Nitride (GaN) module has enabled the world’s first GaN-based high power converter. Transphorm will demonstrate the product built with its customer-partner Yaskawa Electric, Japan at the upcoming APEC 2013 industry conference. The announcement underscores the significant technical and commercial progress that Transphorm has made since being awarded ARPA-E funding in 2011 to reduce the vast amount of electric power waste globally.

Yaskawa’s product, a 4.5kW PV power conditioner, is powered by Transphorm’s 600V GaN half-bridge modules, which have enabled it to achieve several industry firsts:

1. The first high power converter product in the world utilizing GaN technology

2. The first efficient PV power conditioner to operate at 50KHz

3. Simultaneous achievement of a 40% reduction in inverter size and 98% efficiency operation, a form and function benefit uniquely enabled by Transphorm’s EZ-GaN module technology

Transphorm’s patented, high-performance EZ-GaN module technology, combines low switching and conduction losses offering reduced energy loss of over 50% compared to conventional silicon based power conversion designs while simultaneously operating at higher frequency.

“The partnership between Yaskawa, the world leader in inverter solutions, and Transphorm, the world leader in GaN-based power conversion, has produced the world’s first high power GaN power converter,” said Umesh Mishra, CEO of Transphorm. “This is a disruptive first step which signals the broad adoption of GaN-based power conversion solutions.”

“By teaming with Transphorm, Yaskawa is again the technology leader in introducing new technologies into the market place with tremendous benefits to customers and society” said Tatsuya Yamada , General Manager Environment & Energy Business Div. Drives Division of Yaskawa Electric.

Transphorm’s efficient, compact, and easy-to-embed solutions simplify the design and manufacturing of a wide variety of electrical systems and devices, including power supplies and adapters, PV Inverters for solar panels, motor drives and power conversion for electric vehicles.  Transphorm’s proprietary EZ- GaN platform can reduce power system size, increase energy density and deliver high efficiencies across the grid. 

 

LFoundry, an analog mixed signal and specialized technologies foundry, today announced that it has entered into an agreement with Micron Technology, Inc. (NASDAQ: MU) to acquire Micron Technology Italia, Srl. and all of its semiconductor fabrication facility assets in Avezzano, Italy. Micron’s Fab in Italy is expected to become a strategic part of LFoundry’s global growth.

After this acquisition, LFoundry will employ approximately 2,400 people worldwide and will have a wafer start capacity of 65,000 200mm wafers per month, which will allow LFoundry to expand its market presence as the leading analog mixed signal foundry in Europe.

“Operating out of two most advanced European 200mm Fabs, supporting 90nm, a volume copper path and state of the art technology perfectly positions LFoundry to provide flexible and high quality technology and manufacturing services,” said Günther Ernst, CEO of LFoundry. “Combined with our greatly expanded R&D and engineering teams, our customers will have access to a strong partner for specialized technologies and collaborative development, ensuring smooth industrialization from lab to fab, either based on LFoundry’s CMOS or on proprietary technologies.”

Ernst added that the combination of the manufacturing capacity and the technology capabilities of Micron’s Fab in Avezzano with LFoundry’s existing Fab in Rousset, France, is consistent with their development vision for the company.

“We have successfully attained a strategic position in several value added markets in Europe, such as digital security, imaging and power management,” said Ernst. “With the new Fab in Avezzano, we will surpass an important threshold, enabling us to accelerate further growth of our business outside of Europe.”

Ernst believes that this move will allow the company to begin to gain a foothold in U.S. and APAC markets.

DFM Services in the Cloud


February 27, 2013

DFM Services in the CloudJoe Kwan is the Product Marketing Manager for Calibre LFD and DFM Services at Mentor Graphics. He is also responsible for the management of Mentor’s Foundry Programs. He previously worked at VLSI Technology, COMPASS Design Automation, and Virtual Silicon. Joe received a BA in Computer Science from the University of California Berkeley and an MS in Electrical Engineering from Stanford University.

When to Farm Out Your DFM Signoff

The DFM requirements at advanced process nodes pose not only technical challenges to design teams, but also call for new business approaches. At 40nm, 28nm, and 20nm, foundries require designers to perform lithography checking and litho hotspot fixing before tapeout. In the past, DFM signoff has almost always been done in-house. But, particularly for designers who are taping out relatively few devices, the better path may be to hire a qualified external team to perform some or all of your DFM signoff as a service.

 DRC and DFM have changed pretty dramatically over the past few years. At advanced nodes, you need to be more than just “DRC-clean” to guarantee good yield. Even after passing rule-based DRC, designs can still have yield detracting issues that lead to parametric performance variability and even functional failure. At the root of the problem is the distortion of those nice rectilinear shapes on your drawn layout when you print them with photolithographic techniques. Depending on your layout patterns and their nearby structures, the actual geometries on silicon may exhibit pinching (open), bridging (short) or line-end pull-back (see Figure 1).

SEM images of pinching and bridging, 40nm, 28nm and 20nm process nodes
Figure 1: SEM images of pinching and bridging. LPC finds these problems and lets you fix them before tapeout. Litho checking is mandatory at TSMC for 40nm, 28nm and 20nm process nodes.

In the past, these problems were fixed by applying optical proximity correction (OPC) after tapeout, often at the fab. But at 40nm and below, the alterations to the layout must be done in the full design context, i.e. before tapeout, which means that the major foundries now require IC designers to find and fix all Level 1 hotspots. TSMC’s terminology for this is Litho Process Check, LPC.

Usually, design companies purchase the DFM software licenses and run litho checking in-house. This approach has the obvious benefits of software ownership. Designers have full control over when and how frequently they run the checks. The design database doesn’t leave the company’s network. There is a tight loop between updating the design database and re-running verification.

But what if you have not yet set up your own LPC checking flow and need time to plan or budget for software and CPU resources? Or, if you only have a few tapeouts a year? In these cases, you would benefit from the flexibility and convenience of outsourcing the LPC check.

A DFM analysis service is an alternative option to software purchase by performing litho checking for you. Here’s how it works: the design house delivers the encrypted design database to a secure electronic drop box. The analysis service then runs TSMC-certified signoff—for example, Calibre LFD—in a secure data center. Your DFM analysis service should demonstrate that they have an advanced security infrastructure that can isolate and secure you IP. Access should be limited to only those employees that need to handle the data. You would get the litho results back, along with potential guides for fixing the reported hotspots. A cloud-based DFM analysis service for TSMC’s 40nm, 28nm, and 20nm process nodes is available from Mentor Graphics.

A DFM service can also be useful when you already have Calibre LFD licenses, but find yourself with over-utilized computing resources. Having a DFM service option gives you flexibility in getting through a tight CPU resource situation or can ease a critical path in your tape-out schedule. The DMF service can run the LPC while you perform the remaining design and verification tasks in parallel.

Whether you use a DFM services or run LPC in-house on purchased software, it is very important to run litho checking early and often. This lets you identify problematic structures early and allows more time to make the necessary fixes. But now you have more flexibility to make the right business decision regarding how to reach DFM signoff.

Connecting the (quantum) dots


February 26, 2013

Recent research offers a new spin on using nanoscale semiconductor structures to build faster computers and electronics. Literally.

University of Pittsburgh and Delft University of Technology researchers reveal in the Feb. 17 online issue of Nature Nanotechnology a new method that better preserves the units necessary to power lightning-fast electronics, known as qubits. Hole spins, rather than electron spins, can keep quantum bits in the same physical state up to 10 times longer than before, the report finds.

"Previously, our group and others have used electron spins, but the problem was that they interacted with spins of nuclei, and therefore it was difficult to preserve the alignment and control of electron spins," said Sergey Frolov, assistant professor in the Department of Physics and Astronomy within Pitt’s Kenneth P. Dietrich School of Arts and Sciences, who did the work as a postdoctoral fellow at Delft University of Technology in the Netherlands.

Whereas normal computing bits hold mathematical values of zero or one, quantum bits live in a hazy superposition of both states. It is this quality, said Frolov, which allows them to perform multiple calculations at once, offering exponential speed over classical computers. However, maintaining the qubit’s state long enough to perform computation remains a long-standing challenge for physicists.

"To create a viable quantum computer, the demonstration of long-lived quantum bits, or qubits, is necessary," said Frolov. "With our work, we have gotten one step closer."

The holes within hole spins, Frolov explained, are literally empty spaces left when electrons are taken out. Using extremely thin filaments called InSb (indium antimonide) nanowires, the researchers created a transistor-like device that could transform the electrons into holes. They then precisely placed one hole in a nanoscale box called "a quantum dot" and controlled the spin of that hole using electric fields. This approach— featuring nanoscale size and a higher density of devices on an electronic chip—is far more advantageous than magnetic control, which has been typically employed until now, said Frolov.

"Our research shows that holes, or empty spaces, can make better spin qubits than electrons for future quantum computers."

"Spins are the smallest magnets in our universe. Our vision for a quantum computer is to connect thousands of spins, and now we know how to control a single spin," said Frolov. "In the future, we’d like to scale up this concept to include multiple qubits."