Category Archives: Semiconductors

Leti to coordinate European supply chain in silicon photonicsCEA-Leti today announced that it will coordinate a four-year project aimed at building a European-based supply chain in silicon photonics and speeding industrialization of the technology.

The PLAT4M (Photonic Libraries And Technology for Manufacturing) project will focus on bringing the existing silicon photonics research platform to a level that enables seamless transition to industry, suitable for different application fields and levels of production volume.

PLAT4M, which is funded by a European Commission grant of 10.2 million euros, includes 15 leading European research and development institutes and CMOS companies, key industrial and research organizations in design and packaging, as well as end users in different application fields to build the complete supply chain.

“Silicon with its mature integration platform has brought electronic circuits to mass-market applications – our vision is that silicon photonics will follow this evolution,” said Laurent Fulbert, Integrated Photonics Program Manager at CEA-Leti, coordinator of PLAT4M. “Upgrading existing platforms to become compatible with industrialization is now essential and this requires streamlining and stabilizing the design and process flows by taking into account design robustness, process variability and integration constraints. The PLAT4M partners bring a combination of expertise to the challenge of building a complete supply chain for commercializing silicon photonics in Europe.”

A surge in output of silicon photonics research in recent years has significantly boosted the potential for commercial exploitation of the technology. However, most of this R&D has been devoted to developing elementary building blocks, rather than fabricating complete photonic integrated circuits, which are needed to support large potential markets.

 The PLAT4M consortium will make technologies and tools mature by building a coherent design flow, demonstrating manufacturability of elementary devices and process integration and developing a packaging toolkit. The project will validate the complete supply chain through application-driven test vehicles representing various application fields, such as telecom and datacom, gas sensing and light detection and ranging (LiDAR) and vibrometry. It also will focus on preparing the next-generation platform by setting up a roadmap for performance evolution and assessing scalability to high-volume production.

The supply chain will be based on technology platforms of Leti, imec and STMicroelectronics, supported by a unified design environment.

 The multiple benefits of PLAT4M for the European photonic industry will include:

  • Preparing the supply chain for silicon photonics technology, from chip-level technology to packaged circuits
  • Making integration technologies accessible to a broad circle of users in a fabless model
  • Contributing to the development of a design environment that facilitates photonics/electronics convergence
  • Moving the emphasis from the component to the architecture, and thus concentrate efforts on new products or new functionalities rather than the technology level
  • Aggregating competencies in photonics/electronics design and fabrication, and
  • Retaining the key added value in components in Europe through optoelectronic integration, with little added value in offshore assembly

PLAT4M Consortium Members

The consortium consists of technology providers, research institutes, end users and SMEs with excellent track records in advanced photonics technologies. At the design and process level, CEA and imec have been the most prominent European players in silicon photonics for a decade. Together with University of Paris-Sud, III-V Lab and TNO, they have demonstrated numerous scientific and technological breakthroughs.

For building a complete design flow, Mentor Graphics, PhoeniX BV and Si2 are world leaders in EDA tools and will work together to develop a common reference platform.

STMicroelectronics (France and Italy) brings its experience in microelectronics, and it has been engaged for the past year in the development of silicon photonics at the industrial level. Tyndall-UCC and Aifotec are renowned experts in the field of optoelectronic packaging and will work together on the implementation of packaging technologies developed within PLAT4M in a manufacturing environment.

End-users like Polytec, Thales Research & Technology and NXP will drive the demonstrators development and assess the use of silicon photonics in their applications fields.

SEMATECH today announced that Poongsan, a producer of annealing furnaces, has joined its Front End Processes (FEP) program, and will work with SEMATECH to explore high-pressure anneal (HPA) techniques for silicon and non-silicon channel materials to improve device performance and reliability for next-generation technologies.

Today, the solid-state device community is investigating non-silicon, high-mobility materials to increase carrier mobility within the device channels and improve overall transistor performance. High-mobility channels such as germanium and III-V compounds have the potential to operate at high speeds with low operating power and may be used in mainstream semiconductor CMOS technologies in the future. However, numerous manufacturing challenges associated with high-mobility channels such as processes, tools, device test structures and environment, safety, and health issues need to be addressed before these materials-based solutions are brought to manufacturing.

Since 2006, Poongsan and SEMATECH have partnered in tool and process development projects that have successfully demonstrated the technical merits of a high pressure annealing furnace. 

“Working with SEMATECH, we have demonstrated that high-pressure anneals are both effective and manufacturing-worthy approaches to high-k/Si interface defect passivation. From this work, we have gone on to develop and ship production-worthy annealing furnace tools to world-wide customers,” said Dr. Bob Wu, director of sales and marketing of Poongsan. “We look forward to continuing our strategic partnership with SEMATECH as we work toward developing emerging technologies and improving products.”

As a member of SEMATECH’s FEP program, located at the College of Nanoscale Science and Engineering (CNSE) of the University at Albany, Poongsan will collaborate with SEMATECH’s engineers and leverage SEMATECH’s activities in advanced test structures, advanced materials and device electrical characterization to improve processing technologies to increase mobility and reduce interfacial defects. Specifically, SEMATECH and Poongsan will collaborate on passivation of silicon and non-silicon gate stacks and other interfaces.

“To achieve better device performance and help shape the next generations of nanoelectronics, it’s necessary to partner to share know-how in materials, processing, equipment development and device technologies,” said Paul Kirsch, SEMATECH’s director of Front End Processes. “Poongsan’s proven expertise in high-pressure annealing processes will complement our own device and process expertise. We will work together on the technical and manufacturing gaps to address the continued scaling needs of today’s aggressive chip manufacturing market.”

The goal of SEMATECH’s FEP program is to provide novel leading-edge materials, processes, structural modules and electrical and physical characterization methods to support the continued scaling of logic and memory applications.

STMicroelectronics (NYSE: STM) announced today another milestone in its testing of its 28nm FD-SOI Technology Platform. Following the Company’s December announcement of the successful manufacturing of System on Chip (SoC) integrated circuits, ST today announced that application-processor engine devices manufactured at the Company’s Crolles, France fab, were capable of operating at 3GHz with even greater power efficiency at a given operating frequency than alternate technologies.

This announcement follows on the heels of recent announcements from other organizations to utilize FD-SOI technologies. Moore’s Law—the observation that the number of transistors on a chip doubled about every two years—has driven the semiconductor industry over the past 50 years to shrink the size of the transistors, which are essentially miniature on/off switches. The increased density from these size reductions have given consumers the explosion of new and more exciting features at lower-cost that we’ve come to expect. In parallel, these new features are able to operate at clock speeds that allow the phones to respond to your commands—by keypad, touchpad, and now voice—almost before you finish expressing the command.

Now, as those transistors shrink to nanoscale dimensions where about 450 transistors can fit within the diameter of a human hair, physics are challenging the traditional high-speed and low-power advantages of planar CMOS technology manufactured on bulk silicon wafers. FD-SOI technology is a major breakthrough in the pursuit of miniaturization of electronic circuits, and the achievement of 3GHz operating speed for an application-processor engine presages the adoption of FD-SOI in portable equipment, digital still cameras, gaming and ASICs for a range of applications. Of the next-generation process technologies, FD-SOI alone has proven its ability to meet the industry’s highest performance and lowest power demands that are vital to delivering graphics and multimedia that amaze without sacrificing battery life.

“As we had anticipated, FD-SOI is proving to be fast, simple and cool; we had fully expected to see 3GHz operating speeds, the design approach is very consistent with what we had been doing in bulk CMOS, and, with the benefits of fully depleted channels and back biasing, the low-power requirements are also meeting our expectations,” said Jean-Marc Chery, Executive Vice President, General Manager Digital Sector, and Chief Technology and Manufacturing Officer of STMicroelectronics.

Reinforcing the point of simplicity, ST has found porting Libraries and Physical IPs from 28nm Bulk CMOS to 28nm FD-SOI to be straightforward, and the process of designing digital SoCs with conventional CAD tools and methods in FD-SOI to be identical to Bulk, due to the absence of MOS-history-effect. FD-SOI enables production of highly energy-efficient devices, with the dynamic body-bias allowing instant switch to high-performance mode when needed and return to a very-low-leakage state for the rest of the time – all in a totally transparent fashion for the application software, operating system, and the cache systems. Finally, FD-SOI can operate at significant performance at low voltage with superior energy efficiency versus Bulk CMOS.

It is a fact that semiconductor industry capital spending is becoming more concentrated with a greater percentage of spending coming from a shrinking number of companies.  As a result, IC industry capacity is also becoming more concentrated and this trend is especially prevalent in 300mm wafer technology.  The figure below lists the 300mm installed capacity leaders for 2012 and IC Insights’ forecast for 2013.  The list was compiled and included in IC Insights’ updated report titled, Global Wafer Capacity 2013—Detailed Analysis and Forecast of the IC Industry’s Wafer Fab Capacity.    As shown, Samsung was by far the leader in 2012 having about 61% more 300mm capacity than second-place SK Hynix. Intel was the only other company that held a double-digit share of 300mm capacity at the end of 2012.  Assuming Micron is successful in acquiring Elpida in 1H13, the combined 300mm wafer capacity of the two companies will make the merged company the second-largest holder of 300mm capacity in the world behind Samsung.

 Of the top 10 companies on the list, half are primarily memory suppliers, two are pure-play foundries, and one company, Intel, is focused on MPUs.  Samsung is expected to maintain its lead in installed capacity through 2017, with aggressive capital spending plans seen over the past few years continuing over the next five years.  However, in terms of growth rate, IC Insights expects the largest increase in 300mm capacity to come from the pure-play foundries—TSMC, GlobalFoundries, UMC, and SMIC.  In total, IC Insights expects these four companies to more than double their collective 300mm wafer starts per month by 2017.

 IC Insights believes that the companies listed will represent essentially all the advanced 300mm IC production and capacity in the future.  IC Insights believes that the top seven or eight companies—Samsung, “Micron-Elpida,” TSMC, SK Hynix, Intel, Toshiba/SanDisk, and GlobalFoundries—can be considered an “elite” group that is just about guaranteed to be a driving force in 300mm capacity additions.  The remaining companies are likely to participate in future 300mm capacity expansion, but all have varying degrees of risk associated with fully realizing their long-term 300mm IC production capacity goals.

Meanwhile, there is still much uncertainty as to when the industry will make the next wafer-size transition—from 300mm to 450mm—and how much it will cost to do so, but momentum continues to build and the transition can now be considered certain to happen.  IC manufacturers have yet to fully optimize the high-volume manufacturing cost structure for the 300mm wafer size.  However, the potential per-die cost savings that the larger wafer can provide is enough of a motivating factor to make the transition happen.

3-D integration with nanostructuresResearchers at North Carolina State University have developed a new type of nanoscale structure that resembles a “nano-shish-kebab,” consisting of multiple two-dimensional nanosheets that appear to be impaled upon a one-dimensional nanowire. However, the nanowire and nanosheets are actually a single, three-dimensional structure consisting of a seamless series of germanium sulfide (GeS) crystals. The structure holds promise for use in the creation of new, three-dimensional (3-D) technologies.

The researchers believe this is the first engineered nanomaterial to combine one-dimensional and two-dimensional structures in which all of the components have a shared crystalline structure.

Combining the nanowire and nanosheets into a single “heterostructure” creates a material with both a large surface area and the ability to transfer electric charges efficiently. The nanosheets provide a very large surface area, and the nanowire acts as a channel that can transmit charges between the nanosheets or from the nanosheets to another surface. This combination of features means it could be used to develop 3-D devices, such as next-generation sensors, photodetectors or solar cells. This 3-D structure could also be useful for developing new energy storage technologies, such as next-generation supercapacitors.

“We think this approach could also be used to create heterostructures like these using other materials whose molecules form similar crystalline layers, such as molybdenum sulfide (MoS2),” says Dr. Linyou Cao, an assistant professor of materials science and engineering at NC State and co-author of a paper on the research. “And, while germanium sulfide has excellent photonic properties, MoS2 holds more promise for electronic applications.”

The process, Cao says, is also attractive because “it is inexpensive and could be scaled up for industrial processes.”

To create the nano-shish-kebabs, the researchers begin by creating a GeS nanowire approximately 100 nanometers in width. The nanowire is then exposed to air, creating nucleation sites on the wire surface through weak oxidation. The nanowire is then exposed to GeS vapor, which forms into two-dimensional nanosheets at each of the nucleation sites.

“Our next step is to see if we can create these heterostructures in other materials, such as MoS2,” Cao says. “We think we can, but we need to prove it.”

The paper, Epitaxial Nanosheet–Nanowire Heterostructures, was published online Feb. 18 in Nano Letters. The lead author is Dr. Chun Li, a former postdoctoral researcher at NC State. Co-authors are Yifei Yu, a Ph.D. student at NC State; Cao; and Dr. Miaofang Chi of Oak Ridge National Laboratory. The research was supported by the U.S. Army Research Office.

Stretched-out clothing might not be a great practice for laundry day, but in the case of microprocessor manufacture, stretching out the atomic structure of the silicon in the critical components of a device can be a good way to increase a processor’s performance.

Creating "stretched" semiconductors with larger spaces between silicon atoms, commonly referred to as "strained silicon," allows electrons to move more easily through the material. Historically, the semiconductor industry has used strained silicon to squeeze a bit more efficiency and performance out of the conventional microprocessors that power the desktop and laptop computers we use each day.

However, manufacturers’ inability to introduce strained silicon into flexible electronics has limited their theoretical speed and power to, at most, approximately 15GHz. Thanks to a new production process being pioneered by University of Wisconsin-Madison engineers, that cap could be lifted.

Professor develops flexible electronics"This new design is still pretty conservative," says Zhenqiang (Jack) Ma, a professor of electrical and computer engineering. "If we were more aggressive, it could get up to 30 or 40GHz, easily."

Ma and his collaborators reported their new process in Nature Scientific Reports on Feb. 18, 2013.

Ma endeavored to address a paradox for straining and doping silicon electronics built on a flexible substrate. The straining process is similar to stretching out a t-shirt: the researchers pull a layer of silicon over a layer of atomically larger silicon germanium alloy, which stretches out the silicon and forces spaces between atoms to widen. This allows electrons to flow between atoms more freely, moving through the material with ease-just as a t-shirt stretched over a dummy will have more space between threads, allowing it to breathe.

The problem comes during the doping process. This necessary step in semiconductor manufacturing introduces impurities that provide electrons that ultimately flow through the circuit. Doping a stand-alone sheet of strained silicon is like ironing a decal onto a stretched t-shirt. Just as an ironed-on design cracks when the t-shirt is stretched and unstretched, the act of doping distorts the flexible free-standing silicon sheet, limiting its stability and usefulness as a material for integrated circuits.

Ma believes that using the material to design next-generation flexible circuits will yield flexible electronics that offer much higher clock speeds at a fraction of the energy cost.

"We needed to dope this material in a way that the lattice structure within would not be distorted, allowing for silicon that is both strained and doped," says Ma.

The solution is akin to dying a pattern into the fabric of a shirt, rather than ironing it on after the fact. Ma and his UW-Madison collaborators — Max Lagally, the Erwin W. Mueller Professor and Bascom Professor of Surface Science and Materials Science and Engineering; and Paul Voyles, an associate professor of materials science and engineering — have developed a process through which they dope a layer of silicon, then grow a layer of silicon germanium on top of the silicon, then grow a final layer of silicon over that. Now, the doping pattern stretches along with the silicon.

"The structure is maintained, and the doping is still there," says Ma.

The researchers call the new structure a "constrained sharing structure." Ma believes that using the material to design next-generation flexible circuits will yield flexible electronics that offer much higher clock speeds at a fraction of the energy cost.

The next step will be to realize processors, radio frequency amplifiers, and other components that would benefit from being built on flexible materials, but previously have required more advanced processors to be feasible. "We can continue to increase the speed and refine the use of the chips in a wide array of components," says Ma. "At this point, the only limit is the lithography equipment used to make the high-speed devices."

Research and Markets announced the addition of the Global SiC Semiconductor Devices Market 2012-2016 report to their offering.

One of the key factors contributing to this market growth is the high demand of SiC in industrial applications. The global SiC semiconductor devices market has also been witnessing rapid technological advancement. However, the fluctuations in demand and supply could pose a challenge to the growth of this market.

Commenting on the report, an analyst from TechNavio’s Hardware team said: ”Rapid technological advancement is a fast-growing trend in the global silicon carbide (SiC) semiconductor devices market. The overall technological advancement in the electronics industry is growing at a faster rate, which has set the trends for technological advancement in SiC semiconductor devices. The fast-growing demands and changing end-user preferences over SiC semiconductor devices is leading to the trend of rapid technological advancement. Vendors need to continuously upgrade the technology and also implement new technologies.”

According to the report, the high demand for SiC semiconductors in industrial applications is one of the major growth drivers in the global SiC semiconductor devices market. Some of the industrial applications where SiC semiconductor usage is generating more interest for the vendors are in motor control and power conversion devices. This interest is mainly because of the low power loss properties of SiC semiconductors, which enhances the power conversion efficiency of electronic devices and also reduces carbon dioxide emissions. These benefits have replaced the usage of silicon in the above-mentioned applications. Furthermore, the application of SiC semiconductors has significantly reduced the size and weight of motors and power devices.

The key vendors dominating this market space are Cree Inc., GeneSiC Semiconductor Inc, Infineon Technologies AG., and ROHM Semiconductor

ISSCC, the International Solid-State Circuits Conference, is being held on February 17-21, 2013, at the San Francisco Marriott Marquis Hotel. This year, in honor of the conference’s 60th anniversary, we have assembled highlights of the topics and trends that are being discussed. Click through to learn more about the trends and challenges facing the solid-state integrated circuits industry in 2013.

David Su, subcommittee chair of ISSCC 2013, wrote on data rates of modern wireless standards, which are increasing rapidly, as is shown in the table above. The data rate has increased 100x over in the last decade and another 10x is projected in the next five years. Read more.

MORE HIGHLIGHTS FROM ISSCC 2013   >>>

DRS Technologies, Inc., a Finmeccanica Company, and Cypress Semiconductor Corp. (NASDAQ: CY) today announced that DRS will transfer its Microbolometer technology for uncooled infrared detectors to Cypress for high-volume manufacturing.

The proprietary production process, developed by the Network and Imaging Systems (NIS) division of DRS Technologies, will be transferred to Cypress’s 65nm Class 10 eight-inch wafer fabrication facility in Bloomington, Minnesota. The exclusive agreement will allow DRS Technologies to continue to improve sensor production by taking advantage of Cypress’s advanced manufacturing for significantly reduced wafer costs.

Cypress operates its own wafer fabrication facility in Bloomington, Minnesota, and offers access to this facility as a Specialty Foundry Solutions provider. This 8-inch wafer fab manufactures in high volume down to the 90-nm node with 65nm capability. It offers process technologies that integrate SONOS-based non-volatile memory and precision analog/mixed signal capabilities. The facility can handle ITAR material, and has been accredited as a Category 1A Trusted Fab for fabrication, design, and testing of U.S. DoD Trusted Microelectronics.

“The partnership with Cypress will allow us to better meet the growing demands of the thermal imaging market,” said NIS President Mike Sarrica. “With our advanced, proprietary microbolometer production process and Cypress’s proven technology and manufacturing expertise, we can achieve the high-volume, high yield and low-cost capabilities that have become requirements of both the commercial and military markets.”

DRS and Cypress expect to have qualified product by early 2014.

“This partnership validates Cypress’s commitment to high-quality, low-cost manufacturing in the United States”, said Minh Pham, executive vice president of Worldwide Manufacturing at Cypress. “This partnership expands our base of foundry customers for our Minnesota wafer fab, and will add new MEMS processing capabilities to support fabrication of Microbolometers. We expect growth in our wafer foundry business as more companies see the value and service we can offer.”

Yole Développement announced its Emerging Non-Volatile Memories report. Yole Développement’s report provides an analysis of the emerging nonvolatile memories (NVM) five applications fields that will fuel market growth and a description and forecasts of the four emerging NVM (MRAM, PCM, RRAM, FeRAM) technologies. It also analyzes the competitive landscape for both standard memories (DRAM and NAND) and emerging NVM with expected dynamic for the future.

Higher-density NVM chips will spawn many new applications and increase the business ten-fold in just five years

This Yole Développement report describes why and how emerging NVM (FRAM, MRAM/STTMRAM, PCM, RRAM) will be increasingly used in various markets: industrial and transportation, enterprise storage, smart card, mobiles phones and mass storage.

Until recently, only FRAM, PCM and MRAM were industrially produced and available in low-density chips to only a few players. Thus the market was quite limited and considerably smaller than the volatile DRAM and non-volatile Flash NAND dominant memory markets (which enjoyed combined revenues of $50B +in 2012).

However, in the next five years the scalability and chip density of those memories will be greatly improved and will spark many new applications, with the following NVM market drivers explained in detail in this report:

  • With the adoption of STT MRAM and PCM Cache memory, enterprise storage will be the largest NVM market. NVM will greatly improve the input/output performance of enterprise storage systems whose requirements will intensify with the growing need for web-based data supported by cloud servers.
  • Mobile phones will increase its adoption of PCM as a substitute to flash NOR memory in MCP packages thanks to 1GB chips made available by Micron in 2012. Higher-density chips, expected in 2015, will allow access to smart phone applications that are quickly replacing entry-level phones. STTMRAM is expected to replace SRAM in SoC applications thanks to lower power consumption and better scalability.
  • Smart card MCU (microcontrollers) will likely adopt MRAM/STTMRAM and PCM as a substitute to embedded flash. Indeed, flash memory cell-size reduction is limited for the future. NVM could reduce the cell size by 50% and thus be more cost-competitive. Additional features like increased security, lower power consumption and higher endurance are also appealing NVM attributes.
  • Mass storage markets served by flash NAND could begin using 3D RRAM in 2017-2018, when 3D NAND will slow down its scalability as predicted by all of the main memory players. When this happens, a massive RRAM ramp-up will commence in the next decade that will replace NAND, if sufficient 3D RRAM cost-competiveness and chip density are available. Overall, the global emerging non-volatile memory market will grow from $209M in 2012 to $2B in 2018, equating to an impressive growth of + 46 %/year. Nevertheless, this is a forecast based on a conservative scenario, and the report also provides a best-case scenario for an even broader adoption of NVM.

MRAM/STTMRAM and PCM will lead the NVM market, reaching a combined $1.6B by 2018

Market adoption of memory is strongly dependent on its scalability. This Yole Développement report provides a precise memory roadmap in terms of technological nodes, cell size and chip density for each NVM (FRAM, MRAM/STTMRAM, PCM, RRAM). A market forecast is provided for each technology by application, units, revenues and also # of wafers. A comprehensive review of the latest technical developments of every main player is presented in order to understand the technology’s status and the main technical challenges.

“By 2018, MRAM/STTMRAM and PCM will surely be the top two NVM on the market. Combined, they will represent a $1.6B business by 2018, and their sales will almost double each year, with double-density chips launched every two years,” explains Yann de Charentenay, Senior Technology and Market Analyst at Yole Développement.

FeRAM will grow at a steadier growth rate (+10%/ year) and will focus on industrial & transportation applications because of the low-density available. RRAM revenues won’t really surge until 2018, with the availability of high-density chips of several 10’s of Gb that could replace NAND technology.

Giant memory manufacturers and start-up companies compete on technology development

The memory supply chain has been highly concentrated in the last 10 years, supporting a huge price/Gb decrease (-20 to 40 %/year for NAND and DRAM). Five players (Samsung, Micron, SK Hynix, Toshiba and SanDisk) hold 90 % of DRAM and NAND sales. These leading players will have a key role in the competitive landscape of emerging NVM. This report identifies and positions the key emerging NVM players based on the technology developed, market presence (new entrant or established memory player), and targeted markets. The supply chain dynamic is analyzed in order to understand who today’s key market players are in each application and technology, and to illustrate how the competitive landscape will evolve.