Category Archives: Semiconductors

Intersil restructuring to cut 18% of workforceIntersil Corporation (NASDAQ: ISIL) today announced restructuring initiatives designed to prioritize the company’s sales and development efforts, strengthen financial performance and improve cash flow.

The restructuring plan includes a reduction of approximately 18% of Intersil’s worldwide workforce and a reduction of approximately $30 million in annual operating expenses, according to the SEC filing. Currently, Intersil employs approximately 1,700 employees, according to their company website. The estimated 18% reduction would involve around 300 jobs. Intersil has not released a statement about where the workforce reduction would come from within the company.

The restructuring plans will be substantially completed during the first quarter of 2013 and are expected to reduce annual operating expenses by approximately $30 million. A restructuring charge of approximately $15 million for severance-related benefits is expected during the first quarter of 2013.

"Today’s market requires us to sharpen our focus on core strengths and markets where we can offer superior value to our customers," said Jim Diller, Interim President and Chief Executive Officer, of the restructuring initiatives. "Today, we are announcing plans designed to ensure that Intersil remains well-positioned and appropriately structured for sustainable, long-term growth and profitability."

This is not the first time that Intersil, which specializes in the design and manufacture of high-performance analog, mixed-signal and power management semiconductors, has had to cut workforce in an effort to improve cash flow, though it is a more substantial reduction than their most recent restructuring efforts. Intersil reduced their workforce by 9% in 2008, in response to the economic conditions of the day, and then again in May 2012, with a workforce reduction of 11%.

Intersil has locations in California, Florida, China, Malaysia, Japan, Germany and the United Kingdom.

Infineon Technologies AG (FSE: IFX / OTCQX: IFNNY) has achieved a breakthrough in the manufacturing of power semiconductors on 300-millimeter thin wafers. In February, the company received the first customer go-aheads for products of the CoolMOS family produced by the 300-millimeter line at their site in Villach, Austria. The production process based on the new technology has completed qualification from start to finish and customers have given the go-ahead.

"Infineon put its faith in this manufacturing technology very early on and continued to invest even in economically difficult times. The qualification of our entire 300-millimeter line represents a veritable leap ahead of the competition," says Dr. Reinhard Ploss, CEO of Infineon Technologies AG. "300-millimeter thin-wafer manufacturing for power semiconductors will enable us, with the corresponding demand, to seize the opportunities that the market offers."

Infineon is the first and only company worldwide to produce power semiconductors on 300-millimeter thin wafers. Thanks to their larger diameter compared to standard 200-millimeter wafers, two-and-a-half times as many chips can be made from each one. Power semiconductors from Infineon feature low energy loss and compact design. Although not much thicker than a sheet of paper, the chips have electrically active structures on the front and back.

The next step is for the present manufacturing concept for CoolMOS products, qualified from start to finish, with the front-end site Villach and assembly of the thin chips at the back-end site Malacca, Malaysia, to be expanded to the front-end site Dresden. Here the focus is on high-volume production in a fully automated 300-millimeter line. The basis for the processes required and the manufacturing technology is currently being developed in research projects in Dresden. The technology transfer to Dresden is running on schedule and qualification of the first CoolMOS products will be completed in March. Shortly, in Villach more power semiconductor technologies will be transferred to the 300-millimeter line and produced. The development of the next power technology generation will focus on 300 instead of 200-millimeter technology.

"Our ability to innovate is the basis of our success – good ideas are turned into reality,” says Ploss. “In both Austria and in Saxony, we have the necessary conditions for this: technological know-how, well-educated and highly motivated specialists and exemplary support from government policy."

Last year, the independent research institute IMS Research (an IHS company) named Infineon as a market leader in power semiconductors. Infineon develops semiconductor and system solutions addressing three central challenges to modern society: energy efficiency, mobility, and security. In the 2012 fiscal year, ending September 30, the Company reported sales of Euro 3.9 billion with close to 26,700 employees worldwide.

Lithography scientists, engineers, and developers — long accustomed to working years ahead in order to meet industry needs — face keen challenges, with meeting user expectations, enabling new capabilities, and controlling costs at the top of the list. SPIE Advanced Lithography, the annual forum for discussions on meeting the challenges in developing state-of-the-art lithographic tools, resists, metrology, materials characterization, and design and process integration, will bring the community together in San Jose, California, to address those issues. The event will run February 24-28 at the San Jose Convention Center and San Jose Marriott Hotel.

Symposium chair Harry Levinson of GLOBALFOUNDRIES said organizers anticipate interest in several topics in particular, including:

  • Designing with multi-patterning and directed self-assembly (DSA): beyond SEMs toward real chips
  • Line edge roughness: clearly a concern of many and the focus of a session in the conference on Advanced Etch Technology for Nanopatterning.
  • Resist limits: secondary electrons, tradeoffs among resolution, line-edge roughness and exposure speed.

However, Levinson noted, “To be honest, the real buzz usually comes from something unexpected, which is probably one of the best reasons for attending Advanced Lithography!”

With the presence of leaders from companies such as Intel, Samsung, ASML, Taiwan Semiconductor Manufacturing Corp., and other companies that have announced large investment strategies in new technology, “unexpected” topics might include R&D toward photonics integrated circuits versus silicon photonics, retooling for 450mm wafers, or power-source issues in EUV (extreme ultraviolet) tools.

In addition to featured speakers and more than 560 technical talks, the event will include panel discussions on disruptive and emerging technologies, full- and half-day short courses on lithography topics, interactive poster paper receptions, and a 60-company exhibition showcasing many of the industry’s top semiconductor suppliers, integrators, and manufacturers. The exhibition will run Tuesday and Wednesday, February 27 and 28.

Plenary presentations from leaders in the lithography industry include:

  • Bill Siegle, Independent Consultant and ASML Advisory Board Member: “Contact printing to EUV: lessons learned from the art of lithography”
  • Howard Ko, Senior VP and General Manager, Synopsys Silicon Engineering Group: “The evolution of EDA alongside rapid silicon technology innovation”
  • Charles Szmanda, The Patent Practice of Szmanda & Shelnut, LLC: “The new U.S. patent law: what you need to know and how it will affect your strategy.”
  • Technical talks are organized into seven conferences:
  • Alternative Lithographic Technologies
  • Extreme Ultraviolet Lithography
  • Metrology, Inspection, and Process Control for Microlithography
  • Advances in Resist Materials and Processing Technology
  • Optical Microlithography
  • Design for Manufacturability through Design-Process Integration
  • Advanced Etch Technology for Nanopatterning

Accepted papers will be published in the SPIE Digital Library as soon as approved after the meeting, and in print volumes and digital collections.

Experts present advances in lithography at SPIE 2013SEMATECH experts will present research and development results on extreme ultraviolet (EUV) manufacturability and extendibility, alternative lithography, and related areas of metrology at the SPIE Advanced Lithography 2013 conferences taking place February 25-28 at the San Jose Convention Center and Marriott in San Jose, CA.

“We are enthusiastic about sharing our progress on some of the most critical aspects of the development of EUV infrastructure,” said Stefan Wurm, director of lithography at SEMATECH. “SEMATECH lithographers will recount achievements in multiple areas of EUV to further enable EUVL pilot line readiness and advance EUV extendibility.”

SEMATECH engineers will report progress on EUV mask infrastructure, manufacturability, extendibility and metrology, and will showcase some of their findings in over 30 papers and posters demonstrating breakthrough results in exposure tool capability, resist advances, defect-related inspection, e-beam and nanoimprint. 

More importantly, the results presented will be instrumental in driving timely creation of the remaining infrastructure required to bring EUV to production. In one area of investigation, technologists from SEMATECH’s Mask Blank Development Center will report progress with its multilayer deposition process, including recent defect printability results from an NXE3100 tool with comparison of the imaging to various simulation modeling approaches.

Other SEMATECH papers will showcase advances in metrology techniques, photoresist shrinkage, nanopolishing, scatterometry, through-silicon via (TSV) reveal, transmission electron microscopy (TEM) tomography, critical dimension atomic force microscopy (CD-AFM), critical dimension X-ray scattering (CD-SAXS)—a potential metrology technique for FinFET and 3D memory structures—and a through-focus scanning optical microscopy (TSOM) technique being explored for future defect inspection or to enable high-volume manufacturing of high-aspect ratio features.

Additionally, technologists will present a “big picture” CD metrology gaps analysis, which interrelates the combined results from years of SEMATECH CD metrology studies to summarize the outlook for various tool technologies for different applications.

“We will be showcasing impressive metrology advances achieved through collaborative research, as well as revealing new defect characterization results for EUV mask blanks that form the basis of the technology for SEMATECH’s new Nanodefect Center,” said Michael Lercel, senior director of nanodefectivity and metrology at SEMATECH.

Among the global semiconductor community’s leading gatherings, the SPIE conference series attracts thousands of specialists in various aspects of lithography and related metrology, two of the most challenging areas of advanced microchip production.

Gigaphoton, Inc., a major lithography light source manufacturer, announced today that the company has achieved EUV light output equivalent to maximum of 20W for its laser-produced plasma, or LPP light sources for EUV lithography scanners. This result was obtained by irradiating the Sn target with a solid-state pre-pulse laser and a CO2 laser at 100kHz. An average EUV output of 10W was confirmed during operation. Considering that the current commercially accepted EUV output levels are around 10W, the results demonstrated by Gigaphoton represents that a critical milestone has been reached for pre-production level output.

Gigaphoton has focused on developing high output, stable, and economical LPP light sources since 2002. Since that time, Gigaphoton has introduced several unique technologies including the development of on-demand tin droplets generator with droplets measuring less than 20μm, the combining of short wavelength solid-state pre-pulse lasers and CO2 lasers as a main pulse and the utilization of magnetic field for debris mitigation.

The unique LPP light source technology introduced by Gigaphoton extends the lifetime of droplet generators by utilizing ultra-small tin droplets on-demand, reducing downtime and cost. In addition, high EUV output conversion efficiency has been achieved through the optimized combination of short wavelength solid-state pre-pulse laser and CO2 laser as the main pulse. This technology contributes to the real possibility of achieving efficient, high output EUV light sources. In order to maximize the life of the collector mirror, a superconducting magnet is used to generate a powerful magnetic field that guides the unwanted debris resulting from the thermal expansion of the tin droplets towards the tin catcher. This results in further reduction of cost and downtime.

"The fact that our unique LPP light source technology is now able to achieve the level of EUV output matching that of today’s pre-production performance, proves that our vision for high output, low running cost, stable LPP light sources are indeed achievable," said Hitoshi Tomaru, President and CEO of Gigaphoton. "Our efforts will help to bring the industry closer to realizing mass production level EUV lithography scanners. We are making firm progress towards our entry into the EUV light source business – focusing on technology development to accommodate the future industry needs."

The latest details of Gigaphoton’s LPP light source technology will be presented at the SPIE Advanced Lithography 2013, being held in San Jose, California from February 24 through the 28.  Gigaphoton has developed and delivered DUV laser light sources used by major semiconductor chipmakers in the Pan-Asian, US and European regions since its founding in 2000.

Gas chromatograph by ShimadzuShimadzu Corporation today introduced the Tracera, a high-sensitivity gas chromatograph. Tracera is equipped with the newly developed barrier discharge ionization detector (BID), which is capable of detecting all types of trace organic and inorganic compounds, with the exception of helium (He) and neon (Ne), at the 0.1 ppm level (i.e. sub-ppm, where ppm refers to parts per million). Tracera GC is applicable for many types of high-sensitivity analyses typically performed with GC systems incorporating multiple detectors.

Background to Development

Gas chromatographs are used for research and development and quality control in a number of fields, involving petrochemistry, fine chemicals, the environment, pharmaceuticals, foods, electronics/semiconductors, and fragrances. In recent years, demands for higher sensitivity and trace quantity analyses have increased.

Thermal conductivity detectors (TCD) and flame ionization detectors (FID) are general-purpose detectors used in conventional gas chromatographs. A TCD detects a variety of inorganic and organic compounds, excluding the carrier gas component, but the sensitivity is insufficient. An FID is capable of detecting trace components at the ppm level, but can only detect organic compounds (excluding formaldehyde and formic acid). Analysis has thus required complex systems incorporating a variety of detectors to suit the target component.

With this issue in mind, Shimadzu has investigated the basics of plasma detection technology as a means for increasing sensitivity stability and the detectable concentration range. This has resulted in the barrier discharge ionization detector (BID), a new detector capable of the high-sensitivity detection of both organic and inorganic compounds, while providing excellent durability.

"The Tracera is a ground-breaking new system that combines this new type of detector, offering features not provided by conventional detectors, with the Shimadzu GC-2010 Plus high-performance capillary gas chromatograph," Said Masahito Ueda, general manager of GC & TA Business Unit, Analytical & Measuring Instruments Division. "It is expected to improve the efficiency of high-sensitivity, trace-quantity analyses, and to reduce equipment and analysis costs."

Main Features of This System

High Sensitivity—Achieves detection sensitivity over 100 times that of TCD, and over twice that of FID

The built-in barrier discharge ionization detector (BID) generates helium plasma. The extremely high photon energy of this plasma ionizes the sample components, enabling high-sensitivity detection. This system achieves at least 100 times the sensitivity of a conventional TCD, and at least twice the sensitivity of FID, enabling the detection of all types of trace components at the 0.1 ppm level.

Universal Detector—Capable of detecting both organic and inorganic compounds with no difference in sensitivity

The new BID helium plasma has an extremely high energy. It can detect all organic and inorganic compounds, with the exception of He and Ne, with no difference in sensitivity. It improves analysis sensitivity even with aldehydes, alcohols, and halides, for which sensitivity decreases with FID. A single Tracera system can perform analyses that conventionally required complicated systems equipped with multiple detectors and units. Examples include the analysis of hydrogen and organic compounds such as formic acid, generated as part of the reaction process during artificial photosynthesis, and the analysis of low concentration hydrocarbons and permanent gases generated in lithium ion rechargeable batteries.

Long-Term Stability—Adopts electrode-preserving plasma generation technology

With the new BID, the plasma is generated inside a quartz tube, so it makes no contact with the discharge electrode used for plasma generation. As a result, the detector electrode is not degraded, achieving long-term analytical stability.

The relentless march of process technology brings more integration and performance. IBM’s System z processor leads the charge at ISSCC 2013 clocking in at 5.7GHz and with 2.75B transistors.

The chip complexity chart below shows the trend in transistor integration on a single chip over the past two decades. While the 1 billion transistor integration mark was achieved some years ago, we now commonly see processors with beyond 2B transistors on a die.

Leveraging sophisticated strategies to lower leakage and manage voltage, variability and aging, has bolstered the continuing reduction in total power dissipation. This is helping rein in the increase in energy demands from PCs, servers, and similar systems. As power reduction becomes mandatory in every application, the trend towards maintaining near-constant clock frequencies also continues as shown below in frequency trends plot. This will yield solutions with less cost and cooling demands, resulting in greener products in the future.

Processors are choosing to trade off performance by lowering supply voltage. The performance loss of reduced voltage and clock frequency is compensated by further increased parallelism. Processors with more than eight cores are now commonplace. This year at ISSCC 2013, a 24-core processor from Fudan University will be presented as noted in the core count trend chart below.

In addition to the trend to integrate more cores on a single chip, multiple die within a single package are appearing. In ISSCC 2013, IBM will present a multi-chip module with six CPUs and two embedded DRAM cache chips. As well, dedicated co-processing units for graphics and communications are now commonly integrated on these complex systems-on-chip. Design of these SoCs requires broad collaboration across multiple disciplines including circuits, architecture, graphics, process technology, package, system design, energy efficiency and software. New performance and power-efficient computing techniques continue to be introduced at targeted, critical applications such as floating point and SIMD.

As technology continues to scale to finer dimensions, large caches are being integrated into microprocessor die.

Methods to communicate within-die as well as cross-die are becoming increasingly important. This is being driven by two trends: (1) 3D integration continues to grow in interest and (2) intra-die communications become more challenging with process scaling due increases in delay per unit interconnect length. Work on bringing package-level inter-chip transport onto the die has been gaining in popularity and we see this trend continuing.

This and other related topics will be discussed at length at ISSCC 2013, the foremost global forum for new developments in the integrated-circuit industry. ISSCC, the International Solid-State Circuits Conference, will be held on February 17-21, 2013, at the San Francisco Marriott Marquis Hotel.

ISSCC 2013: Memory trends


February 15, 2013

We continue to see progressive scaling in embedded SRAM, DRAM, and floating-gate based Flash for very broad applications. However, due to the major scaling challenges in all mainstream memory technologies, we see a continued increase in the use of smart algorithms and error-correction techniques to compensate for increased device variability. In further response to these challenges, we see logic processes adopting FinFET devices along with read- and write-assist circuits in SRAMs. Emerging memory technologies are making steady progress towards product introductions, including PCRAM and ReRAM, while STT-MRAM is beginning to become a strong candidate for both standalone and embedded applications.

SRAM

Embedded SRAM continues to be a critical technology enabler for a wide range of applications from high performance computing to mobile applications. The key challenges for SRAM include VCCMIN, leakage and dynamic power reduction while relentlessly following Moore’s law to shrink the area by 2× for every technology generation. As the transistor feature size marches toward sub-30nm, device variation has made it very difficult to shrink the bit cell size at the 2× rate while maintaining or lowering VCCMIN between generations. Starting at 45nm, the introduction of high-k metal-gate technology reduces the Vt mismatch and enables further device scaling by significantly reducing the equivalent oxide thickness. Starting at 22nm and beyond, new transistors such as FinFETs and fully-depleted SOI are key to enabling the continuous scaling of bit cell area and low voltage performance. Design solutions such as read/write assist circuitry have been used to improve SRAM VCCMIN performance starting at 32nm. New SRAM bit cells with more than 6 transistors have also been proposed to minimize operating voltage. For example, 8T register file cells have been reported in recent products requiring low VCCMIN. Dual-rail SRAM design emerges as an effective solution to enable dynamic voltage-frequency scaling (DVFS) by decoupling logic supply rails from SRAM arrays and thus allowing much wider operating window. It is important for SRAM to reduce both leakage and dynamic power, keeping products within the same power envelope at the next technology node. Sleep transistors, fine-grain clock gating and clock-less SRAM designs have been proposed to reduce leakage and dynamic power. Redundancy and ECC protection are also keys to ensure yield and reliability when embedded SRAM products go to production. Figure 1 shows the SRAM bit cell scaling trend on the left axis and the SRAM VDD scaling trend on the right axis, using data from major semiconductor manufacturers.

High-Speed I/O for DRAM

In order to reduce the bandwidth gap between main memory and processor frequencies, external data rates continue to increase as conventional high-speed wired interface schemes such as DDR(x) and GDDR(x) for DRAM evolve (Figure 2). Currently GDDR5 and DDR4 memory I/Os operate around 7Gb/s/pin and 3Gb/s/pin, respectively. To achieve higher speed data transfer rate, signal integrity techniques such as crosstalk, noise and skew cancellation, and speed enhancement techniques such as equalizer and pre-emphasis have been developed. These advanced techniques have pushed I/O speeds towards 10Gb/s/pin. Lower power consumption for data center and mobile applications is also pursued. A near ground signaling method, termination impedance optimization, decision feedback equalizer, and clock-feathering slew rate control technologies have been demonstrated to reduce the power dissipation of memory interfaces significantly, while achieving high bandwidth.

Nonvolatile Memories

In the past decade significant focus has been put on the emerging memories field to find a possible alternative to floating gate nonvolatile memory (NVM). The emerging NVMs, such as phase-change memory (PRAM), ferroelectric RAM (FeRAM), magnetic spin-torque-transfer RAM (STT-MRAM), and resistive memory (ReRAM), are showing potential to achieve high cycling capability and lower power per bit for both read and write operations. Some commercial applications, such as cellular phones, have recently started to use PRAM, demonstrating that reliability and cost competitiveness in emerging memories is becoming a reality. Fast write speed and low read-access time are being achieved in many of these emerging memories. At ISSCC 2013, a 32Gb ReRAM cross-point array is demonstrated in 24nm technology. Figures 3 and 4 provide a summary on the scaling trends for both bandwidth and density in emerging memories.

 

NAND Flash Memory

NAND Flash memory continues to advance towards higher density and lower power, resulting in low-cost storage solutions that are enabling the replacement of traditional hard-disk storage with solid-state disks (SSDs). Multiple bits per cell has proven to be effective in increasing the density. Figure 5 shows the observed trend in NAND Flash capacities presented at ISSCC over the past 18 years. With scaling, device variability and error rates increase, requiring system designers to develop sophisticated control algorithms to offset this trend. Some of these are implemented outside the NAND silicon in the system memory controller, especially ECC and data management methods, for improved overall reliability. Possible future scenarios include 3D stacked NAND vertical gates as a solution to further increase the NAND density.

This and other related topics will be discussed at length at ISSCC 2013, the foremost global forum for new developments in the integrated-circuit industry. ISSCC, the International Solid-State Circuits Conference, will be held on February 17-21, 2013, at the San Francisco Marriott Marquis Hotel.

STM headquartersSTMicroelectronics, or STM, a global semiconductor supplier, announced today that it had reached agreement with Hyundai Autron, the electronics subsidiary of Hyundai Motors Group of Korea, to collaborate together to develop world-class electronic control systems for automotive applications.

ST and Hyundai Autron engineers are beginning the project by targeting semiconductors for power-train applications and specifically for engine management units. The two companies are simultaneously exploring expanding the cooperation into other applications. The effort is starting with using existing ST Application Specific Standard Products in new-generation vehicles expected to sample later this year; jointly-designed products should begin to appear soon after.

ST brings its market-tested, reliable automotive technologies, including industry-leading smart-power technologies, such as BCD (Bipolar-CMOS-DMOS) to the cooperation. The ST’s smart-power technologies enable effective integration of interface, control, and communication functions together with the power-driver section and a cost-effective implementation of distributed intelligence.

"With electronic systems playing an increasing role in precise vehicle control, outstanding quality and modest cost are both critical to success," said Myunghee Lee, Sr. Vice President of Hyundai Autron. "As a long-time, leading player in automotive and a reliable partner with a broad technology portfolio, in-house manufacturing and proven commitment to automotive, ST was a good fit for us."

"Hyundai Autron, like ST, is highly focused on quality and value in its products and both companies believe ST’s world-class technology, reliability, manufacturing strength and design expertise can make a significant contribution to one of the fastest-growing car brands globally," said Marco Monti, executive vice-president and general manager of STMicroelectronics Automotive Product Group. "We are excited to begin our journey with Hyundai Autron and look forward to helping them achieve their goals."

ST’s automotive products span a broad range of technologies, such as proprietary BCD Smartpower; advanced CMOS; embedded flash; VIPower for motor and LED-lighting control, power discretes (low- and high-voltage silicon, SiC, GaN), CMOS imaging, and MEMS motion sensors used throughout advanced chassis controls, safety systems and navigation devices.

MEMS APIX new productAnalytical Pixels Technology (APIX) today announced the release of its first commercial product: GCAP, a gas chromatography device designed for a variety of industrial and petrochemical applications, including process monitoring, energy distribution, safety and security and environmental control.

This device, designed, assembled and tested by APIX, is based on nano-scale silicon components licensed from the CEA-Leti and the California Institute of Technology (Caltech). The silicon components are manufactured in Leti’s advanced semiconductor facility in Grenoble and system assembly and test are performed in APIX’s facility in Grenoble.

“GCAP’s very flexible, versatile architecture, based on high-density silicon columns and sensors, means GCAP can be configured to perform in a number of different modes, including conventional, multi-dimensional or concurrent analysis,” said Dr. Pierre Puget, APIX co-founder and CTO. “This makes it the ideal tool for research laboratories, advanced gas analysis, and complex applications such as biomedical screening.”

“One of GCAP’s key features is its ability to work with a number of different carrier gases,” Puget continued. “This is made possible by the extreme sensitivity of the silicon nano-scale sensors at the heart of the system.”

In particular, the ability of GCAP to work with scrubbed air as a carrier gas in lieu of expensive, cumbersome bottled gases allows easy in-situ deployment, nearly real-time analysis, and a significant reduction in operating costs.

Additional major features of GCAP include its ability to:

–      separate and precisely quantify individual molecules among hundreds of interfering substances, depending on architectural configurations

–      limit detection for most chemical compounds below 1 parts-per-million without pre-concentration and in the parts-per-billion range with pre-concentration

–      reduce the volume of analyte required to less than 10 microliters, and the volume of carrier gas to less than 1 milliliter

–      analyze most chemicals is less than one minute

The performance of GCAP, which is available for beta testing, has been demonstrated with alkanes, permanent gases, volatile organic compounds and other materials. 

Analytical Pixels Technology (APIX) was created in 2011 to manufacture and sell gas chromatography products based on joint research by CEA-Leti and Caltech. APIX-designed silicon devices are manufactured at Leti’s Grenoble, France site. APIX is headquartered in Grenoble and has engineering and business operations in the United States.